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1. 发明申请

US20060163631A1 Vertical MOSFET with dual work function materials 失效
标题翻译：具有双功能材料的垂直MOSFET
公开(公告)号：US20060163631A1
公开(公告)日：2006-07-27
申请号：US10622477
申请日：2003-07-18
申请人： Xiangdong Chen , Geng Wang , Yujun Li , Qiqing Ouyang
发明人： Xiangdong Chen , Geng Wang , Yujun Li , Qiqing Ouyang
IPC分类号： H01L29/94
CPC分类号： H01L29/66181 , H01L27/10864
摘要： A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical pass transistor for the DRAM cell incorporates two gate materials having different work functions. The gate material near the storage node is n-type doped polysilicon. The gate material near the bit line diffusion is made of silicide or metal having a higher work function than the n-polysilicon. The novel device structure shows several advantages: the channel doping is reduced while maintaining a high Vt and a low sub-threshold leakage current; the carrier mobility improves with the reduced channel doping; the body effect of the device is reduced which improves the write back current; and the sub-threshold swing is reduced because of the low channel doping.
摘要翻译：在DRAM单元中使用的用于保持低总漏电流并提供足够的驱动电流的垂直传输晶体管与制造这种器件的方法一起被描述。晶体管栅极被设计代替通道。用于DRAM单元的垂直传输晶体管包括具有不同功函数的两个栅极材料。存储节点附近的栅极材料为n型掺杂多晶硅。位线扩散附近的栅极材料由具有比n-多晶硅更高的功函数的硅化物或金属制成。该新颖的器件结构显示出几个优点：沟道掺杂减少，同时保持高Vt和低的亚阈值漏电流; 载流子迁移率随着沟道掺杂的降低而提高; 减少了器件的体效，提高了回写电流; 并且由于低通道掺杂，子阈值摆幅减小。

2. 发明申请

US20070051996A1 METHOD OF FORMING A MOSFET WITH DUAL WORK FUNCTION MATERIALS 有权
标题翻译：形成具有双功能功能材料的MOSFET的方法
公开(公告)号：US20070051996A1
公开(公告)日：2007-03-08
申请号：US11553072
申请日：2006-10-26
申请人： Xiangdong Chen , Geng Wang , Yujun Li , Qiqing Ouyang
发明人： Xiangdong Chen , Geng Wang , Yujun Li , Qiqing Ouyang
IPC分类号： H01L29/94
CPC分类号： H01L29/66181 , H01L27/10864
摘要： A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical pass transistor for the DRAM cell incorporates two gate materials having different work functions. The gate material near the storage node is n-type doped polysilicon. The gate material near the bit line diffusion is made of silicide or metal having a higher work function than the n-polysilicon. The novel device structure shows several advantages: the channel doping is reduced while maintaining a high Vt and a low sub-threshold leakage current; the carrier mobility improves with the reduced channel doping; the body effect of the device is reduced which improves the write back current; and the sub-threshold swing is reduced because of the low channel doping.
摘要翻译：在DRAM单元中使用的用于保持低总漏电流并提供足够的驱动电流的垂直传输晶体管与制造这种器件的方法一起被描述。晶体管栅极被设计代替通道。用于DRAM单元的垂直传输晶体管包括具有不同功函数的两个栅极材料。存储节点附近的栅极材料为n型掺杂多晶硅。位线扩散附近的栅极材料由具有比n-多晶硅更高的功函数的硅化物或金属制成。该新颖的器件结构显示出几个优点：沟道掺杂减少，同时保持高Vt和低的亚阈值漏电流; 载流子迁移率随着沟道掺杂的降低而提高; 减少了器件的体效，提高了回写电流; 并且由于低通道掺杂，子阈值摆幅减小。

3. 发明授权

US07294879B2 Vertical MOSFET with dual work function materials 失效
标题翻译：具有双功能材料的垂直MOSFET
公开(公告)号：US07294879B2
公开(公告)日：2007-11-13
申请号：US10622477
申请日：2003-07-18
申请人： Xiangdong Chen , Geng Wang , Yujun Li , Qiqing C. Ouyang
发明人： Xiangdong Chen , Geng Wang , Yujun Li , Qiqing C. Ouyang
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L29/66181 , H01L27/10864
摘要： A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical pass transistor for the DRAM cell incorporates two gate materials having different work functions. The gate material near the storage node is n-type doped polysilicon. The gate material near the bit line diffusion is made of silicide or metal having a higher work function than the n-polysilicon. The novel device structure shows several advantages: the channel doping is reduced while maintaining a high Vt and a low sub-threshold leakage current; the carrier mobility improves with the reduced channel doping; the body effect of the device is reduced which improves the write back current; and the sub-threshold swing is reduced because of the low channel doping.
摘要翻译：在DRAM单元中使用的用于保持低总漏电流并提供足够的驱动电流的垂直传输晶体管与制造这种器件的方法一起被描述。晶体管栅极被设计代替通道。用于DRAM单元的垂直传输晶体管包括具有不同功函数的两个栅极材料。存储节点附近的栅极材料为n型掺杂多晶硅。位线扩散附近的栅极材料由具有比n-多晶硅更高的功函数的硅化物或金属制成。该新颖的器件结构显示出几个优点：沟道掺杂减少，同时保持高Vt和低的亚阈值漏电流; 载流子迁移率随着沟道掺杂的减少而提高; 减少了器件的体效，提高了回写电流; 并且由于低通道掺杂，子阈值摆幅减小。

4. 发明授权

US07354822B2 Method of forming a MOSFET with dual work function materials 有权
标题翻译：用双功能材料形成MOSFET的方法
公开(公告)号：US07354822B2
公开(公告)日：2008-04-08
申请号：US11553072
申请日：2006-10-26
申请人： Xiangdong Chen , Geng Wang , Yujun Li , Qiqing C. Ouyang
发明人： Xiangdong Chen , Geng Wang , Yujun Li , Qiqing C. Ouyang
IPC分类号： H01L21/8242
CPC分类号： H01L29/66181 , H01L27/10864
摘要： A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical pass transistor for the DRAM cell incorporates two gate materials having different work functions. The gate material near the storage node is n-type doped polysilicon. The gate material near the bit line diffusion is made of silicide or metal having a higher work function than the n-polysilicon. The novel device structure shows several advantages: the channel doping is reduced while maintaining a high Vt and a low sub-threshold leakage current; the carrier mobility improves with the reduced channel doping; the body effect of the device is reduced which improves the write back current; and the sub-threshold swing is reduced because of the low channel doping.
摘要翻译：在DRAM单元中使用的用于保持低总漏电流并提供足够的驱动电流的垂直传输晶体管与制造这种器件的方法一起被描述。晶体管栅极被设计代替通道。用于DRAM单元的垂直传输晶体管包括具有不同功函数的两个栅极材料。存储节点附近的栅极材料为n型掺杂多晶硅。位线扩散附近的栅极材料由具有比n-多晶硅更高的功函数的硅化物或金属制成。该新颖的器件结构显示出几个优点：沟道掺杂减少，同时保持高Vt和低的亚阈值漏电流; 载流子迁移率随着沟道掺杂的降低而提高; 减少了器件的体效，提高了回写电流; 并且由于低通道掺杂，子阈值摆幅减小。

5. 发明授权

US06930004B2 Self-aligned drain/channel junction in vertical pass transistor DRAM cell design for device scaling 有权
标题翻译：垂直传输晶体管中的自对准漏极/沟道结DRAM器件设计用于器件缩放
公开(公告)号：US06930004B2
公开(公告)日：2005-08-16
申请号：US10604731
申请日：2003-08-13
申请人： Geng Wang , Kevin Mcstay , Mary Elizabeth Weybright , Yujun Li , Dureseti Chidambarrao
发明人： Geng Wang , Kevin Mcstay , Mary Elizabeth Weybright , Yujun Li , Dureseti Chidambarrao
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8242
CPC分类号： H01L27/10876 , H01L21/26586 , H01L27/10864 , H01L29/1041 , H01L29/66537 , H01L29/66666 , H01L29/7827 , H01L29/945
摘要： A method of formation of a deep trench vertical transistor is provided. A deep trench with a sidewall in a doped semiconductor substrate is formed. The semiconductor substrate includes a counterdoped drain region in the surface thereof and a channel alongside the sidewall. The drain region has a top level and a bottom level. A counterdoped source region is formed in the substrate juxtaposed with the sidewall below the channel. A gate oxide layer is formed on the sidewalls of the trench juxtaposed with a gate conductor. Perform the step of recessing the gate conductor below the bottom level of the drain region followed by performing angled ion implantation at an angle θ+δ with respect to vertical of a counterdopant into the channel below the source region and performing angled ion implantation at an angle θ with respect to vertical of a dopant into the channel below the source.
摘要翻译：提供了形成深沟槽垂直晶体管的方法。在掺杂半导体衬底中形成具有侧壁的深沟槽。半导体衬底在其表面中包括反向漏极区域和沿着侧壁的通道。漏极区域具有顶层和底层。反向掺杂的源极区域形成在与通道下方的侧壁并置的衬底中。栅极氧化层形成在与栅极导体并置的沟槽的侧壁上。执行将栅极导体凹入低于漏极区域的底部电平的步骤，然后相对于反向掺杂物的垂直角进行成角度的离子注入进入源极区域下方的沟道，并以一定角度进行成角度的离子注入 θ相对于掺杂剂的垂直方向到源下方的通道。

6. 发明申请

US20050037561A1 SELF-ALIGNED DRAIN/CHANNEL JUNCTION IN VERTICAL PASS TRANSISTOR DRAM CELL DESIGN FOR DEVICE SCALING 有权
标题翻译：用于设备放大的垂直通用晶体管DRAM单元设计中的自对准漏极/通道结
公开(公告)号：US20050037561A1
公开(公告)日：2005-02-17
申请号：US10604731
申请日：2003-08-13
申请人： Geng Wang , Kevin McStay , Mary Weybright , Yujun Li , Dureseti Chidambarrao
发明人： Geng Wang , Kevin McStay , Mary Weybright , Yujun Li , Dureseti Chidambarrao
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8242
CPC分类号： H01L27/10876 , H01L21/26586 , H01L27/10864 , H01L29/1041 , H01L29/66537 , H01L29/66666 , H01L29/7827 , H01L29/945
摘要： A method of formation of a deep trench vertical transistor is provided. A deep trench with a sidewall in a doped semiconductor substrate is formed. The semiconductor substrate includes a counterdoped drain region in the surface thereof and a channel alongside the sidewall. The drain region has a top level and a bottom level. A counterdoped source region is formed in the substrate juxtaposed with the sidewall below the channel. A gate oxide layer is formed on the sidewalls of the trench juxtaposed with a gate conductor. Perform the step of recessing the gate conductor below the bottom level of the drain region followed by performing angled ion implantation at an angle θ+δ with respect to vertical of a counterdopant into the channel below the source region and performing angled ion implantation at an angle θ with respect to vertical of a dopant into the channel below the source region
摘要翻译：提供了形成深沟槽垂直晶体管的方法。在掺杂半导体衬底中形成具有侧壁的深沟槽。半导体衬底在其表面中包括反向漏极区域和沿着侧壁的通道。漏极区域具有顶层和底层。反向掺杂的源极区域形成在与通道下方的侧壁并置的衬底中。栅极氧化层形成在与栅极导体并置的沟槽的侧壁上。执行将栅极导体凹入低于漏极区域的底部电平的步骤，然后相对于反向掺杂物的垂直角进行成角度的离子注入进入源极区域下方的沟道，并以一定角度进行成角度的离子注入相对于掺杂剂的垂直方向在源极区域下方的沟道中

7. 发明授权

US09235879B2 Apparatus, system, and method for temporal domain hole filling based on background modeling for view synthesis 有权
标题翻译：基于视图合成的背景建模的时域填充的装置，系统和方法
公开(公告)号：US09235879B2
公开(公告)日：2016-01-12
申请号：US13538966
申请日：2012-06-29
申请人： Sun Wenxiu , Oscar C. Au , Lingfeng Xu , Yujun Li , Wei Hu , Lu Wang
发明人： Sun Wenxiu , Oscar C. Au , Lingfeng Xu , Yujun Li , Wei Hu , Lu Wang
IPC分类号： G06T5/00 , H04N13/02
CPC分类号： G06T5/005 , G06T2207/10021 , G06T2207/20182 , H04N13/261
摘要： Embodiments of apparatuses, systems, and methods for a temporal hole filling are described. Specifically, an embodiment of the present invention may include a depth-based hole filling process that includes a background modeling technique (SGM). Beneficially, in such an embodiment, holes in the synthesized view may be filled effectively and efficiently.
摘要翻译：描述了用于时空填充的装置，系统和方法的实施例。具体地，本发明的实施例可以包括基于深度的孔填充过程，其包括背景建模技术（SGM）。有利地，在这样的实施例中，可以有效且有效地填充合成视图中的孔。

8. 发明授权

US07696539B2 Device fabrication by anisotropic wet etch 失效
标题翻译：通过各向异性湿法蚀刻的器件制造
公开(公告)号：US07696539B2
公开(公告)日：2010-04-13
申请号：US12141878
申请日：2008-06-18
申请人： Yujun Li , Kenneth T. Settlemyer, Jr. , Jochen Beintner
发明人： Yujun Li , Kenneth T. Settlemyer, Jr. , Jochen Beintner
IPC分类号： H01L29/80
CPC分类号： H01L21/84 , H01L21/30608 , H01L27/1203 , H01L29/045 , H01L29/66772 , H01L29/66818 , H01L29/785
摘要： A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substantially parallel with selected crystallographic planes of the pedestal and of a supporting member. The pedestal is wet etched with an anisotropic solution containing ammonium hydroxide. The sidewalls of the pedestal become faceted forming a segment in the pedestal with a reduced cross section. The dopant concentration in the reduced cross section segment is chosen to be sufficiently high for it to provide for electrical continuity through the pedestal.
摘要翻译：提出了一种制造方法和场效应器件结构，其减少源/漏电容并允许器件接触。产生基于Si的材料基座，其顶表面和其侧壁的方向定位成与基座和支撑构件的选定结晶平面基本平行。用包含氢氧化铵的各向异性溶液湿式蚀刻基座。基座的侧壁变小，在基座上形成截面减小的部分。选择减小的横截面段中的掺杂剂浓度足够高以使其提供穿过基座的电连续性。

9. 发明授权

US07470570B2 Process for fabrication of FinFETs 有权
标题翻译： FinFET的制造工艺
公开(公告)号：US07470570B2
公开(公告)日：2008-12-30
申请号：US11559460
申请日：2006-11-14
申请人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
发明人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
IPC分类号： H01L21/00
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.
摘要翻译：提供了在半导体衬底上制造多个FinFET的方法，其中仅使用单个蚀刻工艺限定每个单个FinFET的栅极宽度，而不是两个或更多个。本发明的方法导致改善的栅极宽度控制和在基板的整个表面上每个单独栅极的栅极宽度的变化较小。本发明的方法通过利用改进的侧壁图像转印（SIT）工艺实现上述，其中采用稍后被栅极导体替代的绝缘间隔物，并且使用高密度底部向上氧化物填充物将栅极与衬底隔离。

10. 发明申请

US20080111184A1 PROCESS FOR FABRICATION OF FINFETs 有权
标题翻译： FINFET制造工艺
公开(公告)号：US20080111184A1
公开(公告)日：2008-05-15
申请号：US11559460
申请日：2006-11-14
申请人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
发明人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.
摘要翻译：提供了在半导体衬底上制造多个FinFET的方法，其中仅使用单个蚀刻工艺限定每个单个FinFET的栅极宽度，而不是两个或更多个。本发明的方法导致改善的栅极宽度控制和在基板的整个表面上每个单独栅极的栅极宽度的变化较小。本发明的方法通过利用改进的侧壁图像转印（SIT）工艺实现上述，其中采用稍后被栅极导体替代的绝缘间隔物，并且使用高密度底部向上氧化物填充物将栅极与衬底隔离。

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