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1. 发明授权

US06240033B1 Antifuse circuitry for post-package DRAM repair 有权
标题翻译：用于后封装DRAM修复的防漏电路
公开(公告)号：US06240033B1
公开(公告)日：2001-05-29
申请号：US09479665
申请日：2000-01-10
申请人： Woodward Yang , Joo Sun Choi , Jae Kyung Wee , Young Ho Seol , Jin Keun Oh , Phil Jung Kim , Ho Youe Cho
发明人： Woodward Yang , Joo Sun Choi , Jae Kyung Wee , Young Ho Seol , Jin Keun Oh , Phil Jung Kim , Ho Youe Cho
IPC分类号： G11C700
CPC分类号： G11C29/781 , G11C17/18
摘要： The anti-fuse circuit includes three sub-blocks: a multiplexer having inputs of control signals and addresses and yielding the activation of a programming signal and program addresses; a programming voltage generator consisting of an oscillator and a charge pump; and an anti-fuse unit circuits for the program/read of anti-fuse states. For an anti-fuse program at the special test mode, a program address generation circuit having inputs of control signals and addresses activates the programming voltage generator and makes a special or program address for selection of anti-fuse. In the normal mode, the program address generation circuit and an internal power generator remain at an inactive state. In anti-fuse unit circuit, the program address and the programming voltage signal from the programming voltage generator serve to switch the terminal of the anti-fuse up to a programming voltage level when the anti-fuse is selected for programming of anti-fuse elements.
摘要翻译：反熔丝电路包括三个子块：具有控制信号和地址的输入并产生编程信号和程序地址的激活的多路复用器; 由振荡器和电荷泵组成的编程电压发生器; 以及用于编程/读取反熔丝状态的反熔丝单元电路。对于在特殊测试模式下的反熔丝程序，具有控制信号和地址的输入的程序地址产生电路激活编程电压发生器，并产生用于选择反熔丝的特殊或程序地址。在正常模式中，程序地址产生电路和内部发电机保持在非工作状态。在反熔丝单元电路中，编程电压发生器的程序地址和编程电压信号用于在反熔丝被选择用于编程抗熔丝元件时将反熔丝的端子切换到编程电压电平。

2. 发明授权

US06366118B2 Antifuse repair circuit 失效
标题翻译：防腐修复电路
公开(公告)号：US06366118B2
公开(公告)日：2002-04-02
申请号：US09790019
申请日：2001-02-21
申请人： Jin Keun Oh , Jae Kyung Wee , Chang Hyuk Lee , Phil Jung Kim
发明人： Jin Keun Oh , Jae Kyung Wee , Chang Hyuk Lee , Phil Jung Kim
IPC分类号： G06F738
CPC分类号： G11C17/18 , G11C29/785
摘要： An antifuse repair circuit is disclosed for selectively programming a specific antifuse to replace a defective cell with a redundant cell. The antifuse repair circuit includes: (a) a special test mode decoder for selecting an antifuse box according to an address signal; (b) a bank selector for selecting an antifuse bank according to the output signal from the special test mode decoder and the address signal; (c) a special address multiplexer for selecting a specific antifuse within an antifuse bank selected by the bank selector according to the output signal from the bank selector and the address signal; (d) a negative voltage generator for generating a negative voltage to program an antifuse device; (e) a power-up detector for detecting the supply voltage to generate a plurality of control signals in order to detect whether the antifuse device is programmed; (f) a unit antifuse circuit for programming the antifuse device according to the signals from the special test mode detector, the special address multiplexer, the negative voltage generator and the power-up detector; and (g) a repair circuit responsive to the output signal from the unit antifuse circuit and an external control signal to replace a defective cell with a redundant cell.
摘要翻译：公开了一种反熔丝修复电路，用于选择性地编程特定反熔丝以用冗余单元替换有缺陷的单元。反熔丝修复电路包括：（a）专用测试模式解码器，用于根据地址信号选择反熔丝; （b）根据来自特殊测试模式解码器的输出信号和地址信号选择反熔丝组的存储体选择器; （c）专用地址多路复用器，用于根据来自存储体选择器的输出信号和地址信号，选择由存储体选择器选择的反熔丝库内的特定反熔丝; （d）用于产生负电压以编程反熔丝装置的负电压发生器; （e）上电检测器，用于检测电源电压以产生多个控制信号，以便检测反熔丝装置是否被编程; （f）用于根据来自特殊测试模式检测器，专用地址多路复用器，负电压发生器和上电检测器的信号对反熔丝装置进行编程的单元反熔丝电路; 和（g）响应于来自单元反熔丝电路的输出信号的修复电路和外部控制信号以用冗余单元替换有缺陷的单元。

3. 发明授权

US06229747B1 Self-refresh apparatus for a semiconductor memory device 有权
标题翻译：用于半导体存储器件的自刷新装置
公开(公告)号：US06229747B1
公开(公告)日：2001-05-08
申请号：US09468784
申请日：1999-12-21
申请人： Ho Youb Cho , Jin Keun Oh
发明人： Ho Youb Cho , Jin Keun Oh
IPC分类号： G11C700
CPC分类号： G11C11/40615 , G11C11/406 , G11C2211/4068
摘要： A self-refresh apparatus for a semiconductor memory device is disclosed. According to the self-refresh apparatus, Data loss can be prevented by monitoring a leakage of memory cell data, activating a variable self-refresh signal in accordance with a signal resulted from the monitoring during a self-refresh mode, producing a refresh request signal when the self-refresh signal is activated and then refreshing all of memory cells. An unnecessary power consumption can be also prevented by variably performing the refresh operation in accordance with the retention time of cell data.
摘要翻译：公开了一种用于半导体存储器件的自刷新装置。根据自刷新装置，可以通过监视存储单元数据的泄漏，根据在自刷新模式期间的监视产生的信号来激活可变自刷新信号来防止数据丢失，产生刷新请求信号当自刷新信号被激活然后刷新所有存储单元时。还可以通过根据单元数据的保持时间可变地执行刷新操作来防止不必要的功耗。

4. 发明授权

US06184720B2 Internal voltage generating circuit of a semiconductor device using test pad and a method thereof 有权
标题翻译：使用测试焊盘的半导体器件的内部电压产生电路及其方法
公开(公告)号：US06184720B2
公开(公告)日：2001-02-06
申请号：US09334920
申请日：1999-06-17
申请人： Young Hee Kim , Jin Keun Oh
发明人： Young Hee Kim , Jin Keun Oh
IPC分类号： H03K908
CPC分类号： G01R31/31715 , G01R31/31712 , G01R31/318575 , G05F1/465
摘要： An internal voltage generating circuit and method for generating thereof in semiconductor device capable of performing test without any needless transfer between a test equipment and a repair equipment are disclosed. The circuit includes a plurality of test power voltage pads, each of which can be selectively applied with the external power voltage and a ground voltage during test; a fuse programmable control signal generator coupled to the plurality of test power voltage pads for generating a control signal according to the signals applied to the plurality of the test power voltage pads during test, and for generating the control signal according to fuse-programmed state after at least one fuse included therein is programmed; a reference voltage generator for receiving the external power voltage so as to produce a reference voltage having a predetermined level; and a voltage trimming unit for trimming the reference voltage in accordance with the output of the fuse programmable control signal generator.
摘要翻译：公开了一种内部电压产生电路及其在半导体器件中的生成方法，能够在测试设备和维修设备之间进行无需传输的测试。该电路包括多个测试电源电压焊盘，每个测试电源焊盘可以在测试期间选择性地施加外部电源电压和接地电压; 熔丝可编程控制信号发生器，其耦合到所述多个测试电源电压焊盘，用于根据在测试期间施加到所述多个测试电源电压焊盘的信号产生控制信号，并且用于根据熔丝编程状态生成所述控制信号其中包括的至少一个保险丝被编程; 参考电压发生器，用于接收外部电源电压以产生具有预定电平的参考电压; 以及电压修整单元，用于根据熔丝可编程控制信号发生器的输出修整参考电压。

5. 发明授权

US09255313B2 Steel sheet for hot press forming having low-temperature heat treatment property, method of manufacturing the same, method of manufacturing parts using the same, and parts manufactured by the same 有权
标题翻译：具有低温热处理性能的热压成型用钢板，其制造方法，使用其的制造零件的方法及其制造方法
公开(公告)号：US09255313B2
公开(公告)日：2016-02-09
申请号：US12183519
申请日：2008-07-31
申请人： Yeol Rae Cho , Jin Keun Oh , Sung Ho Park
发明人： Yeol Rae Cho , Jin Keun Oh , Sung Ho Park
IPC分类号： C22C38/06 , C21D1/48 , C21D1/673 , C21D6/00 , C21D8/02 , C21D9/46 , C22C38/00 , C22C38/04 , C22C38/12 , C22C38/14
CPC分类号： C22C38/06 , C21D1/48 , C21D1/673 , C21D6/005 , C21D8/0226 , C21D8/0263 , C21D9/46 , C21D2211/002 , C21D2211/005 , C21D2211/008 , C21D2211/009 , C22C38/002 , C22C38/04 , C22C38/12 , C22C38/14 , Y10T29/49991
摘要： A steel sheet for forming having low-temperature heat treatment property, in which heat treatment is performed within a range of lower temperature than a conventional steel sheet in the event of hot press forming or post-heat treatment after cold forming, a method of manufacturing the same, and a method of manufacturing parts using the same. The steel sheet has a composition of, by weight, carbon (C): 0.15 to 0.35%, silicon (Si): 0.5% or less, manganese (Mn): 1.5 to 2.2%, phosphorus (P): 0.025% or less, sulfur (S): 0.01% or less, aluminum (Al): 0.01 to 0.05%, nitrogen (N): 50 to 200 ppm, titanium (Ti): 0.005 to 0.05%, tungsten (W): 0.005 to 0.1%, and boron (B): 1 to 50 ppm, wherein Ti/N: less than 3.4, where Ti/N is the atomic ratio of the corresponding elements, Ceq expressed by the following formula ranges from 0.48 to 0.58, and temperature Ar3 ranges from 670° C. to 725° C. Wherein Ceq C+Si/24+Mn/6+Ni/40+Cr/5+V/14 where C, Si, Mn, Ni, Cr and V indicate the contents (wt %) of the respective elements.
摘要翻译：一种在热成型或冷成型后的后热处理的情况下，在比常规钢板低温的范围内进行热处理的低温热处理性的钢板，制造方法以及使用该部件的部件的制造方法。该钢板的碳（C）重量比为0.15〜0.35％，硅（Si）：0.5％以下，锰（Mn）：1.5〜2.2％，磷（P）：0.025％以下），硫（S）：0.01％以下，铝（Al）：0.01〜0.05％，氮（N）：50〜200ppm，钛（Ti）：0.005〜0.05％，钨（W）：0.005〜，硼（B）：1〜50ppm，其中Ti / N：小于3.4，其中Ti / N是相应元素的原子比，由下式表示的Ceq为0.48〜0.58，温度Ar3为其中C，Si，Mn，Ni，Cr和V表示内容物（wt（重量）），其中C 1，C 2，C 2，％）。

6. 发明申请

US20110017363A1 HIGH STRENGTH THIN STEEL SHEET EXCELLING IN WELDABILITY AND PROCESS FOR PRODUCING THE SAME 审中-公开
标题翻译：高强度钢板在焊接性能及其制造方法中的应用
公开(公告)号：US20110017363A1
公开(公告)日：2011-01-27
申请号：US12810852
申请日：2008-08-08
申请人： Hee Jae Kang , Jin Keun Oh , Kwang Geun Chin , Jong Sang Kim
发明人： Hee Jae Kang , Jin Keun Oh , Kwang Geun Chin , Jong Sang Kim
IPC分类号： C21D8/02 , C22C38/12 , C22C38/14
CPC分类号： C22C38/38 , C22C38/06 , C22C38/32 , C22C38/60
摘要： Provided are a high strength thin steel sheet having tensile strength of about 800 MPa or more, and a manufacturing method thereof. The thin steel sheet is mainly used for construction materials, home appliances, and automobiles. The thin steel sheet has excellent plating characteristic, welding characteristic, bending workability, and hole expansion ratio. The thin steel sheet includes, in weight %, C: 0.02-0.20%, Si: 1.5% or less, Mn: 1.5-3.0%, P: 0.001-0.10%, S: 0.010% or less, SoLAl: 0.01-0.40%, N: 0.020% or less, Cr: 0.3-1.5%, B: 0.0010-0.0060%, Sb: 0.001-0.10%, and including at least one material selected from the group consisting of Ti: 0.003-0.08%, Nb: 0.003-0.08%, and Mo: 0.003-0.08%, and includes Fe and other inevitable impurities as a remainder. Here, Si, Mn, B, Sb, P, and S meet conditions of 5
摘要翻译：本发明提供一种拉伸强度为约800MPa以上的高强度薄钢板及其制造方法。薄钢板主要用于建筑材料，家用电器和汽车。薄钢板具有优异的电镀特性，焊接特性，弯曲加工性和孔膨胀率。该薄钢板以重量％计含有C：0.02-0.20％，Si：1.5％以下，Mn：1.5-3.0％，P：0.001-0.10％，S：0.010％以下，SoLAl：0.01-0.40 ％，N：0.020％以下，Cr：0.3〜1.5％，B：0.0010〜0.0060％，Sb：0.001-0.10％，并且包括选自Ti：0.003-0.08％，Nb ：0.003-0.08％，Mo：0.003-0.08％，其余为Fe等不可避免的杂质。这里，Si，Mn，B，Sb，P和S满足5 <（Si / Mn + 150B）/ Sb <20和C + Mn / 20 + Si / 30 + 2P + 4S <0.27的条件。此外，制造方法可以确保薄钢板的可加工性。

7. 发明申请

US20090238715A1 STEEL SHEET FOR HOT PRESS FORMING HAVING LOW-TEMPERATURE HEAT TREATMENT PROPERTY, METHOD OF MANUFACTURING THE SAME, METHOD OF MANUFACTURING PARTS USING THE SAME, AND PARTS MANUFACTURED BY THE SAME 有权
标题翻译：用于具有低温热处理性能的热压成型的钢板，其制造方法，使用该方法制造部件的方法以及由其制造的部件
公开(公告)号：US20090238715A1
公开(公告)日：2009-09-24
申请号：US12183519
申请日：2008-07-31
申请人： Yeol-Rae Cho , Jin Keun Oh , Sung-Ho Park
发明人： Yeol-Rae Cho , Jin Keun Oh , Sung-Ho Park
IPC分类号： C22C38/16 , C22C38/04 , C21D8/02 , B21B13/22 , C22C38/00 , C22C38/08
CPC分类号： C22C38/06 , C21D1/48 , C21D1/673 , C21D6/005 , C21D8/0226 , C21D8/0263 , C21D9/46 , C21D2211/002 , C21D2211/005 , C21D2211/008 , C21D2211/009 , C22C38/002 , C22C38/04 , C22C38/12 , C22C38/14 , Y10T29/49991
摘要： A steel sheet for forming having low-temperature heat treatment property, in which heat treatment is performed within a range of lower temperature than a conventional steel sheet in the event of hot press forming or post-heat treatment after cold forming, a method of manufacturing the same, and a method of manufacturing parts using the same. The steel sheet has a composition of, by weight, carbon (C): 0.15 to 0.35%, silicon (Si): 0.5% or less, manganese (Mn): 1.5 to 2.2%, phosphorus (P): 0.025% or less, sulfur (S): 0.01% or less, aluminum (Al): 0.01 to 0.05%, nitrogen (N): 50 to 200 ppm, titanium (Ti): 0.005 to 0.05%, tungsten (W): 0.005 to 0.1%, and boron (B): 1 to 50 ppm, wherein Ti/N: less than 3.4, where Ti/N is the atomic ratio of the corresponding elements, Ceq expressed by the following formula ranges from 0.48 to 0.58, and temperature Ar3 ranges from 670° C. to 725° C. Wherein Ceq=C+Si/24+Mn/6+Ni/40+Cr/5+V/14 where C, Si, Mn, Ni, Cr and V indicate the contents (wt %) of the respective elements.
摘要翻译：一种在热成型或冷成型后的后热处理的情况下，在比常规钢板低温的范围内进行热处理的低温热处理性的钢板，制造方法以及使用该部件的部件的制造方法。该钢板的碳（C）重量比为0.15〜0.35％，硅（Si）：0.5％以下，锰（Mn）：1.5〜2.2％，磷（P）：0.025％以下），硫（S）：0.01％以下，铝（Al）：0.01〜0.05％，氮（N）：50〜200ppm，钛（Ti）：0.005〜0.05％，钨（W）：0.005〜，硼（B）：1〜50ppm，其中Ti / N：小于3.4，其中Ti / N是相应元素的原子比，由下式表示的Ceq为0.48〜0.58，温度Ar3为其中Ce，C + Si / 24 + Mn / 6 + Ni / 40 + Cr / 5 + V / 14其中C，Si，Mn，Ni，Cr和V表示含量 wt％）。

8. 发明授权

US06389563B1 Semiconductor memory test circuit and method for the same 失效
标题翻译：半导体存储器测试电路及其方法相同
公开(公告)号：US06389563B1
公开(公告)日：2002-05-14
申请号：US09340731
申请日：1999-06-29
申请人： Jin Keun Oh , Young Hee Kim
发明人： Jin Keun Oh , Young Hee Kim
IPC分类号： G11C2900
CPC分类号： G11C29/34 , G11C29/40 , G11C29/46
摘要： A semiconductor memory test circuit and a method for the same to reduce the test time in testing a semiconductor memory. The semiconductor memory test circuit includes: a parallel test circuit for performing a parallel test when inputting a battery backup signal (bbu), a column address signal (cas5), a CAS before RAS signal (cbr), a write enable signal (ew), a power-up bar signal (pwrupb), and a row address signal (ras71)); and a test mode circuit which is controlled by a combination of a parallel test signal (pt) and the battery backup signal (bbu) generated from the parallel test circuit, and generates a test time reduction signal (ttrb), whereby the semiconductor memory test circuit compresses one least significant bit indicating a row address of a device in the case of a 4K refresh operation when the test time reduction signal (ttrb) is enabled, and compresses two least significant bits indicating a row address of a device in the case of an 8K refresh operation when the test time reduction signal (ttrb) is enabled.
摘要翻译：一种半导体存储器测试电路及其方法，用于减少测试半导体存储器的测试时间。半导体存储器测试电路包括：并行测试电路，用于在输入电池备用信号（bbu），列地址信号（cas5），RAS信号（cbr）之前的CAS，写使能信号（ew），上电条信号（pwrupb）和行地址信号（ras71））; 以及由并行测试电路产生的并行测试信号（pt）和电池备用信号（bbu）的组合控制的测试模式电路，并且产生测试时间减少信号（ttrb），由此半导体存储器测试当测试时间减少信号（ttrb）被使能时，在4K刷新操作的情况下，电路压缩指示设备的行地址的一个最低有效位，并且在两个最低有效位的情况下压缩指示设备的行地址的两个最低有效位当测试时间减少信号（ttrb）被使能时，8K刷新操作。

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