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1. 发明申请

US20060033591A1 Voltage-controlled oscillators with controlled operating range and related bias circuits and methods 失效
标题翻译：具有受控工作范围和相关偏置电路和方法的压控振荡器
公开(公告)号：US20060033591A1
公开(公告)日：2006-02-16
申请号：US11198691
申请日：2005-08-05
申请人： Woo-Seok Kim , Ju-Hyung Kim
发明人： Woo-Seok Kim , Ju-Hyung Kim
IPC分类号： H03L7/099
CPC分类号： H03L7/0995 , H03K3/0322 , H03K5/2472 , H03L1/022 , H03L7/099
摘要： A voltage-controlled oscillator includes a bias circuit and a delay circuit. The bias circuit may generate a bias voltage signal pair having levels that are based on the voltage level of an input voltage signal and that are constrained by the values of a maximum current signal and a minimum current signal that are generated in the bias circuit. The delay circuit generates an output signal having a frequency that varies in response to the bias voltage signal pair. Because an operating frequency range of a voltage-controlled oscillator VCO is limited by a bias circuit, the VCO can operate with reduced gain and can limit the maximum operating frequency to a predetermined level. The VCO may also include a PTAT current generator in the bias circuit which can allow the VCO to compensate for variations of the VCO output frequency based on temperature.
摘要翻译：压控振荡器包括偏置电路和延迟电路。偏置电路可以产生具有基于输入电压信号的电压电平并且受偏置电路中产生的最大电流信号和最小电流信号的值约束的电平的偏置电压信号对。延迟电路产生具有响应于偏置电压信号对而变化的频率的输出信号。由于压控振荡器VCO的工作频率范围由偏置电路限制，所以VCO可以以减小的增益进行工作，并且可以将最大工作频率限制在预定的水平。 VCO还可以包括偏置电路中的PTAT电流发生器，其可以允许VCO基于温度补偿VCO输出频率的变化。

2. 发明授权

US07233214B2 Voltage-controlled oscillators with controlled operating range and related bias circuits and methods 失效
标题翻译：具有受控工作范围和相关偏置电路和方法的压控振荡器
公开(公告)号：US07233214B2
公开(公告)日：2007-06-19
申请号：US11198691
申请日：2005-08-05
申请人： Woo-Seok Kim , Ju-Hyung Kim
发明人： Woo-Seok Kim , Ju-Hyung Kim
IPC分类号： H03L1/02 , H03L7/099
CPC分类号： H03L7/0995 , H03K3/0322 , H03K5/2472 , H03L1/022 , H03L7/099
摘要： A voltage-controlled oscillator includes a bias circuit and a delay circuit. The bias circuit may generate a bias voltage signal pair having levels that are based on the voltage level of an input voltage signal and that are constrained by the values of a maximum current signal and a minimum current signal that are generated in the bias circuit. The delay circuit generates an output signal having a frequency that varies in response to the bias voltage signal pair. Because an operating frequency range of a voltage-controlled oscillator VCO is limited by a bias circuit, the VCO can operate with reduced gain and can limit the maximum operating frequency to a predetermined level. The VCO may also include a PTAT current generator in the bias circuit which can allow the VCO to compensate for variations of the VCO output frequency based on temperature.
摘要翻译：压控振荡器包括偏置电路和延迟电路。偏置电路可以产生具有基于输入电压信号的电压电平并且受偏置电路中产生的最大电流信号和最小电流信号的值约束的电平的偏置电压信号对。延迟电路产生具有响应于偏置电压信号对而变化的频率的输出信号。由于压控振荡器VCO的工作频率范围由偏置电路限制，所以VCO可以以减小的增益进行工作，并且可以将最大工作频率限制在预定的水平。 VCO还可以包括偏置电路中的PTAT电流发生器，其可以允许VCO基于温度补偿VCO输出频率的变化。

3. 发明授权

US08188532B2 Semiconductor device having a gate contact structure capable of reducing interfacial resistance 有权
标题翻译：具有能够降低界面电阻的栅极接触结构的半导体器件
公开(公告)号：US08188532B2
公开(公告)日：2012-05-29
申请号：US12856295
申请日：2010-08-13
申请人： Chang-Seok Kang , Yoo-Cheol Shin , Jung-Dal Choi , Jong-Sun Sel , Ju-Hyung Kim , Sang-Hun Jeon
发明人： Chang-Seok Kang , Yoo-Cheol Shin , Jung-Dal Choi , Jong-Sun Sel , Ju-Hyung Kim , Sang-Hun Jeon
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/823462 , H01L21/823475 , H01L27/115 , H01L27/11524 , H01L29/7883
摘要： A semiconductor device has a gate contact structure, including a semiconductor substrate, a polycrystalline silicon layer used as a gate electrode of a transistor, a middle conductive layer, a top metal layer having an opening exposing the polycrystalline silicon layer, and a contact plug directly contacting the polycrystalline silicon layer through the opening.
摘要翻译：半导体器件具有栅极接触结构，包括半导体衬底，用作晶体管的栅电极的多晶硅层，中间导电层，具有暴露多晶硅层的开口的顶部金属层和直接接触的插塞使多晶硅层通过开口接触。

4. 发明申请

US20110037118A1 Nonvolatile memory device having cell and peripheral regions and method of making the same 有权
公开(公告)号：US20110037118A1
公开(公告)日：2011-02-17
申请号：US12923998
申请日：2010-10-20
申请人： Ju-Hyung Kim , Jung-Dal Choi , Jang-Hyun You
发明人： Ju-Hyung Kim , Jung-Dal Choi , Jang-Hyun You
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , H01L27/105 , H01L27/11568 , H01L27/11573
摘要： A nonvolatile memory device and method of making the same are provided. Memory cells may be provided in a cell area wherein each memory cell has an insulative structure including a tunnel insulating layer, a floating trap layer and a blocking layer, and a conductive structure including an energy barrier layer, a barrier metal layer and a low resistance gate electrode. A material having a lower resistivity may be used as the gate electrode so as to avoid problems associated with increased resistance and to allow the gate electrode to be made relatively thin. The memory device may further include transistors in the peripheral area, which may have a gate dielectric layer, a lower gate electrode of poly-silicon and an upper gate electrode made of metal silicide, allowing an improved interface with the lower gate electrode without diffusion or reaction while providing a lower resistance.

5. 发明申请

US20100133604A1 Semiconductor Devices Having Gate Structures with Conductive Patterns of Different Widths and Methods of Fabricating Such Devices 有权
标题翻译：具有具有不同宽度的导电图案的门结构的半导体器件和制造这种器件的方法
公开(公告)号：US20100133604A1
公开(公告)日：2010-06-03
申请号：US12622594
申请日：2009-11-20
申请人： Ju-Hyung Kim , Chang-Seok Kang , Sung-Il Chang , Young-Woo Park , Jung-Dal Choi
发明人： Ju-Hyung Kim , Chang-Seok Kang , Sung-Il Chang , Young-Woo Park , Jung-Dal Choi
IPC分类号： H01L29/792
CPC分类号： H01L29/42324 , H01L21/28273 , H01L21/28282 , H01L29/4234
摘要： A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first dielectric pattern, a data storage pattern and a second dielectric pattern, which are sequentially stacked on a semiconductor substrate. A first conductive pattern is provided on the second dielectric pattern. A second conductive pattern having a greater width than the first conductive pattern is provided on the first conductive pattern.
摘要翻译：提供半导体器件及其制造方法。半导体器件包括依次层叠在半导体衬底上的第一电介质图案，数据存储图案和第二电介质图案。在第二电介质图案上提供第一导电图案。具有比第一导电图案更大的宽度的第二导电图案设置在第一导电图案上。

6. 发明申请

US20060255399A1 Nonvolatile memory device having a plurality of trapping films 审中-公开
标题翻译：具有多个捕获膜的非易失性存储器件
公开(公告)号：US20060255399A1
公开(公告)日：2006-11-16
申请号：US11354076
申请日：2006-02-15
申请人： Ju-Hyung Kim , Jeong-Hee Han , Chung-Woo Kim , Yo-Sep Min , Moon-Kyung Kim , Youn-Seok Jeong
发明人： Ju-Hyung Kim , Jeong-Hee Han , Chung-Woo Kim , Yo-Sep Min , Moon-Kyung Kim , Youn-Seok Jeong
IPC分类号： H01L29/792
CPC分类号： H01L29/7881 , H01L29/4232 , H01L29/42324 , H01L29/513 , H01L29/792
摘要： Provided is a nonvolatile memory device which includes a tunneling insulating film formed on a semiconductor substrate, a storage node formed on the tunneling insulating film, a blocking insulating film formed on the storage node, and a control gate electrode formed on the blocking insulating film. The storage node includes at least two trapping films having different trap densities, and the blocking insulating film has a dielectric constant greater than that of the silicon oxide film.
摘要翻译：提供了一种非易失性存储器件，其包括形成在半导体衬底上的隧道绝缘膜，形成在隧道绝缘膜上的存储节点，形成在存储节点上的阻挡绝缘膜，以及形成在阻挡绝缘膜上的控制栅电极。存储节点包括具有不同陷阱密度的至少两个俘获膜，并且阻挡绝缘膜的介电常数大于氧化硅膜的介电常数。

7. 发明申请

US20060186462A1 Nonvolatile memory device and method of fabricating the same 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20060186462A1
公开(公告)日：2006-08-24
申请号：US11357329
申请日：2006-02-21
申请人： Jeong-Hee Han , Ju-Hyung Kim , Chung-Woo Kim , Sang-Hun Jeon , Youn-Seok Jeong , Seung-Hyun Lee
发明人： Jeong-Hee Han , Ju-Hyung Kim , Chung-Woo Kim , Sang-Hun Jeon , Youn-Seok Jeong , Seung-Hyun Lee
IPC分类号： H01L29/788
CPC分类号： H01L29/42324 , H01L29/513 , H01L29/792
摘要： Provided are example embodiments of fabrication methods and resulting structures suitable for use in nonvolatile memory devices formed on semiconductor substrates. The example embodiments of the gate structures include a first insulating film formed on the semiconductor substrate, a storage node formed on the first insulating film for storing charges, a second insulating film formed on the storage node, a third insulating film formed on the second insulating film, and a gate electrode formed on the third insulating film. The insulating films are selected whereby the dielectric constant of one or both of the second and third insulating films is greater than the dielectric constant of the first insulating film.
摘要翻译：提供了适用于形成在半导体衬底上的非易失性存储器件中的制造方法和结果结构的示例性实施例。栅极结构的示例实施例包括形成在半导体衬底上的第一绝缘膜，形成在用于存储电荷的第一绝缘膜上的存储节点，形成在存储节点上的第二绝缘膜，形成在第二绝缘层上的第三绝缘膜膜和形成在第三绝缘膜上的栅电极。选择绝缘膜，由此第二和第三绝缘膜中的一个或两个的介电常数大于第一绝缘膜的介电常数。

8. 发明申请

US20060017476A1 Phase locked loop integrated circuits having fast locking characteristics and methods of operating same 有权
标题翻译：具有快速锁定特性的锁相环集成电路及其操作方法
公开(公告)号：US20060017476A1
公开(公告)日：2006-01-26
申请号：US11178629
申请日：2005-07-11
申请人： Seok-Min Jung , Ju-Hyung Kim
发明人： Seok-Min Jung , Ju-Hyung Kim
IPC分类号： H03L7/06
CPC分类号： H03L7/10 , H03L7/0893 , H03L7/093
摘要： An integrated circuit device includes a fast-locking phase locked loop (PLL). This PLL includes a phase-frequency detector and first and second charge pumps, which are responsive to first and second control signals generated by the phase-frequency detector. The first and second charge pumps have different current sourcing characteristics when the first control signal is active and different current sinking characteristics when the second control signal is active.
摘要翻译：集成电路器件包括快锁锁相环（PLL）。该PLL包括相位检测器和第一和第二电荷泵，其响应由相位频率检测器产生的第一和第二控制信号。当第二控制信号有效时，第一和第二电荷泵具有不同的电流源特性，当第二控制信号有效时，具有不同的电流吸收特性。

9. 发明授权

US10478275B2 Medical diagnostic apparatus having height-adjustable table for animals 有权
公开(公告)号：US10478275B2
公开(公告)日：2019-11-19
申请号：US15636724
申请日：2017-06-29
申请人： Ju-Hyung Kim
发明人： Ju-Hyung Kim
IPC分类号： A61D3/00 , A61G13/06 , A61B90/50 , A61B6/04 , A61B6/00
摘要： A medical diagnostic apparatus having a height-adjustable table for animals according to an embodiment of the present invention includes: a table where an animal is placed; a support stand supporting the table such that the table vertically moves and adjusting height of the table to move the table close to a floor; an X-ray detector disposed under the table and coupled to the support stand to move with the table; and an imaging stand spaced from the table, connected to the support stand, and having an X-ray tube for radiating X-rays to the X-ray detector.

10. 发明授权

US09112045B2 Nonvolatile memory device and fabricating method thereof 有权
标题翻译：非易失存储器件及其制造方法
公开(公告)号：US09112045B2
公开(公告)日：2015-08-18
申请号：US13775833
申请日：2013-02-25
申请人： Ju-Hyung Kim , Chang-Seok Kang , Woon-Kyung Lee
发明人： Ju-Hyung Kim , Chang-Seok Kang , Woon-Kyung Lee
IPC分类号： H01L29/792 , H01L29/66 , H01L29/423 , H01L29/51 , H01L27/115
CPC分类号： H01L29/792 , H01L27/11582 , H01L29/4234 , H01L29/513 , H01L29/66833 , H01L29/7926
摘要： A nonvolatile memory device comprises a channel pattern, a first interlayer dielectric film and a second interlayer dielectric film spaced apart from each other and stacked over each other, a gate pattern disposed between the first interlayer dielectric film and the second interlayer dielectric film, a trap layer disposed between the gate pattern and the channel pattern and a charge spreading inhibition layer disposed between the channel pattern and the first interlayer dielectric film and between the channel pattern and the second interlayer dielectric film. The charge spreading inhibition layer may include charges inside or on its surface. The charge spreading inhibition layer includes at least one of a metal oxide film or a metal nitride film or a metal oxynitride film having a greater dielectric constant than a silicon oxide film.
摘要翻译：非易失性存储器件包括彼此间隔开并且彼此堆叠的沟道图案，第一层间电介质膜和第二层间电介质膜，布置在第一层间电介质膜和第二层间电介质膜之间的栅极图案，阱设置在栅极图案和沟道图案之间的层，以及设置在沟道图案和第一层间电介质膜之间以及沟道图案和第二层间电介质膜之间的电荷扩展抑制层。电荷扩散抑制层可以包括其表面内部或其表面上的电荷。电荷扩散抑制层包括金属氧化物膜或金属氮化物膜或具有比氧化硅膜更大的介电常数的金属氧氮化物膜中的至少一种。

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