专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4317169A Data processing system having centralized memory refresh 失效
标题翻译：数据处理系统具有集中的内存刷新
公开(公告)号：US4317169A
公开(公告)日：1982-02-23
申请号：US12081
申请日：1979-02-14
申请人： William Panepinto, Jr. , Ming T. Miu , Chester M. Nibby, Jr. , Jian-Kuo Shen
发明人： William Panepinto, Jr. , Ming T. Miu , Chester M. Nibby, Jr. , Jian-Kuo Shen
IPC分类号： G06F12/00 , G11C11/406 , G06F13/00
CPC分类号： G11C11/406
摘要： In a data processing system which includes a central processing unit and one or more main memory units for storing program software instructions and program data, logic is provided within the CPU to signal the main memory units, comprised of semiconductor random access memory chips, that a memory refresh operation can be performed. The logic is organized such that the memory refresh operation signal may be given to the main memory units in parallel with and without detracting from other CPU operations. Further, logic is provided within the CPU to interrupt the CPU normal processing and perform a memory refresh operation if one has not been performed with a predetermined time period. Logic is provided within each main memory unit to accept the memory refresh signals from the CPU and to discard those memory refresh signals that would refresh the memory more frequently than required to retain the memory contents thus reducing main memory power consumption.
摘要翻译：在包括中央处理单元和用于存储程序软件指令和程序数据的一个或多个主存储器单元的数据处理系统中，在CPU内提供逻辑以对由半导体随机存取存储器芯片组成的主存储器单元进行信号，可以执行存储器刷新操作。逻辑被组织使得可以将存储器刷新操作信号并行并且不降低其他CPU操作的情况下给予主存储器单元。此外，在CPU内提供中断CPU正常处理的逻辑，并且如果在预定时间段内未执行存储器刷新操作则执行存储器刷新操作。在每个主存储器单元内提供逻辑以接受来自CPU的存储器刷新信号，并且丢弃将比保持存储器内容所需的频率更新的内存刷新信号，从而减少主存储器功耗的那些存储器刷新信号。

2. 发明授权

US5956522A Symmetric multiprocessing system with unified environment and distributed system functions 失效
公开(公告)号：US5956522A
公开(公告)日：1999-09-21
申请号：US405510
申请日：1995-03-16
申请人： James F. Bertone , Bruno DiPlacido, Jr. , Thomas F Joyce , Martin Massucci , Lance T. McNally , Thomas L. Murray, Jr. , Chester M. Nibby, Jr. , Michelle A. Pence , Marc Sanfacon , Jian-Kuo Shen , Jeffrey S. Somers , G. Lewis Steiner
发明人： James F. Bertone , Bruno DiPlacido, Jr. , Thomas F Joyce , Martin Massucci , Lance T. McNally , Thomas L. Murray, Jr. , Chester M. Nibby, Jr. , Michelle A. Pence , Marc Sanfacon , Jian-Kuo Shen , Jeffrey S. Somers , G. Lewis Steiner
IPC分类号： G06F12/08 , G06F13/16 , G06F13/368 , G06F13/00
CPC分类号： G06F13/1657 , G06F12/0831 , G06F13/1689 , G06F13/1694 , G06F13/368
摘要： A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assumes responsibility for its own aspects of these operations. In addition, the system provides improved system bus operation for transfer of data from memory.

3. 发明授权

US5517648A Symmetric multiprocessing system with unified environment and distributed system functions 失效
公开(公告)号：US5517648A
公开(公告)日：1996-05-14
申请号：US405550
申请日：1995-03-16
申请人： James F. Bertone , Bruno DiPlacido, Jr. , Thomas F. Joyce , Martin Massucci , Lance J. McNally , Thomas L. Murray, Jr. , Chester M. Nibby, Jr. , Michelle A. Pence , Marc Sanfacon , Jian-Kuo Shen , Jeffrey S. Somers , G. Lewis Steiner
发明人： James F. Bertone , Bruno DiPlacido, Jr. , Thomas F. Joyce , Martin Massucci , Lance J. McNally , Thomas L. Murray, Jr. , Chester M. Nibby, Jr. , Michelle A. Pence , Marc Sanfacon , Jian-Kuo Shen , Jeffrey S. Somers , G. Lewis Steiner
IPC分类号： G06F12/08 , G06F13/16 , G06F13/368 , G06F9/46
CPC分类号： G06F13/1657 , G06F12/0831 , G06F13/1689 , G06F13/1694 , G06F13/368
摘要： A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assumes responsibility for its own aspects of these operations. In addition, the system provides improved system bus operation for transfer of data from memory.

4. 发明授权

US4296467A Rotating chip selection technique and apparatus 失效
标题翻译：旋转芯片选择技术和装置
公开(公告)号：US4296467A
公开(公告)日：1981-10-20
申请号：US921292
申请日：1978-07-03
申请人： Chester M. Nibby, Jr. , William Panepinto, Jr.
发明人： Chester M. Nibby, Jr. , William Panepinto, Jr.
IPC分类号： G06F12/06 , G11C11/407 , G11C13/00
CPC分类号： G11C11/407 , G06F12/0669
摘要： A memory subsystem includes at least one up to a number of memory module boards identical in layout and construction. The board includes a number of memory chips which are positioned at an initial physical row location providing a predetermined number of addressable contiguous memory locations corresponding to a predetermined increment of memory capacity. The board further includes a register for receiving address signals for accessing the contents of a memory location, rotating chip selection circuits which include a set of switches and an arithmetic unit having first and second sets of input terminals. The first set of input terminals is connected to the register for receiving predetermined ones of the address signals representative of the physical row location of chips being addressed and the second set of input terminals are connected to receive signals from the set of switches. The arithmetic unit operates to perform a predetermined arithmetic operation upon the signals applied to the sets of input terminals to generate a set of logical row address signals for enabling the number of chips at the initial row location.
摘要翻译：存储器子系统包括至少一个在布局和结构上相同的多个存储器模块板。该板包括多个存储器芯片，这些存储器芯片位于初始物理行位置，提供对应于预定增量的存储器容量的预定数量的可寻址连续存储器位置。板还包括一个寄存器，用于接收访问存储器位置的内容的地址信号，旋转芯片选择电路包括一组开关和具有第一组和第二组输入端的运算单元。第一组输入端子连接到寄存器，用于接收表示正在寻址的芯片的物理行位置的预定的地址信号，并且第二组输入端子被连接以从该组开关接收信号。算术单元操作以对施加到输入端子组的信号执行预定的算术运算，以产生用于使初始行位置处的码片数量的一组逻辑行地址信号。

5. 发明授权

US06311286B1 Symmetric multiprocessing system with unified environment and distributed system functions 失效
标题翻译：具有统一环境和分布式系统功能的对称多处理系统
公开(公告)号：US06311286B1
公开(公告)日：2001-10-30
申请号：US08258752
申请日：1994-06-10
申请人： James F. Bertone , Bruno DiPlacido, Jr. , Thomas F Joyce , Martin Massucci , Lance J. McNally , Thomas L. Murray, Jr. , Chester M. Nibby, Jr. , Michelle A. Pence , Marc Sanfacon , Jian-Kuo Shen , Jeffrey S. Somers , G. Lewis Steiner
发明人： James F. Bertone , Bruno DiPlacido, Jr. , Thomas F Joyce , Martin Massucci , Lance J. McNally , Thomas L. Murray, Jr. , Chester M. Nibby, Jr. , Michelle A. Pence , Marc Sanfacon , Jian-Kuo Shen , Jeffrey S. Somers , G. Lewis Steiner
IPC分类号： G06F926
CPC分类号： G06F13/1657 , G06F12/0831 , G06F13/1689 , G06F13/1694 , G06F13/368
摘要： The invention is directed to a memory controller for use with memory having varying timing characteristics. In particular, the timing characteristics of the various memory devices are determined and used to generate timing signals commensurate with each particular memory device.
摘要翻译：本发明涉及一种与具有不同时序特征的存储器一起使用的存储器控制器。具体地，确定各种存储器件的定时特性并用于产生与每个特定存储器件相称的定时信号。

6. 发明授权

US5809340A Adaptively generating timing signals for access to various memory devices based on stored profiles 失效
标题翻译：基于存储的简档自适应地生成用于访问各种存储器设备的定时信号
公开(公告)号：US5809340A
公开(公告)日：1998-09-15
申请号：US909745
申请日：1997-08-12
申请人： James F. Bertone , Bruno DiPlacido, Jr. , Thomas F. Joyce , Martin Massucci , Lance J. McNally , Thomas L. Murray, Jr. , Chester M. Nibby, Jr. , Michelle A. Pence , Marc Sanfacon , Jian-Kuo Shen , Jeffrey S. Somers , G. Lewis Steiner , William S. Wu , Norman J. Rasmussen , Suresh K. Marisetty , Puthiya K. Nizar
发明人： James F. Bertone , Bruno DiPlacido, Jr. , Thomas F. Joyce , Martin Massucci , Lance J. McNally , Thomas L. Murray, Jr. , Chester M. Nibby, Jr. , Michelle A. Pence , Marc Sanfacon , Jian-Kuo Shen , Jeffrey S. Somers , G. Lewis Steiner , William S. Wu , Norman J. Rasmussen , Suresh K. Marisetty , Puthiya K. Nizar
IPC分类号： G06F12/08 , G06F13/16 , G06F13/368
CPC分类号： G06F13/1694 , G06F12/0831 , G06F13/1657 , G06F13/1689 , G06F13/368
摘要： Timing calculator means in a computer system are used to adaptively generate an appropriate access signal, to one of a plurality of memory types, based on first and second timing control values, wherein the first timing control value represents information specific to and limited to the start of a memory operation and wherein the second timing control value represents information representing other timing events. That is, the state machine of the present invention requires a distinct starting control value, separate from other timing values, for calculation of appropriate memory access parameters.
摘要翻译：基于第一和第二定时控制值，计算机系统中的定时计算器装置被用于自适应地生成适合多种存储器类型的存取信号，其中第一定时控制值表示特定于并限于开始的信息并且其中所述第二定时控制值表示表示其他定时事件的信息。也就是说，本发明的状态机需要与其他定时值分开的独特的启动控制值，用于计算适当的存储器访问参数。

7. 发明授权

US4916601A Means for transferring firmware signals between a control store and a microprocessor means through a reduced number of connections by transfer according to firmware signal function 失效
标题翻译：用于通过根据固件信号功能的转移通过减少数量的连接在控制存储器和微处理器装置之间传送固件信号的装置
公开(公告)号：US4916601A
公开(公告)日：1990-04-10
申请号：US286581
申请日：1988-12-19
申请人： Richard P. Kelly , Jian-Kuo Shen , Robert V. Ledoux , Chester M. Nibby, Jr.
发明人： Richard P. Kelly , Jian-Kuo Shen , Robert V. Ledoux , Chester M. Nibby, Jr.
IPC分类号： G06F9/22
CPC分类号： G06F9/223
摘要： A firmware controlled microprocessor plugged into a printed circuit board received firmware signals from a control store mounted on the printed circuit board. The number of pins required for transferring firmware signals is reduced by time sharing pins with firmware signal required for the full cycle of operation and firmware signal required only during the second half of the cycle of operation.
摘要翻译：插入印刷电路板的固件控制微处理器从安装在印刷电路板上的控制存储器接收固件信号。传输固件信号所需的引脚数量通过时间分配引脚减少，固件信号仅在操作周期的后半部分需要完整的操作周期和固件信号。

8. 发明授权

US4303993A Memory present apparatus 失效
标题翻译：存储器设备
公开(公告)号：US4303993A
公开(公告)日：1981-12-01
申请号：US83438
申请日：1979-10-10
申请人： William Panepinto, Jr. , Chester M. Nibby, Jr.
发明人： William Panepinto, Jr. , Chester M. Nibby, Jr.
IPC分类号： G06F12/06 , G11C8/12 , G11C13/00
CPC分类号： G06F12/0669 , G11C8/12
摘要： A memory subsystem includes at least one up to a number of memory module boards identical in layout and construction. The board includes a number of memory chips which are positioned in a number of physical row locations together providing a predetermined number of addressable contiguous memory locations corresponding to a predetermined increment of memory capacity. The board includes a set of switches whose input terminals are connected to receive predetermined ones of a plurality of address signals. These predetermined signals are coded specifying the segments of memory being accessed. The signals applied to the switch output terminals are logically combined and the resulting signal is applied to a group of memory present circuits connected to receive other ones of the address signals representative of the row of chips being addressed. By altering the set of switches, the group of memory present circuits can be conditioned to generate an output signal for indicating that the same increment is present for accessing within any one of a number of different segments thereby enabling the same board to be used in any available address slot position.
摘要翻译：存储器子系统包括至少一个在布局和结构上相同的多个存储器模块板。该板包括多个存储器芯片，这些存储器芯片位于多个物理行位置，一起提供对应于预定增量的存储器容量的预定数量的可寻址连续存储单元。该板包括一组开关，其输入端连接以接收多个地址信号中的预定的开关。这些预定信号被编码，指定被访问的存储器的段。施加到开关输出端子的信号被逻辑地组合，并且所得到的信号被施加到连接的一组存储器当前电路，以接收代表所寻址的芯片行的其他地址信号。通过改变开关组，可以调节存储器组电路以产生输出信号，以指示存在相同的增量用于在多个不同段中的任何一个中进行访问，从而使同一板可以用于任何可用的地址槽位置。

9. 发明授权

US5522069A Symmetric multiprocessing system with unified environment and distributed system functions 失效
公开(公告)号：US5522069A
公开(公告)日：1996-05-28
申请号：US258750
申请日：1994-06-10
申请人： James F. Bertone , Bruno DiPlacido, Jr. , Thomas F. Joyce , Martin Massucci , Lance J. McNally , Thomas L. Murray, Jr. , Chester M. Nibby, Jr. , Michelle A. Pence , Marc Sanfacon , Jian-Kuo Shen , Jeffrey S. Somers , G. Lewis Steiner , William S. Wu , Norman J. Rasmussen , Suresh K. Marisetty , Puthiya K. Nizar
发明人： James F. Bertone , Bruno DiPlacido, Jr. , Thomas F. Joyce , Martin Massucci , Lance J. McNally , Thomas L. Murray, Jr. , Chester M. Nibby, Jr. , Michelle A. Pence , Marc Sanfacon , Jian-Kuo Shen , Jeffrey S. Somers , G. Lewis Steiner , William S. Wu , Norman J. Rasmussen , Suresh K. Marisetty , Puthiya K. Nizar
IPC分类号： G06F12/08 , G06F13/16 , G06F13/368 , G06F13/00
CPC分类号： G06F13/1657 , G06F12/0831 , G06F13/1689 , G06F13/1694 , G06F13/368
摘要： A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assumes responsibility for its own aspects of these operations. In addition, the system provides improved system bus operation for transfer of data from memory.

10. 发明授权

US6125436A Symmetric multiprocessing system with unified environment and distributed system functions wherein bus operations related storage spaces are mapped into a single system address space 失效
标题翻译：具有统一环境和分布式系统功能的对称多处理系统，其中总线操作相关的存储空间映射到单个系统地址空间
公开(公告)号：US6125436A
公开(公告)日：2000-09-26
申请号：US855810
申请日：1997-05-12
申请人： James F. Bertone , Bruno DiPlacido, Jr. , Thomas F. Joyce , Martin Massucci , Lance J. McNally , Thomas L. Murray, Jr. , Chester M. Nibby, Jr. , Michelle A. Pence , Marc Sanfacon , Jian-Kuo Shen , Jeffrey S. Somers , G. Lewis Steiner
发明人： James F. Bertone , Bruno DiPlacido, Jr. , Thomas F. Joyce , Martin Massucci , Lance J. McNally , Thomas L. Murray, Jr. , Chester M. Nibby, Jr. , Michelle A. Pence , Marc Sanfacon , Jian-Kuo Shen , Jeffrey S. Somers , G. Lewis Steiner
IPC分类号： G06F12/08 , G06F13/16 , G06F13/368 , G06F12/00
CPC分类号： G06F13/1657 , G06F12/0831 , G06F13/1689 , G06F13/1694 , G06F13/368
摘要： A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assumes responsibility for its own aspects of these operations. In addition, the system provides improved system bus operation for transfer of data from memory.
摘要翻译：具有统一环境和分布式系统功能的对称多处理系统为系统中的所有功能单元提供统一的地址空间，同时在系统的功能单元上分配各种系统功能的执行，每个功能单元承担其自身方面的责任操作。此外，该系统提供改进的系统总线操作，用于从存储器传输数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式