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1. 发明授权

US5522069A Symmetric multiprocessing system with unified environment and distributed system functions 失效
公开(公告)号：US5522069A
公开(公告)日：1996-05-28
申请号：US258750
申请日：1994-06-10
申请人： James F. Bertone , Bruno DiPlacido, Jr. , Thomas F. Joyce , Martin Massucci , Lance J. McNally , Thomas L. Murray, Jr. , Chester M. Nibby, Jr. , Michelle A. Pence , Marc Sanfacon , Jian-Kuo Shen , Jeffrey S. Somers , G. Lewis Steiner , William S. Wu , Norman J. Rasmussen , Suresh K. Marisetty , Puthiya K. Nizar
发明人： James F. Bertone , Bruno DiPlacido, Jr. , Thomas F. Joyce , Martin Massucci , Lance J. McNally , Thomas L. Murray, Jr. , Chester M. Nibby, Jr. , Michelle A. Pence , Marc Sanfacon , Jian-Kuo Shen , Jeffrey S. Somers , G. Lewis Steiner , William S. Wu , Norman J. Rasmussen , Suresh K. Marisetty , Puthiya K. Nizar
IPC分类号： G06F12/08 , G06F13/16 , G06F13/368 , G06F13/00
CPC分类号： G06F13/1657 , G06F12/0831 , G06F13/1689 , G06F13/1694 , G06F13/368
摘要： A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assumes responsibility for its own aspects of these operations. In addition, the system provides improved system bus operation for transfer of data from memory.

2. 发明授权

US5809340A Adaptively generating timing signals for access to various memory devices based on stored profiles 失效
标题翻译：基于存储的简档自适应地生成用于访问各种存储器设备的定时信号
公开(公告)号：US5809340A
公开(公告)日：1998-09-15
申请号：US909745
申请日：1997-08-12
申请人： James F. Bertone , Bruno DiPlacido, Jr. , Thomas F. Joyce , Martin Massucci , Lance J. McNally , Thomas L. Murray, Jr. , Chester M. Nibby, Jr. , Michelle A. Pence , Marc Sanfacon , Jian-Kuo Shen , Jeffrey S. Somers , G. Lewis Steiner , William S. Wu , Norman J. Rasmussen , Suresh K. Marisetty , Puthiya K. Nizar
发明人： James F. Bertone , Bruno DiPlacido, Jr. , Thomas F. Joyce , Martin Massucci , Lance J. McNally , Thomas L. Murray, Jr. , Chester M. Nibby, Jr. , Michelle A. Pence , Marc Sanfacon , Jian-Kuo Shen , Jeffrey S. Somers , G. Lewis Steiner , William S. Wu , Norman J. Rasmussen , Suresh K. Marisetty , Puthiya K. Nizar
IPC分类号： G06F12/08 , G06F13/16 , G06F13/368
CPC分类号： G06F13/1694 , G06F12/0831 , G06F13/1657 , G06F13/1689 , G06F13/368
摘要： Timing calculator means in a computer system are used to adaptively generate an appropriate access signal, to one of a plurality of memory types, based on first and second timing control values, wherein the first timing control value represents information specific to and limited to the start of a memory operation and wherein the second timing control value represents information representing other timing events. That is, the state machine of the present invention requires a distinct starting control value, separate from other timing values, for calculation of appropriate memory access parameters.
摘要翻译：基于第一和第二定时控制值，计算机系统中的定时计算器装置被用于自适应地生成适合多种存储器类型的存取信号，其中第一定时控制值表示特定于并限于开始的信息并且其中所述第二定时控制值表示表示其他定时事件的信息。也就是说，本发明的状态机需要与其他定时值分开的独特的启动控制值，用于计算适当的存储器访问参数。

3. 发明授权

US06047355A Symmetric multiprocessing system with unified environment and distributed system functions 失效
标题翻译：具有统一环境和分布式系统功能的对称多处理系统
公开(公告)号：US06047355A
公开(公告)日：2000-04-04
申请号：US814606
申请日：1997-03-10
申请人： William S. Wu , Norman J. Rasmussen , Suresh K. Marisetty , Puthiya K. Nizar
发明人： William S. Wu , Norman J. Rasmussen , Suresh K. Marisetty , Puthiya K. Nizar
IPC分类号： G06F12/08 , G06F13/16 , G06F13/368 , G06F13/00
CPC分类号： G06F13/1657 , G06F12/0831 , G06F13/1689 , G06F13/1694 , G06F13/368
摘要： A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assumes responsibility for its own aspects of these operations. In addition, the system provides improved system bus operation for transfer of data from memory.
摘要翻译：具有统一环境和分布式系统功能的对称多处理系统为系统中的所有功能单元提供统一的地址空间，同时在系统的功能单元上分配各种系统功能的执行，每个功能单元承担其自身方面的责任操作。此外，该系统提供改进的系统总线操作，用于从存储器传输数据。

4. 发明授权

US6006291A High-throughput interface between a system memory controller and a peripheral device 失效
公开(公告)号：US6006291A
公开(公告)日：1999-12-21
申请号：US002130
申请日：1997-12-31
申请人： Norman J. Rasmussen , William S. Wu
发明人： Norman J. Rasmussen , William S. Wu
IPC分类号： G06F3/14 , G06F13/12 , G06F13/10 , G06F13/16
CPC分类号： G06F3/14 , G06F13/126
摘要： A high-throughput memory access interface allows higher data transfer rates between a system memory controller and video/graphics adapters than is possible using standard local bus architectures. The interface enables data to be written directly to a peripheral device at either one of two selectable speeds. The peripheral device may be a graphics adapter. A signal indicative of whether the adapter's write buffers are full is used to determine whether a write transaction to the adapter can proceed. If the transaction can not proceed at that time, it can be enqueued in the interface.

5. 发明授权

US06266719B1 High-throughput interface between a system memory controller and a peripheral device 有权
标题翻译：系统内存控制器和外围设备之间的高吞吐量接口
公开(公告)号：US06266719B1
公开(公告)日：2001-07-24
申请号：US09656192
申请日：2000-09-06
申请人： Norman J. Rasmussen , William S. Wu
发明人： Norman J. Rasmussen , William S. Wu
IPC分类号： G06F1328
CPC分类号： G06F3/14 , G06F13/126
摘要： A high-throughput memory access interface allows higher data transfer rates between a system memory controller and video/graphics adapters than is possible using standard local bus architectures. The interface enables data to be written directly to a peripheral device at either one of two selectable speeds. The peripheral device may be a graphics adapter. A signal indicative of whether the adapter's write buffers are full is used to determine whether a write transaction to the adapter can proceed. If the transaction can not proceed at that time, it can be enqueued in the interface.
摘要翻译：高通量存储器访问接口允许系统内存控制器和视频/图形适配器之间的数据传输速率高于使用标准本地总线架构的数据传输速率。该接口使数据可以以两种可选速度中的任意一种直接写入外围设备。外围设备可以是图形适配器。指示适配器的写入缓冲器是否满的信号用于确定到适配器的写入事务是否可以进行。如果事务当时无法继续，则可以在界面中排队。

6. 发明授权

US06434692B1 High-throughput interface between a system memory controller and a peripheral device 有权
公开(公告)号：US06434692B1
公开(公告)日：2002-08-13
申请号：US09792496
申请日：2001-02-23
申请人： Norman J. Rasmussen , William S. Wu
发明人： Norman J. Rasmussen , William S. Wu
IPC分类号： G06F1338
摘要： A high-throughput memory access interface allows higher data transfer rates between a system memory controller and video/graphics adapters than is possible using standard local bus architectures. The interface enables data to be written directly to a peripheral device at either one of two selectable speeds. The peripheral device may be a graphics adapter. A signal indicative of whether the adapter's write buffers are full is used to determine whether a write transaction to the adapter can proceed. If the transaction can not proceed at that time, it can be enqueued in the interface.

7. 发明授权

US6167468A High-throughput interface between a system memory controller and a peripheral device 有权
公开(公告)号：US6167468A
公开(公告)日：2000-12-26
申请号：US382885
申请日：1999-08-25
申请人： Norman J. Rasmussen , William S. Wu
发明人： Norman J. Rasmussen , William S. Wu
IPC分类号： G06F3/14 , G06F13/12 , G06F13/40 , G06F13/32
CPC分类号： G06F3/14 , G06F13/126
摘要： A high-throughput memory access interface allows higher data transfer rates between a system memory controller and video/graphics adapters than is possible using standard local bus architectures. The interface enables data to be written directly to a peripheral device at either one of two selectable speeds. The peripheral device may be a graphics adapter. A signal indicative of whether the adapter's write buffers are full is used to determine whether a write transaction to the adapter can proceed. If the transaction can not proceed at that time, it can be enqueued in the interface.

8. 发明授权

US5651137A Scalable cache attributes for an input/output bus 失效
标题翻译：输入/输出总线的可扩展缓存属性
公开(公告)号：US5651137A
公开(公告)日：1997-07-22
申请号：US420494
申请日：1995-04-12
申请人： Peter D. MacWilliams , Norman J. Rasmussen , Nicholas D. Wade , William S. F. Wu
发明人： Peter D. MacWilliams , Norman J. Rasmussen , Nicholas D. Wade , William S. F. Wu
IPC分类号： G06F12/08
CPC分类号： G06F12/0831
摘要： Memory bus extensions to a high speed peripheral bus are presented. Specifically, sideband signals are used to overlay advanced mechanisms for cache attribute mapping, cache consistency cycles, and dual processor support onto a high speed peripheral bus. In the case of cache attribute mapping, three cache memory attribute signals that have been supported in previous processors and caches are replaced by two cache attribute signals that maintain all the functionality of the three original signals. In the case of cache consistency cycles, advanced modes of operation are presented. These include support of fast writes, the discarding of write back data by a cache for full cache line writes, and read intervention that permits a cache to supply data in response to a memory read. In the case of dual processor support, several new signals and an associated protocol for support of dual processors are presented. Specific support falls into three areas: the extension of snooping to support multiple caches, the support of shared data between the two processors, and the provision of a processor and upgrade arbitration protocol that permits dual processors to share a single grant signal line.
摘要翻译：介绍了高速外设总线的内存总线扩展。具体来说，边带信号用于将高速缓存属性映射，高速缓存一致性周期和双处理器支持的高级机制覆盖到高速外设总线上。在高速缓存属性映射的情况下，先前处理器和高速缓存中支持的三个高速缓存存储器属性信号被保持三个原始信号的所有功能的两个高速缓存属性信号所取代。在缓存一致性周期的情况下，提供高级操作模式。这些包括支持快速写入，通过缓存对完全高速缓存行写入的写回数据的丢弃以及允许高速缓存提供响应于存储器读取的数据的读取干预。在双处理器支持的情况下，呈现了用于支持双处理器的几个新信号和相关协议。具体支持分为以下三个方面：扩展侦听以支持多个缓存，支持两个处理器之间的共享数据，以及提供处理器和升级仲裁协议，允许双处理器共享一个授权信号线。

9. 发明授权

US06502146B1 Apparatus and method for dedicated interconnection over a shared external bus 失效
标题翻译：通过共享外部总线进行专用互连的装置和方法
公开(公告)号：US06502146B1
公开(公告)日：2002-12-31
申请号：US09537087
申请日：2000-03-29
申请人： Norman J. Rasmussen , Brad W. Hosler , Darren Abramson , Michael J. McTague
发明人： Norman J. Rasmussen , Brad W. Hosler , Darren Abramson , Michael J. McTague
IPC分类号： G06F1300
CPC分类号： G06F13/385
摘要： Apparatus and methods to control an external bus. In one embodiment, an apparatus includes an external bus port and an external bus controller. The external bus controller can include a first register interface to receive a first set of data and a second register interface to receive a second set of data. The external bus controller can send the first set of data and the second set of data to said external bus port.
摘要翻译：控制外部总线的装置和方法。在一个实施例中，装置包括外部总线端口和外部总线控制器。外部总线控制器可以包括用于接收第一组数据的第一寄存器接口和用于接收第二组数据的第二寄存器接口。外部总线控制器可以将第一组数据和第二组数据发送到所述外部总线端口。

10. 发明授权

US5948094A Method and apparatus for executing multiple transactions within a single arbitration cycle 失效
标题翻译：在单个仲裁周期内执行多个事务的方法和装置
公开(公告)号：US5948094A
公开(公告)日：1999-09-07
申请号：US932745
申请日：1997-09-17
申请人： Gary A. Solomon , Norman J. Rasmussen , Peter D. MacWilliams
发明人： Gary A. Solomon , Norman J. Rasmussen , Peter D. MacWilliams
IPC分类号： G06F13/362 , G06F13/14
CPC分类号： G06F13/3625
摘要： A method of arbitrating among bus agents, wherein a bus agent is permitted multiple transactions within a single arbitration cycle. An arbitration event is initiated, and a request from a bus agent is granted to that bus agent for executing a transaction. A timer is started and the transaction is executed. If the timer does not expire before the transaction is completed, another request from that same bus agent is granted to the bus agent for executing an additional transaction before a subsequent arbitration event is initiated.
摘要翻译：一种在总线代理之间进行仲裁的方法，其中总线代理被允许在单个仲裁周期内的多个事务。启动仲裁事件，并向总线代理授予来自总线代理的请求以执行事务。启动定时器并执行事务。如果定时器在事务完成之前没有到期，那么来自该相同总线代理的另一个请求将被授予总线代理，以便在后续仲裁事件发起之前执行附加事务。

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