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1. 发明授权

US4916601A Means for transferring firmware signals between a control store and a microprocessor means through a reduced number of connections by transfer according to firmware signal function 失效
标题翻译：用于通过根据固件信号功能的转移通过减少数量的连接在控制存储器和微处理器装置之间传送固件信号的装置
公开(公告)号：US4916601A
公开(公告)日：1990-04-10
申请号：US286581
申请日：1988-12-19
申请人： Richard P. Kelly , Jian-Kuo Shen , Robert V. Ledoux , Chester M. Nibby, Jr.
发明人： Richard P. Kelly , Jian-Kuo Shen , Robert V. Ledoux , Chester M. Nibby, Jr.
IPC分类号： G06F9/22
CPC分类号： G06F9/223
摘要： A firmware controlled microprocessor plugged into a printed circuit board received firmware signals from a control store mounted on the printed circuit board. The number of pins required for transferring firmware signals is reduced by time sharing pins with firmware signal required for the full cycle of operation and firmware signal required only during the second half of the cycle of operation.
摘要翻译：插入印刷电路板的固件控制微处理器从安装在印刷电路板上的控制存储器接收固件信号。传输固件信号所需的引脚数量通过时间分配引脚减少，固件信号仅在操作周期的后半部分需要完整的操作周期和固件信号。

2. 发明授权

US5956522A Symmetric multiprocessing system with unified environment and distributed system functions 失效
公开(公告)号：US5956522A
公开(公告)日：1999-09-21
申请号：US405510
申请日：1995-03-16
申请人： James F. Bertone , Bruno DiPlacido, Jr. , Thomas F Joyce , Martin Massucci , Lance T. McNally , Thomas L. Murray, Jr. , Chester M. Nibby, Jr. , Michelle A. Pence , Marc Sanfacon , Jian-Kuo Shen , Jeffrey S. Somers , G. Lewis Steiner
发明人： James F. Bertone , Bruno DiPlacido, Jr. , Thomas F Joyce , Martin Massucci , Lance T. McNally , Thomas L. Murray, Jr. , Chester M. Nibby, Jr. , Michelle A. Pence , Marc Sanfacon , Jian-Kuo Shen , Jeffrey S. Somers , G. Lewis Steiner
IPC分类号： G06F12/08 , G06F13/16 , G06F13/368 , G06F13/00
CPC分类号： G06F13/1657 , G06F12/0831 , G06F13/1689 , G06F13/1694 , G06F13/368
摘要： A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assumes responsibility for its own aspects of these operations. In addition, the system provides improved system bus operation for transfer of data from memory.

3. 发明授权

US5517648A Symmetric multiprocessing system with unified environment and distributed system functions 失效
公开(公告)号：US5517648A
公开(公告)日：1996-05-14
申请号：US405550
申请日：1995-03-16
申请人： James F. Bertone , Bruno DiPlacido, Jr. , Thomas F. Joyce , Martin Massucci , Lance J. McNally , Thomas L. Murray, Jr. , Chester M. Nibby, Jr. , Michelle A. Pence , Marc Sanfacon , Jian-Kuo Shen , Jeffrey S. Somers , G. Lewis Steiner
发明人： James F. Bertone , Bruno DiPlacido, Jr. , Thomas F. Joyce , Martin Massucci , Lance J. McNally , Thomas L. Murray, Jr. , Chester M. Nibby, Jr. , Michelle A. Pence , Marc Sanfacon , Jian-Kuo Shen , Jeffrey S. Somers , G. Lewis Steiner
IPC分类号： G06F12/08 , G06F13/16 , G06F13/368 , G06F9/46
CPC分类号： G06F13/1657 , G06F12/0831 , G06F13/1689 , G06F13/1694 , G06F13/368
摘要： A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assumes responsibility for its own aspects of these operations. In addition, the system provides improved system bus operation for transfer of data from memory.

4. 发明授权

US06311286B1 Symmetric multiprocessing system with unified environment and distributed system functions 失效
标题翻译：具有统一环境和分布式系统功能的对称多处理系统
公开(公告)号：US06311286B1
公开(公告)日：2001-10-30
申请号：US08258752
申请日：1994-06-10
申请人： James F. Bertone , Bruno DiPlacido, Jr. , Thomas F Joyce , Martin Massucci , Lance J. McNally , Thomas L. Murray, Jr. , Chester M. Nibby, Jr. , Michelle A. Pence , Marc Sanfacon , Jian-Kuo Shen , Jeffrey S. Somers , G. Lewis Steiner
发明人： James F. Bertone , Bruno DiPlacido, Jr. , Thomas F Joyce , Martin Massucci , Lance J. McNally , Thomas L. Murray, Jr. , Chester M. Nibby, Jr. , Michelle A. Pence , Marc Sanfacon , Jian-Kuo Shen , Jeffrey S. Somers , G. Lewis Steiner
IPC分类号： G06F926
CPC分类号： G06F13/1657 , G06F12/0831 , G06F13/1689 , G06F13/1694 , G06F13/368
摘要： The invention is directed to a memory controller for use with memory having varying timing characteristics. In particular, the timing characteristics of the various memory devices are determined and used to generate timing signals commensurate with each particular memory device.
摘要翻译：本发明涉及一种与具有不同时序特征的存储器一起使用的存储器控制器。具体地，确定各种存储器件的定时特性并用于产生与每个特定存储器件相称的定时信号。

5. 发明授权

US5809340A Adaptively generating timing signals for access to various memory devices based on stored profiles 失效
标题翻译：基于存储的简档自适应地生成用于访问各种存储器设备的定时信号
公开(公告)号：US5809340A
公开(公告)日：1998-09-15
申请号：US909745
申请日：1997-08-12
申请人： James F. Bertone , Bruno DiPlacido, Jr. , Thomas F. Joyce , Martin Massucci , Lance J. McNally , Thomas L. Murray, Jr. , Chester M. Nibby, Jr. , Michelle A. Pence , Marc Sanfacon , Jian-Kuo Shen , Jeffrey S. Somers , G. Lewis Steiner , William S. Wu , Norman J. Rasmussen , Suresh K. Marisetty , Puthiya K. Nizar
发明人： James F. Bertone , Bruno DiPlacido, Jr. , Thomas F. Joyce , Martin Massucci , Lance J. McNally , Thomas L. Murray, Jr. , Chester M. Nibby, Jr. , Michelle A. Pence , Marc Sanfacon , Jian-Kuo Shen , Jeffrey S. Somers , G. Lewis Steiner , William S. Wu , Norman J. Rasmussen , Suresh K. Marisetty , Puthiya K. Nizar
IPC分类号： G06F12/08 , G06F13/16 , G06F13/368
CPC分类号： G06F13/1694 , G06F12/0831 , G06F13/1657 , G06F13/1689 , G06F13/368
摘要： Timing calculator means in a computer system are used to adaptively generate an appropriate access signal, to one of a plurality of memory types, based on first and second timing control values, wherein the first timing control value represents information specific to and limited to the start of a memory operation and wherein the second timing control value represents information representing other timing events. That is, the state machine of the present invention requires a distinct starting control value, separate from other timing values, for calculation of appropriate memory access parameters.
摘要翻译：基于第一和第二定时控制值，计算机系统中的定时计算器装置被用于自适应地生成适合多种存储器类型的存取信号，其中第一定时控制值表示特定于并限于开始的信息并且其中所述第二定时控制值表示表示其他定时事件的信息。也就是说，本发明的状态机需要与其他定时值分开的独特的启动控制值，用于计算适当的存储器访问参数。

6. 发明授权

US4317169A Data processing system having centralized memory refresh 失效
标题翻译：数据处理系统具有集中的内存刷新
公开(公告)号：US4317169A
公开(公告)日：1982-02-23
申请号：US12081
申请日：1979-02-14
申请人： William Panepinto, Jr. , Ming T. Miu , Chester M. Nibby, Jr. , Jian-Kuo Shen
发明人： William Panepinto, Jr. , Ming T. Miu , Chester M. Nibby, Jr. , Jian-Kuo Shen
IPC分类号： G06F12/00 , G11C11/406 , G06F13/00
CPC分类号： G11C11/406
摘要： In a data processing system which includes a central processing unit and one or more main memory units for storing program software instructions and program data, logic is provided within the CPU to signal the main memory units, comprised of semiconductor random access memory chips, that a memory refresh operation can be performed. The logic is organized such that the memory refresh operation signal may be given to the main memory units in parallel with and without detracting from other CPU operations. Further, logic is provided within the CPU to interrupt the CPU normal processing and perform a memory refresh operation if one has not been performed with a predetermined time period. Logic is provided within each main memory unit to accept the memory refresh signals from the CPU and to discard those memory refresh signals that would refresh the memory more frequently than required to retain the memory contents thus reducing main memory power consumption.
摘要翻译：在包括中央处理单元和用于存储程序软件指令和程序数据的一个或多个主存储器单元的数据处理系统中，在CPU内提供逻辑以对由半导体随机存取存储器芯片组成的主存储器单元进行信号，可以执行存储器刷新操作。逻辑被组织使得可以将存储器刷新操作信号并行并且不降低其他CPU操作的情况下给予主存储器单元。此外，在CPU内提供中断CPU正常处理的逻辑，并且如果在预定时间段内未执行存储器刷新操作则执行存储器刷新操作。在每个主存储器单元内提供逻辑以接受来自CPU的存储器刷新信号，并且丢弃将比保持存储器内容所需的频率更新的内存刷新信号，从而减少主存储器功耗的那些存储器刷新信号。

7. 发明授权

US5522069A Symmetric multiprocessing system with unified environment and distributed system functions 失效
公开(公告)号：US5522069A
公开(公告)日：1996-05-28
申请号：US258750
申请日：1994-06-10
申请人： James F. Bertone , Bruno DiPlacido, Jr. , Thomas F. Joyce , Martin Massucci , Lance J. McNally , Thomas L. Murray, Jr. , Chester M. Nibby, Jr. , Michelle A. Pence , Marc Sanfacon , Jian-Kuo Shen , Jeffrey S. Somers , G. Lewis Steiner , William S. Wu , Norman J. Rasmussen , Suresh K. Marisetty , Puthiya K. Nizar
发明人： James F. Bertone , Bruno DiPlacido, Jr. , Thomas F. Joyce , Martin Massucci , Lance J. McNally , Thomas L. Murray, Jr. , Chester M. Nibby, Jr. , Michelle A. Pence , Marc Sanfacon , Jian-Kuo Shen , Jeffrey S. Somers , G. Lewis Steiner , William S. Wu , Norman J. Rasmussen , Suresh K. Marisetty , Puthiya K. Nizar
IPC分类号： G06F12/08 , G06F13/16 , G06F13/368 , G06F13/00
CPC分类号： G06F13/1657 , G06F12/0831 , G06F13/1689 , G06F13/1694 , G06F13/368
摘要： A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assumes responsibility for its own aspects of these operations. In addition, the system provides improved system bus operation for transfer of data from memory.

8. 发明授权

US6125436A Symmetric multiprocessing system with unified environment and distributed system functions wherein bus operations related storage spaces are mapped into a single system address space 失效
标题翻译：具有统一环境和分布式系统功能的对称多处理系统，其中总线操作相关的存储空间映射到单个系统地址空间
公开(公告)号：US6125436A
公开(公告)日：2000-09-26
申请号：US855810
申请日：1997-05-12
申请人： James F. Bertone , Bruno DiPlacido, Jr. , Thomas F. Joyce , Martin Massucci , Lance J. McNally , Thomas L. Murray, Jr. , Chester M. Nibby, Jr. , Michelle A. Pence , Marc Sanfacon , Jian-Kuo Shen , Jeffrey S. Somers , G. Lewis Steiner
发明人： James F. Bertone , Bruno DiPlacido, Jr. , Thomas F. Joyce , Martin Massucci , Lance J. McNally , Thomas L. Murray, Jr. , Chester M. Nibby, Jr. , Michelle A. Pence , Marc Sanfacon , Jian-Kuo Shen , Jeffrey S. Somers , G. Lewis Steiner
IPC分类号： G06F12/08 , G06F13/16 , G06F13/368 , G06F12/00
CPC分类号： G06F13/1657 , G06F12/0831 , G06F13/1689 , G06F13/1694 , G06F13/368
摘要： A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assumes responsibility for its own aspects of these operations. In addition, the system provides improved system bus operation for transfer of data from memory.
摘要翻译：具有统一环境和分布式系统功能的对称多处理系统为系统中的所有功能单元提供统一的地址空间，同时在系统的功能单元上分配各种系统功能的执行，每个功能单元承担其自身方面的责任操作。此外，该系统提供改进的系统总线操作，用于从存储器传输数据。

9. 发明授权

US4451880A Memory controller with interleaved queuing apparatus 失效
标题翻译：具有交错排队装置的存储控制器
公开(公告)号：US4451880A
公开(公告)日：1984-05-29
申请号：US202821
申请日：1980-10-31
申请人： Robert B. Johnson , Chester M. Nibby, Jr.
发明人： Robert B. Johnson , Chester M. Nibby, Jr.
IPC分类号： G06F12/00 , G06F12/06 , G06F13/16 , G06F13/28 , H04L25/49 , G06F13/00
CPC分类号： G06F13/1642 , G06F13/28
摘要： A memory controller controls the operation of a number of memory module units and includes a number of queues which couple to the module units. Each queue includes an address queue register, a control queue register and a data queue register. Each address queue register has tristate control for independent operation. Control circuits which couple to the queue address, control and data registers assign memory cycles between queues on an alternate basis when the queue control registers store requests which are being processed. This enables the interleaving of memory requests which eliminates processing delays particularly in cases where such requests involve multiword transfers over successive memory cycles of operation.
摘要翻译：存储器控制器控制多个存储器模块单元的操作，并且包括耦合到模块单元的多个队列。每个队列包括地址队列寄存器，控制队列寄存器和数据队列寄存器。每个地址队列寄存器都有三态控制，用于独立操作。当队列控制寄存器存储正在处理的请求时，耦合到队列地址，控制和数据寄存器的控制电路在备用的队列之间分配存储器周期。这使得能够消除处理延迟的存储器请求的交织，特别是在这种请求涉及在连续存储器操作周期中的多字传输的情况下。

10. 发明授权

US4376972A Sequential word aligned address apparatus 失效
标题翻译：顺序字对齐地址设备
公开(公告)号：US4376972A
公开(公告)日：1983-03-15
申请号：US110521
申请日：1980-01-08
申请人： Robert B. Johnson , Chester M. Nibby, Jr. , Dana W. Moore
发明人： Robert B. Johnson , Chester M. Nibby, Jr. , Dana W. Moore
IPC分类号： G11C11/401 , G06F12/02 , G06F12/04 , G06F12/06 , G06F13/12 , G06F13/00
CPC分类号： G06F12/04 , G06F12/02
摘要： A memory subsystem which couples to a multiword bus for processing memory requests received therefrom includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem further includes an adder circuit, a pair of tri-state operated address register circuits and timing circuits. The address circuits include a pair of tri-state operated address registers which couple to the bus and to the set of address lines to each memory unit. In response to a memory request, the registers store row and column address portions of a chip address of the memory request. A multibit adder circuit is connected to increment by one the low order row address when the least significant address bits of the memory request indicate a subboundary address condition thereby enabling access to a pair of sequential word locations. Whenever a memory request specifies an address which cannot access a double word, boundary circuits upon detecting the condition cause the timing circuits to generate only timing signals necessary for accessing the first word location.
摘要翻译：耦合到多字总线以用于处理从其接收的存储器请求的存储器子系统包括至少一对独立可寻址的动态存储器模块单元。每个存储器单元包括多行随机存取存储器（RAM）芯片。子系统还包括加法器电路，一对三态操作地址寄存器电路和定时电路。地址电路包括一对三态操作地址寄存器，其耦合到总线和到每个存储器单元的地址线集合。响应于存储器请求，寄存器存储存储器请求的芯片地址的行和列地址部分。当存储器请求的最低有效地址位指示子边界地址条件从而使得能够访问一对顺序字位置时，多位加法器电路被连接以递增一个低位行地址。每当存储器请求指定不能访问双字的地址时，边界电路在检测到条件时，使定时电路仅产生访问第一字位置所必需的定时信号。

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