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1. 发明授权

US06961347B1 High-speed interconnection link having automated lane reordering 有权
标题翻译：具有自动车道重新排序的高速互连链路
公开(公告)号：US06961347B1
公开(公告)日：2005-11-01
申请号：US09597190
申请日：2000-06-20
申请人： William P. Bunton , John Krause , Patricia L. Whiteside
发明人： William P. Bunton , John Krause , Patricia L. Whiteside
IPC分类号： H04J3/16 , H04L25/14
CPC分类号： H04L25/14
摘要： A multi-lane link that automatically detects if the lanes in the link have been reordered and corrects the order of the lanes. In one embodiment, the link includes a transmitter and a receiver. The receiver is configured to receive a plurality of lanes and includes a receiver logic circuit configured to receive signals from each of the plurality of lanes. Lane misordering is corrected during a training sequence in which a first training sequence and a second training sequence are bilaterally transmitted between the transmitter and receiver. The receiver monitors the training sequence for symbols that are unique to each lane and if an unexpected symbol is detected in the lane, the receiver logic circuit will correct the order of the lanes. The link further comprises a transmitter logic circuit configured to transmit signals to the lanes. The transmitter logic circuit is configured to reorder the sequence of the signals transmitted to the lanes if the transmitter does not detect a response from the receiver. The transmitter logic circuit may consist of a bank of multiplexers configured to transmit a selected one of two input signals to be transmitted through a lane. Similarly, the receiver logic circuit may comprises a bank of multiplexers configured to transmit a selected one of two input signals received from a lane. The unique lane identifiers symbols are preferably insensitive to binary inversion and are preferably 10-bit symbols compatible with an 8B/10B encoding scheme.
摘要翻译：一个多通道链接，可以自动检测链路中的通道是否重新排序，并纠正通道的顺序。在一个实施例中，链路包括发射机和接收机。接收机被配置为接收多个车道，并且包括被配置为从多个车道中的每一条车道接收信号的接收机逻辑电路。在训练序列期间校正车道排序，其中第一训练序列和第二训练序列在发射机和接收机之间被双向传输。接收机监视每个通道唯一的符号的训练序列，如果在通道中检测到意外符号，则接收机逻辑电路将校正车道的顺序。该链路还包括被配置为向车道传输信号的发射机逻辑电路。发射机逻辑电路被配置为如果发射机未检测到来自接收机的响应，则重新排序发送到车道的信号的序列。发射机逻辑电路可以由一组多路复用器组成，其被配置为发送要通过车道传输的两个输入信号中的所选择的一个。类似地，接收器逻辑电路可以包括一组复用器，其被配置为发送从通道接收的两个输入信号中选择的一个。唯一的车道标识符符号优选地对二进制反转不敏感，并且优选地是与8B / 10B编码方案兼容的10位符号。

2. 发明授权

US07197100B2 High-speed interconnection adapter having automated lane de-skew 有权
标题翻译：具有自动车道偏斜的高速互连适配器
公开(公告)号：US07197100B2
公开(公告)日：2007-03-27
申请号：US10680913
申请日：2003-10-08
申请人： William P. Bunton , John Krause , Scott Smith , Patricia L. Whiteside
发明人： William P. Bunton , John Krause , Scott Smith , Patricia L. Whiteside
IPC分类号： H04L25/00 , H04L7/00
CPC分类号： H04L25/14
摘要： An adapter that buffers received symbols and automatically determines and corrects for skew between lanes is disclosed. In one embodiment, the adapter is a part of a network that includes a first and second devices coupled together by a communications link having multiple independent serial lanes. The first device initiates communication by repeatedly transmitting a training sequence that includes a start symbol for each lane. An adapter in the second device includes a set of buffers each configured to receive the symbols conveyed by a corresponding serial lane. The buffers are coupled to a reconstruction circuit that removes one “symbol group” at a time from the buffers. A symbol group is made up of one symbol from each buffer. The reconstruction circuit removes symbol groups until a start symbol is detected. If the start symbol is not detected in all buffers, output from the buffers having start symbols is temporarily suspended.
摘要翻译：公开了缓冲接收到的符号并自动确定和校正车道之间的偏斜的适配器。在一个实施例中，适配器是网络的一部分，其包括通过具有多个独立串行通道的通信链路耦合在一起的第一和第二设备。第一设备通过重复发送包括每个车道的起始符号的训练序列来发起通信。第二设备中的适配器包括一组缓冲器，每个缓冲器被配置为接收由相应串行通道传送的符号。缓冲器被耦合到重建电路，其从缓冲器一次移除一个“符号组”。符号组由每个缓冲区中的一个符号组成。重建电路去除符号组，直到检测到起始符号为止。如果在所有缓冲区中没有检测到起始符号，则具有起始符号的缓冲区的输出被暂停。

3. 发明授权

US06690757B1 High-speed interconnection adapter having automated lane de-skew 有权
标题翻译：具有自动车道偏斜的高速互连适配器
公开(公告)号：US06690757B1
公开(公告)日：2004-02-10
申请号：US09596980
申请日：2000-06-20
申请人： William P. Bunton , John Krause , Scott Smith , Patricia L. Whiteside
发明人： William P. Bunton , John Krause , Scott Smith , Patricia L. Whiteside
IPC分类号： H04L2500
CPC分类号： H04L25/14
摘要： An adapter that buffers received symbols and automatically determines and corrects for skew between lanes is disclosed. In one embodiment, the adapter is a part of a network that includes a first and second devices coupled together by a communications link having multiple independent serial lanes. The first device Initiates communication by repeatedly transmitting a training sequence that includes a start symbol for each lane. An adapter in the second device includes a set of buffers each configured to receive the symbols conveyed by a corresponding serial lane. The buffers are coupled to a reconstruction circuit that removes one “symbol groups” at a time from the buffers. A symbol group is made up of one symbol from each buffer. The reconstruction circuit removes symbol groups until a start symbol is detected. If the start symbol is not detected in all buffers, output from buffers having start symbols is temporarily suspended.
摘要翻译：公开了缓冲接收到的符号并自动确定和校正车道之间的偏斜的适配器。在一个实施例中，适配器是网络的一部分，其包括通过具有多个独立串行通道的通信链路耦合在一起的第一和第二设备。第一设备通过重复地发送包括每个通道的开始符号的训练序列来启动通信。第二设备中的适配器包括一组缓冲器，每个缓冲器被配置为接收由相应串行通道传送的符号。缓冲器被耦合到重建电路，其从缓冲器一次移除一个“符号组”。符号组由每个缓冲区中的一个符号组成。重建电路去除符号组，直到检测到起始符号为止。如果在所有缓冲区中没有检测到起始符号，则从具有起始符号的缓冲区输出暂时停止。

4. 发明授权

US06865231B1 High-speed interconnection adapter having automated crossed differential pair correction 失效
标题翻译：具有自动交叉差分对校正的高速互连适配器
公开(公告)号：US06865231B1
公开(公告)日：2005-03-08
申请号：US09597192
申请日：2000-06-20
申请人： William P. Bunton , John Krause , Patricia L. Whiteside
发明人： William P. Bunton , John Krause , Patricia L. Whiteside
IPC分类号： H04L25/34
CPC分类号： H04L25/085
摘要： An adapter configured to automatically detect and compensate for differential signal inversion is herein disclosed. In one embodiment, the adapter is part of a computer network having differential conductor pairs conveying differential signals between network devices. The network devices include adapters coupled to transmit and receive signals via the differential conductor pairs. The adapter preferably includes a lane receiver, a decoder, and a synchronization circuit. The lane receiver is configured to receive a single differential signal and to convert the differential signal into a sequence of code symbols. The decoder decodes the code symbols to produce a sequence of received symbols. The synchronization circuit examines the sequence of received symbols to determine if it is incorrect due to inversion of the differential signal, and if so, it causes the lane receiver to correct for the differential signal inversion. It is expected that the received symbol sequence will include a training symbol sequence which will have a start symbol whose decoded value is unaffected by differential signal inversion, and a training symbol whose decoded value is indicative of the presence or absence of invasion. The synchronization circuit, upon identifying the training sequence, will thus be able to determine whether inversion exists and be able to automatically correct for it.
摘要翻译：本文公开了一种被配置为自动检测和补偿差分信号反相的适配器。在一个实施例中，适配器是具有在网络设备之间传送差分信号的差分导体对的计算机网络的一部分。网络设备包括耦合到经由差分导体对发送和接收信号的适配器。适配器优选地包括通道接收器，解码器和同步电路。车道接收器被配置为接收单个差分信号并且将差分信号转换成代码符号序列。解码器对码符号进行解码以产生接收符号的序列。同步电路检查接收到的符号的序列，以确定由于差分信号的反相而不正确，如果是，则使得通道接收机校正差分信号反相。预期所接收的符号序列将包括训练符号序列，该训练符号序列将具有其解码值不受差分信号反相影响的起始符号，以及其解码值表示存在或不存在入侵的训练符号。因此，同步电路在识别训练序列时将能够确定反转是否存在并能够自动校正。

5. 发明授权

US5293636A Module for insertion into a multi-module system having electronic keying for preventing power to improperly connected modules with improperly configured diode connections 失效
标题翻译：用于插入具有电子键控的多模块系统的模块，用于防止由于未正确配置的二极管连接而使不正确连接的模块的电力
公开(公告)号：US5293636A
公开(公告)日：1994-03-08
申请号：US996728
申请日：1992-12-24
申请人： William P. Bunton , John M. Brown , Patricia L. Whiteside
发明人： William P. Bunton , John M. Brown , Patricia L. Whiteside
IPC分类号： G06F3/00 , G06F13/40 , H05K1/14 , G06F1/26 , G06F15/08
CPC分类号： G06F13/409 , H05K1/14 , Y10S439/955 , Y10T307/944
摘要： A computer system with a number of subsystems or modules on separate circuit boards employs electronic keying to ensure proper configuration of these boards. A power key arrangement associated with a plug-in connector enables a separate power supply for each set of boards. A power supply turn-on signal is routed through a uniquely-configured connector path for each board, so the power supply turn-on is inhibited for improper configurations. The uniquely-configured connector path may use either a series or a parallel implementation. The series implementation employs a set of diodes connected for conduction in either of two directions, with the mating connector having its conductor paths connected to match the diode configuration; in this manner, the power supply enable signal can only flow through the series path if the proper board is plugged into a properly-coded slot, in which case the power supply to activate this board is activated through the series path including the diodes. The parallel implementation employs a given number of connector pins to establish the coding for each board, and each pin is either open-circuited or connected to ground; if this coding of the subsystem board is not the same as that of the slot into which it is plugged then the power supply activation signal will be shorted to ground by one or the other of the coded pins.
摘要翻译：在单独的电路板上具有多个子系统或模块的计算机系统采用电子键控来确保这些板的正确配置。与插入式连接器相关联的电源键配置可为每组电路板提供单独的电源。电源开启信号通过每个电路板的独特配置的连接器路径布线，因此不正确的配置禁止电源接通。唯一配置的连接器路径可以使用串行或并行实现。串联实现采用一组二极管，连接用于在两个方向中的任一方向上传导，其中配合连接器的导体路径连接以匹配二极管配置; 以这种方式，如果适当的板插入正确编码的插槽中，则电源使能信号只能流过串联路径，在这种情况下，通过包括二极管的串联路径来激活该电路板的电源。并行实现采用给定数量的连接器引脚来建立每个板的编码，并且每个引脚是开路的或连接到地; 如果子系统板的编码与其被插入的插槽的编码不同，则电源激活信号将被一个或另一个编码引脚短路到地。

6. 发明授权

US5203004A Multi-board system having electronic keying and preventing power to improperly connected plug-in board with improperly configured diode connections 失效
标题翻译：具有电子键控功能的多板系统和使用不正确配置的二极管连接将不正确连接的插拔板的功率预防
公开(公告)号：US5203004A
公开(公告)日：1993-04-13
申请号：US464817
申请日：1990-01-08
申请人： William P. Bunton , John M. Brown , Patricia L. Whiteside
发明人： William P. Bunton , John M. Brown , Patricia L. Whiteside
IPC分类号： G06F3/00 , G06F13/40 , H05K1/14
CPC分类号： G06F13/409 , H05K1/14 , Y10S439/955 , Y10T307/944
摘要： A computer system with a number of subsystems or modules on separate circuit boards employs electronic keying to ensure proper configuration of these boards. A power key arrangement associated with a plug-in connector enables a separate power supply for each set of boards. A power supply turn-on signal is routed through a uniquely-configured connector path for each board, so the power supply turn-on is inhibited for improper configurations. The uniquely-configured connector path may use either a series or a parallel implementation. The series implementation employs a set of diodes connected for conduction in either of two directions, with the mating connector having its conductor paths connected to match the diode configuration; in this manner, the power supply enable signal can only flow through the series path if the proper board is plugged into a properly-coded slot, in which case the power supply to activate this board is activated through the series path including the diodes. The parallel implementation employs a given number of connector pins to establish the coding for each board, and each pin is either open-circuited or connected to ground; if this coding of the subsystem board is not the same as that of the slot into which it is plugged then the power supply activation signal will be shorted to ground by one or the other of the coded pins.

7. 发明授权

US5751932A Fail-fast, fail-functional, fault-tolerant multiprocessor system 失效
标题翻译：故障快速，故障功能，容错多处理器系统
公开(公告)号：US5751932A
公开(公告)日：1998-05-12
申请号：US485217
申请日：1995-06-07
申请人： Robert W. Horst , William Edward Baker , Randall G. Banton , John Michael Brown , William F. Bruckert , William Patterson Bunton , Gary F. Campbell , John Deane Coddington , Richard W. Cutts, Jr. , Barry Lee Drexler , Harry Frank Elrod , Daniel L. Fowler , David J. Garcia , Paul N. Hintikka , Geoffrey I. Iswandhi , Douglas Eugene Jewett , Curtis Willard Jones, Jr. , James Stevens Klecka , John C. Krause , Stephen G. Low , Susan Stone Meredith , Steven C. Meyers , David P. Sonnier , William Joel Watson , Patricia L. Whiteside , Frank A. Williams , Linda Ellen Zalzala
发明人： Robert W. Horst , William Edward Baker , Randall G. Banton , John Michael Brown , William F. Bruckert , William Patterson Bunton , Gary F. Campbell , John Deane Coddington , Richard W. Cutts, Jr. , Barry Lee Drexler , Harry Frank Elrod , Daniel L. Fowler , David J. Garcia , Paul N. Hintikka , Geoffrey I. Iswandhi , Douglas Eugene Jewett , Curtis Willard Jones, Jr. , James Stevens Klecka , John C. Krause , Stephen G. Low , Susan Stone Meredith , Steven C. Meyers , David P. Sonnier , William Joel Watson , Patricia L. Whiteside , Frank A. Williams , Linda Ellen Zalzala
IPC分类号： G06F11/18 , G01R31/317 , G01R31/3185 , G06F1/12 , G06F9/52 , G06F11/00 , G06F11/10 , G06F11/16 , G06F11/20 , G06F11/273 , G06F12/08 , G06F12/14 , G06F12/16 , G06F13/00 , H04L12/56 , H04L29/14
CPC分类号： G01R31/31727 , G06F1/12 , G06F11/10 , G06F11/1604 , G06F11/1633 , G06F11/1645 , G06F11/165 , G06F11/1658 , G06F11/1679 , G06F11/1687 , G06F12/0815 , G06F12/1483 , H04L47/10 , H04L49/90 , H04L49/901 , H04L49/9057 , H04L69/40 , G01R31/318533 , G06F11/004 , G06F11/1044 , G06F11/167 , G06F11/1683 , G06F11/1695 , G06F11/20 , G06F11/2043 , G06F11/2097 , G06F11/2736 , G06F2201/845 , H04L12/56
摘要： A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. The CPUs are structured to operate in one of two modes: a simplex mode in which the two CPUs operate independently of each other, and a duplex mode in which the CPUs operate in lock-step synchronism to execute each instruction of identical instruction streams at substantially the same time. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.
摘要翻译：多处理器系统包括大量相同构造的多个子处理器系统，每个子处理器系统包括中央处理单元（CPU），以及至少一个I / O设备，其通过也互连子处理器系统的路由设备互连。任何一个子处理器系统的CPU可以通过路由元件与系统的任何I / O设备或系统的任何CPU通信。 CPU被构造为以两种模式之一操作：两个CPU彼此独立地操作的单工模式，以及CPU以锁步同步操作的双工模式，以基本上执行相同指令流的每条指令同一时间。 I / O设备和CPU之间的通信是分组消息。来自I / O设备的中断从I / O设备传送到CPU（或从一个CPU到另一个CPU）作为消息数据包。 CPU和I / O设备可以写入或读取系统的CPU的存储器。存储器保护由每个CPU维护的访问验证方法提供，其中CPU和/或I / O设备被提供有对该CPU的存储器的读/写的验证，没有哪个内存访问被拒绝。

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