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    • 8. 发明授权
    • High-speed interconnection link having automated lane reordering
    • 具有自动车道重新排序的高速互连链路
    • US06961347B1
    • 2005-11-01
    • US09597190
    • 2000-06-20
    • William P. BuntonJohn KrausePatricia L. Whiteside
    • William P. BuntonJohn KrausePatricia L. Whiteside
    • H04J3/16H04L25/14
    • H04L25/14
    • A multi-lane link that automatically detects if the lanes in the link have been reordered and corrects the order of the lanes. In one embodiment, the link includes a transmitter and a receiver. The receiver is configured to receive a plurality of lanes and includes a receiver logic circuit configured to receive signals from each of the plurality of lanes. Lane misordering is corrected during a training sequence in which a first training sequence and a second training sequence are bilaterally transmitted between the transmitter and receiver. The receiver monitors the training sequence for symbols that are unique to each lane and if an unexpected symbol is detected in the lane, the receiver logic circuit will correct the order of the lanes. The link further comprises a transmitter logic circuit configured to transmit signals to the lanes. The transmitter logic circuit is configured to reorder the sequence of the signals transmitted to the lanes if the transmitter does not detect a response from the receiver. The transmitter logic circuit may consist of a bank of multiplexers configured to transmit a selected one of two input signals to be transmitted through a lane. Similarly, the receiver logic circuit may comprises a bank of multiplexers configured to transmit a selected one of two input signals received from a lane. The unique lane identifiers symbols are preferably insensitive to binary inversion and are preferably 10-bit symbols compatible with an 8B/10B encoding scheme.
    • 一个多通道链接,可以自动检测链路中的通道是否重新排序,并纠正通道的顺序。 在一个实施例中,链路包括发射机和接收机。 接收机被配置为接收多个车道,并且包括被配置为从多个车道中的每一条车道接收信号的接收机逻辑电路。 在训练序列期间校正车道排序,其中第一训练序列和第二训练序列在发射机和接收机之间被双向传输。 接收机监视每个通道唯一的符号的训练序列,如果在通道中检测到意外符号,则接收机逻辑电路将校正车道的顺序。 该链路还包括被配置为向车道传输信号的发射机逻辑电路。 发射机逻辑电路被配置为如果发射机未检测到来自接收机的响应,则重新排序发送到车道的信号的序列。 发射机逻辑电路可以由一组多路复用器组成,其被配置为发送要通过车道传输的两个输入信号中的所选择的一个。 类似地,接收器逻辑电路可以包括一组复用器,其被配置为发送从通道接收的两个输入信号中选择的一个。 唯一的车道标识符符号优选地对二进制反转不敏感,并且优选地是与8B / 10B编码方案兼容的10位符号。
    • 10. 发明授权
    • High-speed interconnection adapter having automated lane de-skew
    • 具有自动车道偏斜的高速互连适配器
    • US07197100B2
    • 2007-03-27
    • US10680913
    • 2003-10-08
    • William P. BuntonJohn KrauseScott SmithPatricia L. Whiteside
    • William P. BuntonJohn KrauseScott SmithPatricia L. Whiteside
    • H04L25/00H04L7/00
    • H04L25/14
    • An adapter that buffers received symbols and automatically determines and corrects for skew between lanes is disclosed. In one embodiment, the adapter is a part of a network that includes a first and second devices coupled together by a communications link having multiple independent serial lanes. The first device initiates communication by repeatedly transmitting a training sequence that includes a start symbol for each lane. An adapter in the second device includes a set of buffers each configured to receive the symbols conveyed by a corresponding serial lane. The buffers are coupled to a reconstruction circuit that removes one “symbol group” at a time from the buffers. A symbol group is made up of one symbol from each buffer. The reconstruction circuit removes symbol groups until a start symbol is detected. If the start symbol is not detected in all buffers, output from the buffers having start symbols is temporarily suspended.
    • 公开了缓冲接收到的符号并自动确定和校正车道之间的偏斜的适配器。 在一个实施例中,适配器是网络的一部分,其包括通过具有多个独立串行通道的通信链路耦合在一起的第一和第二设备。 第一设备通过重复发送包括每个车道的起始符号的训练序列来发起通信。 第二设备中的适配器包括一组缓冲器,每个缓冲器被配置为接收由相应串行通道传送的符号。 缓冲器被耦合到重建电路,其从缓冲器一次移除一个“符号组”。 符号组由每个缓冲区中的一个符号组成。 重建电路去除符号组,直到检测到起始符号为止。 如果在所有缓冲区中没有检测到起始符号,则具有起始符号的缓冲区的输出被暂停。