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1. 发明授权

US07605077B2 Dual metal integration scheme based on full silicidation of the gate electrode 失效
标题翻译：基于栅电极完全硅化的双金属集成方案
公开(公告)号：US07605077B2
公开(公告)日：2009-10-20
申请号：US11308486
申请日：2006-03-29
申请人： William K. Henson , Kern Rim , Jack A. Mandelman
发明人： William K. Henson , Kern Rim , Jack A. Mandelman
IPC分类号： H01L21/40 , H01L29/45
CPC分类号： H01L21/823443 , H01L21/82345 , H01L21/823835 , H01L21/823842
摘要： An integration scheme that enables full silicidation (FUSI) of the nFET and pFET gate electrodes at the same time as that of the source/drain regions is provided. The FUSI of the gate electrodes eliminates the gate depletion problem that is observed with polysilicon gate electrodes. In addition, the inventive integration scheme creates different silicon thicknesses of the gate electrode just prior to silicidation. This feature of the present invention allows for fabricating nFETs and pFETs that have a band edge workfunction that is tailored for the specific device region.
摘要翻译：提供了与源极/漏极区域同时实现nFET和pFET栅电极的全硅化（FUSI）的集成方案。栅电极的FUSI消除了多晶硅栅电极观察到的栅耗尽问题。此外，本发明的集成方案刚好在硅化之前产生栅电极的不同硅厚度。本发明的该特征允许制造具有针对特定器件区域定制的带边缘功能函数的nFET和pFET。

2. 发明授权

US07202513B1 Stress engineering using dual pad nitride with selective SOI device architecture 有权
标题翻译：使用双衬垫氮化物的应力工程与选择性SOI器件架构
公开(公告)号：US07202513B1
公开(公告)日：2007-04-10
申请号：US11162953
申请日：2005-09-29
申请人： Dureseti Chidambarrao , William K. Henson , Kern Rim , William C. Wille
发明人： Dureseti Chidambarrao , William K. Henson , Kern Rim , William C. Wille
IPC分类号： H01L31/00
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L29/0653 , H01L29/7842
摘要： A method for engineering stress in the channels of MOS transistors of different conductivity using highly stressed nitride films in combination with selective semiconductor-on-insulator (SOI) device architecture is described. A method of using compressive and tensile nitride films in the shallow trench isolation (STI) process is described. High values of stress are achieved when the method is applied to a selective SOI architecture.
摘要翻译：描述了一种使用高应力氮化物膜与选择性绝缘体上半导体（SOI）器件结构结合的在不同导电性的MOS晶体管的沟道中应力的方法。描述了在浅沟槽隔离（STI）工艺中使用压缩和拉伸氮化物膜的方法。当将该方法应用于选择性SOI结构时，实现高应力值。

3. 发明申请

US20120091506A1 Method and Structure for pFET Junction Profile With SiGe Channel 有权
标题翻译：具有SiGe通道的pFET结型材的方法和结构
公开(公告)号：US20120091506A1
公开(公告)日：2012-04-19
申请号：US12905158
申请日：2010-10-15
申请人： Kern Rim , William K. Henson , Yue Liang , Xinlin Wang
发明人： Kern Rim , William K. Henson , Yue Liang , Xinlin Wang
IPC分类号： H01L29/772 , H01L21/335
CPC分类号： H01L29/1054 , H01L21/26506 , H01L21/26586 , H01L29/1083 , H01L29/6659
摘要： A semiconductor structure including a p-channel field effect transistor (pFET) device located on a surface of a silicon germanium (SiGe) channel is provided in which the junction profile of the source region and the drain region is abrupt. The abrupt source/drain junctions for pFET devices are provided in this disclosure by forming an N- or C-doped Si layer directly beneath a SiGe channel layer which is located above a Si substrate. A structure is thus provided in which the N- or C-doped Si layer (sandwiched between the SiGe channel layer and the Si substrate) has approximately the same diffusion rate for a p-type dopant as the overlying SiGe channel layer. Since the N- or C-doped Si layer and the overlying SiGe channel layer have substantially the same diffusivity for a p-type dopant and because the N- or C-doped Si layer retards diffusion of the p-type dopant into the underlying Si substrate, abrupt source/drain junctions can be formed.
摘要翻译：提供了包括位于硅锗（SiGe）沟道的表面上的p沟道场效应晶体管（pFET）器件的半导体结构，其中源极区和漏极区的结分布是突然的。在本公开内容中，通过在位于Si衬底之上的SiGe沟道层的正下方形成N或C掺杂的Si层来提供用于pFET器件的突发的源极/漏极结。因此，提供了其中N或C掺杂的Si层（夹在SiGe沟道层和Si衬底之间）对于p型掺杂剂具有与覆盖的SiGe沟道层大致相同的扩散速率的结构。由于N或C掺杂的Si层和上覆的SiGe沟道层对于p型掺杂物具有基本上相同的扩散率，并且因为N或C掺杂的Si层阻碍p型掺杂剂扩散到下面的Si 衬底，可以形成突发的源极/漏极结。

4. 发明授权

US07932158B2 Formation of improved SOI substrates using bulk semiconductor wafers 有权
标题翻译：使用块状半导体晶片形成改进的SOI衬底
公开(公告)号：US07932158B2
公开(公告)日：2011-04-26
申请号：US12254197
申请日：2008-10-20
申请人： William K. Henson , Dureseti Chidambarrao , Kern Rim , Hsingjen Wann , Hung Y. Ng
发明人： William K. Henson , Dureseti Chidambarrao , Kern Rim , Hsingjen Wann , Hung Y. Ng
IPC分类号： H01L21/76
CPC分类号： H01L21/764 , H01L21/76283
摘要： The present invention relates to a semiconductor-on-insulator (SOI) substrate having one or more device regions. Each device region comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, while the semiconductor device layer is supported by one or more vertical insulating pillars. The vertical insulating pillars each preferably has a ledge extending between the base semiconductor substrate layer and the semiconductor device layer. The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a “floating” semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap and is supported by one or more vertical insulating pillars. The air gap is preferably formed by selective removal of a sacrificial layer located between the base semiconductor substrate layer and the semiconductor device layer.
摘要翻译：本发明涉及具有一个或多个器件区域的绝缘体上半导体（SOI）衬底。每个器件区域至少包括基底半导体衬底层和其间设置有掩埋绝缘体层的半导体器件层，而半导体器件层由一个或多个垂直绝缘柱支撑。垂直绝缘柱各自优选地具有在基底半导体衬底层和半导体器件层之间延伸的凸缘。本发明的SOI衬底可以容易地由具有“浮动”半导体器件层的前体衬底结构形成，该半导体器件层通过气隙与基底半导体衬底层间隔开并由一个或多个垂直绝缘柱支撑。气隙优选通过选择性地去除位于基底半导体衬底层和半导体器件层之间的牺牲层来形成。

5. 发明授权

US07608489B2 High performance stress-enhance MOSFET and method of manufacture 有权
标题翻译：高性能应力增强型MOSFET及其制造方法
公开(公告)号：US07608489B2
公开(公告)日：2009-10-27
申请号：US11380689
申请日：2006-04-28
申请人： Dureseti Chidambarrao , Ricardo A. Donaton , William K. Henson , Kern Rim
发明人： Dureseti Chidambarrao , Ricardo A. Donaton , William K. Henson , Kern Rim
IPC分类号： H01L21/8232 , H01L21/335
CPC分类号： H01L21/823814 , H01L21/823807 , H01L27/1203 , H01L29/1054 , H01L29/6653 , H01L29/66636 , H01L29/7843 , H01L29/7848 , Y10S438/938
摘要： The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with a stress inducing material embedded in both gates and also in the source/drain region of the PFET and varying thickness of the PFET and NFET channel. In one embodiment, the structure enhances the device performance by varying the thickness of the top Silicon layer respective to the NFET or the PFET.
摘要翻译：本发明涉及半导体结构和制造方法，更具体地说涉及一种CMOS器件，其具有嵌入在PFET的栅极和源极/漏极区域中以及PFET和NFET沟道的变化厚度的应力诱导材料。在一个实施例中，该结构通过改变相应于NFET或PFET的顶部硅层的厚度来增强器件性能。

6. 发明授权

US08268698B2 Formation of improved SOI substrates using bulk semiconductor wafers 有权
标题翻译：使用块状半导体晶片形成改进的SOI衬底
公开(公告)号：US08268698B2
公开(公告)日：2012-09-18
申请号：US13037608
申请日：2011-03-01
申请人： William K. Henson , Dureseti Chidambarrao , Kern Rim , Hsingjen Wann , Hung Y. Ng
发明人： William K. Henson , Dureseti Chidambarrao , Kern Rim , Hsingjen Wann , Hung Y. Ng
IPC分类号： H01L21/76
CPC分类号： H01L21/764 , H01L21/76283
摘要： The present invention relates to a semiconductor-on-insulator (SOI) substrate having one or more device regions. Each device region comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, while the semiconductor device layer is supported by one or more vertical insulating pillars. The vertical insulating pillars each preferably has a ledge extending between the base semiconductor substrate layer and the semiconductor device layer. The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a “floating” semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap and is supported by one or more vertical insulating pillars. The air gap is preferably formed by selective removal of a sacrificial layer located between the base semiconductor substrate layer and the semiconductor device layer.
摘要翻译：本发明涉及具有一个或多个器件区域的绝缘体上半导体（SOI）衬底。每个器件区域至少包括基底半导体衬底层和其间设置有掩埋绝缘体层的半导体器件层，而半导体器件层由一个或多个垂直绝缘柱支撑。垂直绝缘柱各自优选地具有在基底半导体衬底层和半导体器件层之间延伸的凸缘。本发明的SOI衬底可以容易地由具有“浮动”半导体器件层的前体衬底结构形成，半导体器件层通过气隙与基底半导体衬底层间隔开并由一个或多个垂直绝缘柱支撑。气隙优选通过选择性地去除位于基底半导体衬底层和半导体器件层之间的牺牲层来形成。

7. 发明申请

US20100013024A1 HIGH PERFORMANCE STRESS-ENHANCE MOSFET AND METHOD OF MANUFACTURE 有权
标题翻译：高性能应力增强MOSFET及其制造方法
公开(公告)号：US20100013024A1
公开(公告)日：2010-01-21
申请号：US12506770
申请日：2009-07-21
申请人： Dureseti Chidambarrao , Ricardo A. Donaton , William K. Henson , Kern Rim
发明人： Dureseti Chidambarrao , Ricardo A. Donaton , William K. Henson , Kern Rim
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823807 , H01L27/1203 , H01L29/1054 , H01L29/6653 , H01L29/66636 , H01L29/7843 , H01L29/7848 , Y10S438/938
摘要： The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with a stress inducing material embedded in both gates and also in the source/drain region of the PFET and varying thickness of the PFET and NFET channel. In one embodiment, the structure enhances the device performance by varying the thickness of the top Silicon layer respective to the NFET or the PFET.
摘要翻译：本发明涉及半导体结构和制造方法，更具体地说涉及一种CMOS器件，其具有嵌入在PFET的栅极和源极/漏极区域中以及PFET和NFET沟道的变化厚度的应力诱导材料。在一个实施例中，该结构通过改变相应于NFET或PFET的顶部硅层的厚度来增强器件性能。

8. 发明授权

US07297618B1 Fully silicided gate electrodes and method of making the same 失效
标题翻译：全硅化物栅极及其制造方法
公开(公告)号：US07297618B1
公开(公告)日：2007-11-20
申请号：US11460762
申请日：2006-07-28
申请人： William K. Henson , Kern Rim
发明人： William K. Henson , Kern Rim
IPC分类号： H01L21/28
CPC分类号： H01L21/28097 , H01L21/28052 , H01L21/324 , H01L21/823835 , H01L21/823842 , H01L29/4941 , H01L29/4975 , H01L29/517 , H01L29/665
摘要： The present invention relates to a method of selectively fabricating metal gate electrodes in one or more device regions by fully siliciding (FUSI) the gate electrode. The selective formation of FUSI enables metal gate electrodes to be fabricated on devices that are compatible with workfunctions that are different from conventional n+ and p+ doped poly silicon electrodes. Each device region consists of at least one Field Effect Transistor (FET) device which consists of either a polysilicon gate electrode or a fully silicided (FUSI) gate electrode. A gate electrode comprised of silicon and a Ge containing layer is used in combination with a selective removal process of the Ge containing layer. The Ge containing layer is not removed on devices with threshold voltages that are not compatible with the FUSI workfunction. Devices that are compatible with the FUSI workfunction have the Ge containing layer removed prior to the junction silicidation step. The remaining thin silicon layer of the gate electrode becomes fully silicided during the same step as the junction silicidation step.
摘要翻译：本发明涉及一种通过完全硅化（FUSI）栅极选择性地在一个或多个器件区域中制造金属栅电极的方法。 FUSI的选择性形成使得能够在与常规n +和p +掺杂多晶硅电极不同的工作功能兼容的器件上制造金属栅电极。每个器件区域由至少一个场效应晶体管（FET）器件组成，其由多晶硅栅电极或完全硅化（FUSI）栅电极组成。与含锗层的选择性去除方法结合使用由硅和含Ge层组成的栅电极。在与FUSI功能不兼容的阈值电压的器件上，Ge含量层不被去除。与FUSI功能功能兼容的器件在接合硅化步骤之前已除去Ge含量层。在与连接硅化步骤相同的步骤中，栅电极的剩余薄硅层变得完全硅化。

9. 发明授权

US07791144B2 High performance stress-enhance MOSFET and method of manufacture 有权
标题翻译：高性能应力增强型MOSFET及其制造方法
公开(公告)号：US07791144B2
公开(公告)日：2010-09-07
申请号：US12506770
申请日：2009-07-21
申请人： Dureseti Chidambarrao , Ricardo A. Donaton , William K. Henson , Kern Rim
发明人： Dureseti Chidambarrao , Ricardo A. Donaton , William K. Henson , Kern Rim
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/823814 , H01L21/823807 , H01L27/1203 , H01L29/1054 , H01L29/6653 , H01L29/66636 , H01L29/7843 , H01L29/7848 , Y10S438/938
摘要： The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with a stress inducing material embedded in both gates and also in the source/drain of the PFET and varying thickness of the PFET and NFET channel. In one embodiment, the structure enhances the device performance by varying the thickness of the top Silicon layer respective to the NFET or the PFET.
摘要翻译：本发明涉及一种制造半导体结构和方法，更具体地说涉及一种CMOS器件，其具有嵌入在PFET的栅极和源极/漏极中的应力诱导材料以及PFET和NFET沟道的变化的厚度。在一个实施例中，该结构通过改变相应于NFET或PFET的顶部硅层的厚度来增强器件性能。

10. 发明授权

US07550364B2 Stress engineering using dual pad nitride with selective SOI device architecture 失效
标题翻译：使用双衬垫氮化物的应力工程与选择性SOI器件架构
公开(公告)号：US07550364B2
公开(公告)日：2009-06-23
申请号：US11668790
申请日：2007-01-30
申请人： Dureseti Chidambarrao , William K. Henson , Kern Rim , William C. Wille
发明人： Dureseti Chidambarrao , William K. Henson , Kern Rim , William C. Wille
IPC分类号： H01L21/76
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L29/0653 , H01L29/7842
摘要： A method for engineering stress in the channels of MOS transistors of different conductivity using highly stressed nitride films in combination with selective semiconductor-on-insulator (SOI) device architecture is described. A method of using compressive and tensile nitride films in the shallow trench isolation (STI) process is described. High values of stress are achieved when the method is applied to a selective SOI architecture.
摘要翻译：描述了一种使用高应力氮化物膜与选择性绝缘体上半导体（SOI）器件结构结合的在不同导电性的MOS晶体管的沟道中应力的方法。描述了在浅沟槽隔离（STI）工艺中使用压缩和拉伸氮化物膜的方法。当将该方法应用于选择性SOI结构时，实现高应力值。

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