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1. 发明申请

US20080168258A1 Method and Apparatus For Selecting the Architecture Level to Which a Processor Appears to Conform 有权
标题翻译：用于选择处理器符合的架构级别的方法和设备
公开(公告)号：US20080168258A1
公开(公告)日：2008-07-10
申请号：US11621393
申请日：2007-01-09
申请人： William J. Armstrong , Richard L. Arndt , Michael J. Corrigan , Giles R. Frazier , Timothy R. Marchini , Cathy May , Naresh Nayar , John T. O'Quin
发明人： William J. Armstrong , Richard L. Arndt , Michael J. Corrigan , Giles R. Frazier , Timothy R. Marchini , Cathy May , Naresh Nayar , John T. O'Quin
IPC分类号： G06F15/76 , G06F9/30
CPC分类号： G06F9/30101 , G06F9/30181 , G06F9/468
摘要： A method and system for selecting the architecture level to which a processor appears to conform within a computing environment when executing specific logical partitions or programs and performing migration among different levels of processor architecture. The method utilizes a “processor compatibility register” (PCR) that controls the level of the architecture that the processor appears to support. In one embodiment, the PCR is accessible only to super-privileged software. The super-privileged software sets bits in the PCR that specify the architecture level that the processor is to appear to support so that when the program runs on the processor, the processor behaves in accordance with the architecture level for which the program was designed.
摘要翻译：一种用于在执行特定逻辑分区或程序并且在不同级别的处理器架构之间执行迁移时，选择处理器在计算环境内符合的架构级别的方法和系统。该方法利用“处理器兼容性寄存器”（PCR）来控制处理器似乎支持的架构级别。在一个实施方案中，PCR仅可用于超特权软件。超级特权软件设置PCR中的位，指定处理器将要支持的架构级别，以便当程序在处理器上运行时，处理器的行为与程序设计的架构级别相符。

2. 发明授权

US07802252B2 Method and apparatus for selecting the architecture level to which a processor appears to conform 有权
标题翻译：用于选择处理器似乎符合的架构级别的方法和装置
公开(公告)号：US07802252B2
公开(公告)日：2010-09-21
申请号：US11621393
申请日：2007-01-09
申请人： William J. Armstrong , Richard L. Arndt , Michael J. Corrigan , Giles R. Frazier , Timothy R. Marchini , Cathy May , Naresh Nayar , John T. O'Quin, II
发明人： William J. Armstrong , Richard L. Arndt , Michael J. Corrigan , Giles R. Frazier , Timothy R. Marchini , Cathy May , Naresh Nayar , John T. O'Quin, II
IPC分类号： G06F9/46 , G06F9/50
CPC分类号： G06F9/30101 , G06F9/30181 , G06F9/468
摘要： A method and system for selecting the architecture level to which a processor appears to conform within a computing environment when executing specific logical partitions or programs and performing migration among different levels of processor architecture. The method utilizes a “processor compatibility register” (PCR) that controls the level of the architecture that the processor appears to support. In one embodiment, the PCR is accessible only to super-privileged software. The super-privileged software sets bits in the PCR that specify the architecture level that the processor is to appear to support so that when the program runs on the processor, the processor behaves in accordance with the architecture level for which the program was designed.
摘要翻译：一种用于在执行特定逻辑分区或程序并且在不同级别的处理器架构之间执行迁移时，选择处理器在计算环境内符合的架构级别的方法和系统。该方法利用“处理器兼容性寄存器”（PCR）来控制处理器似乎支持的架构级别。在一个实施方案中，PCR仅可用于超特权软件。超级特权软件设置PCR中的位，指定处理器将要支持的架构级别，以便当程序在处理器上运行时，处理器的行为与程序设计的架构级别相符。

3. 发明申请

US20130179886A1 PROVIDING LOGICAL PARTIONS WITH HARDWARE-THREAD SPECIFIC INFORMATION REFLECTIVE OF EXCLUSIVE USE OF A PROCESSOR CORE 审中-公开
标题翻译：提供具有硬件特征信息的逻辑分段反映处理器核心的独家使用
公开(公告)号：US20130179886A1
公开(公告)日：2013-07-11
申请号：US13452745
申请日：2012-04-20
申请人： Giles R. Frazier , Bruce Mealy , Naresh Nayar
发明人： Giles R. Frazier , Bruce Mealy , Naresh Nayar
IPC分类号： G06F9/46
CPC分类号： G06F21/6218 , G06F9/3012 , G06F9/3851 , G06F9/45541 , G06F9/45558 , G06F2009/45587
摘要： Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread-specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.
摘要翻译：用于模拟在多个逻辑分区（LPAR）中独占使用处理器核心的技术包括提供响应于LPAR的访问请求的硬件线程依赖状态信息，所述LPAR反映了LPAR访问硬件线程相关的独占使用处理器信息。如果请求者是在低于管理程序权限级别的特权级别下执行的程序，则转换响应于访问请求而返回的信息，使得每个逻辑分区将处理器视为处理器的独占使用。这些技术可以由处理器核心内的逻辑电路块来实现，其将硬件线程特定信息转换为硬件线程特定信息的逻辑表示，或者可以通过将访问陷阱的中断处理程序的程序指令执行物理寄存器包含信息。

4. 发明申请

US20130086581A1 PRIVILEGE LEVEL AWARE PROCESSOR HARDWARE RESOURCE MANAGEMENT FACILITY 有权
标题翻译：特权级注意处理器硬件资源管理设施
公开(公告)号：US20130086581A1
公开(公告)日：2013-04-04
申请号：US13251879
申请日：2011-10-03
申请人： Giles R. Frazier , Michael K. Gschwind , Naresh Nayar
发明人： Giles R. Frazier , Michael K. Gschwind , Naresh Nayar
IPC分类号： G06F9/455
CPC分类号： G06F9/45533 , G06F9/45558 , G06F9/462 , G06F9/5077 , G06F2009/45579
摘要： Multiple machine state registers are included in a processor core to permit distinction between use of hardware facilities by applications, supervisory threads and the hypervisor. All facilities are initially disabled by the hypervisor when a partition is initialized. When any access is made to a disabled facility, the hypervisor receives an indication of which facility was accessed and sets a corresponding hardware flag in the hypervisor's machine state register. When an application attempts to access a disabled facility, the supervisor managing the operating system image receives an indication of which facility was accessed and sets a corresponding hardware flag in the supervisor's machine state register. The multiple register implementation permits the supervisor to determine whether particular hardware facilities need to have their state saved when an application context swap occurs and the hypervisor can determine which hardware facilities need to have their state saved when a partition swap occurs.
摘要翻译：多个机器状态寄存器被包括在处理器核心中，以便区分应用程序，监督线程和管理程序之间的硬件设施的使用。当初始化分区时，所有的设备最初被管理程序禁用。当对残疾设施进行访问时，管理程序将收到访问哪个设施的指示，并在管理程序的机器状态寄存器中设置相应的硬件标志。当应用程序尝试访问禁用的设备时，管理操作系统映像的主管接收到哪个设备被访问的指示，并在主管机器状态寄存器中设置相应的硬件标志。多寄存器实现允许主管当发生应用程序上下文交换时确定特定硬件设施是否需要保存其状态，并且管理程序可以确定在发生分区交换时哪些硬件设施需要保存其状态。

5. 发明申请

US20130179892A1 PROVIDING LOGICAL PARTIONS WITH HARDWARE-THREAD SPECIFIC INFORMATION REFLECTIVE OF EXCLUSIVE USE OF A PROCESSOR CORE 有权
公开(公告)号：US20130179892A1
公开(公告)日：2013-07-11
申请号：US13345002
申请日：2012-01-06
申请人： Giles R. Frazier , Bruce Mealy , Naresh Nayar
发明人： Giles R. Frazier , Bruce Mealy , Naresh Nayar
IPC分类号： G06F9/46 , G06F13/24
CPC分类号： G06F21/6218 , G06F9/3012 , G06F9/3851 , G06F9/45541 , G06F9/45558 , G06F2009/45587
摘要： Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread-specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.

6. 发明授权

US09069598B2 Providing logical partions with hardware-thread specific information reflective of exclusive use of a processor core 有权
标题翻译：提供逻辑分支与反映独家使用处理器核心的硬件线程特定信息
公开(公告)号：US09069598B2
公开(公告)日：2015-06-30
申请号：US13345002
申请日：2012-01-06
申请人： Giles R. Frazier , Bruce Mealy , Naresh Nayar
发明人： Giles R. Frazier , Bruce Mealy , Naresh Nayar
IPC分类号： G06F9/455 , G06F9/38
CPC分类号： G06F21/6218 , G06F9/3012 , G06F9/3851 , G06F9/45541 , G06F9/45558 , G06F2009/45587
摘要： Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread-specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.
摘要翻译：用于模拟在多个逻辑分区（LPAR）中独占使用处理器核心的技术包括提供响应于LPAR的访问请求的硬件线程依赖状态信息，所述LPAR反映了LPAR访问硬件线程相关的独占使用处理器信息。如果请求者是在低于管理程序权限级别的特权级别下执行的程序，则转换响应于访问请求而返回的信息，使得每个逻辑分区将处理器视为处理器的独占使用。这些技术可以由处理器核心内的逻辑电路块来实现，其将硬件线程特定信息转换为硬件线程特定信息的逻辑表示，或者可以通过将访问陷阱的中断处理程序的程序指令执行物理寄存器包含信息。

7. 发明授权

US08990816B2 Providing logical partions with hardware-thread specific information reflective of exclusive use of a processor core 有权
公开(公告)号：US08990816B2
公开(公告)日：2015-03-24
申请号：US13452745
申请日：2012-04-20
申请人： Giles R. Frazier , Bruce Mealy , Naresh Nayar
发明人： Giles R. Frazier , Bruce Mealy , Naresh Nayar
IPC分类号： G06F9/52 , G06F9/455 , G06F9/38
CPC分类号： G06F21/6218 , G06F9/3012 , G06F9/3851 , G06F9/45541 , G06F9/45558 , G06F2009/45587
摘要： Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread-specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.

8. 发明授权

US08695010B2 Privilege level aware processor hardware resource management facility 有权
标题翻译：特权级别的处理器硬件资源管理工具
公开(公告)号：US08695010B2
公开(公告)日：2014-04-08
申请号：US13251879
申请日：2011-10-03
申请人： Giles R. Frazier , Michael K. Gschwind , Naresh Nayar
发明人： Giles R. Frazier , Michael K. Gschwind , Naresh Nayar
IPC分类号： G06F9/46
CPC分类号： G06F9/45533 , G06F9/45558 , G06F9/462 , G06F9/5077 , G06F2009/45579
摘要： Multiple machine state registers are included in a processor core to permit distinction between use of hardware facilities by applications, supervisory threads and the hypervisor. All facilities are initially disabled by the hypervisor when a partition is initialized. When any access is made to a disabled facility, the hypervisor receives an indication of which facility was accessed and sets a corresponding hardware flag in the hypervisor's machine state register. When an application attempts to access a disabled facility, the supervisor managing the operating system image receives an indication of which facility was accessed and sets a corresponding hardware flag in the supervisor's machine state register. The multiple register implementation permits the supervisor to determine whether particular hardware facilities need to have their state saved when an application context swap occurs and the hypervisor can determine which hardware facilities need to have their state saved when a partition swap occurs.
摘要翻译：多个机器状态寄存器被包括在处理器核心中，以便区分应用程序，监督线程和管理程序之间的硬件设施的使用。当初始化分区时，所有的设备最初被管理程序禁用。当对残疾设施进行访问时，管理程序将收到访问哪个设施的指示，并在管理程序的机器状态寄存器中设置相应的硬件标志。当应用程序尝试访问禁用的设备时，管理操作系统映像的主管接收到哪个设备被访问的指示，并在主管机器状态寄存器中设置相应的硬件标志。多寄存器实现允许主管当发生应用程序上下文交换时确定特定硬件设施是否需要保存其状态，并且管理程序可以确定在发生分区交换时哪些硬件设施需要保存其状态。

9. 发明授权

US08615644B2 Processor with hardware thread control logic indicating disable status when instructions accessing shared resources are completed for safe shared resource condition 有权
标题翻译：具有硬件线程控制逻辑的处理器，指示访问共享资源的指令在安全共享资源状态完成时指示禁用状态
公开(公告)号：US08615644B2
公开(公告)日：2013-12-24
申请号：US12708791
申请日：2010-02-19
申请人： Becky Bruce , Giles R. Frazier , Bradly G. Frey , Kumar K. Gala , Cathy May , Michael D. Snyder , Gary Whisenhunt , James Xenidis
发明人： Becky Bruce , Giles R. Frazier , Bradly G. Frey , Kumar K. Gala , Cathy May , Michael D. Snyder , Gary Whisenhunt , James Xenidis
IPC分类号： G06F9/38
CPC分类号： G06F9/30101 , G06F9/30123 , G06F9/3851 , G06F9/3857
摘要： A technique for indicating a safe shared resource condition with respect to a disabled thread provides a mechanism for providing a fast indication to other hardware threads that a temporarily disabled thread can no longer impact shared resources, such as shared special-purpose registers and translation look-aside buffers within the processor core. Signals from pipelines within the core indicates whether any of the instructions pending in the pipeline impact the shared resources and if not, then the thread disable status is presented to the other threads via a state change in a thread status register. Upon receiving an indication that a particular hardware thread is to be disabled, control logic halts the dispatch of instructions for the particular hardware thread, and then waits until any indication that a shared resource is impacted by an instruction has cleared. Then the control logic updates the thread status to indicate the thread is disabled.
摘要翻译：用于指示关于被禁用线程的安全共享资源状况的技术提供了一种用于向其他硬件线程提供快速指示的机制，临时禁用的线程不再影响共享资源，例如共享专用寄存器和翻译查找，处理器核心内的缓冲区。来自核心内的流水线的信号表示流水线中的任何待执行的任何指示是否影响共享资源，如果没有，则通过线程状态寄存器中的状态更改将线程禁用状态呈现给其他线程。在接收到特定硬件线程被禁用的指示时，控制逻辑停止对特定硬件线程的指令的分派，然后等待直到由指令影响共享资源的任何指示已经被清除。然后控制逻辑更新线程状态以指示线程被禁用。

10. 发明申请

US20120185678A1 HARDWARE THREAD DISABLE WITH STATUS INDICATING SAFE SHARED RESOURCE CONDITION 有权
标题翻译：硬件螺纹与状态指示安全共享资源条件
公开(公告)号：US20120185678A1
公开(公告)日：2012-07-19
申请号：US13435123
申请日：2012-03-30
申请人： Becky Bruce , Giles R. Frazier , Bradly G. Frey , Kumar K. Gala , Cathy May , Michael D. Snyder , Gary Whisenhunt , James Xenidis
发明人： Becky Bruce , Giles R. Frazier , Bradly G. Frey , Kumar K. Gala , Cathy May , Michael D. Snyder , Gary Whisenhunt , James Xenidis
IPC分类号： G06F9/38
CPC分类号： G06F9/30101 , G06F9/30123 , G06F9/3851 , G06F9/3857 , G06F9/3889
摘要： A technique for indicating a safe shared resource condition with respect to a disabled thread provides a mechanism for providing a fast indication to other hardware threads that a temporarily disabled thread can no longer impact shared resources, such as shared special-purpose registers and translation look-aside buffers within the processor core. Signals from pipelines within the core indicates whether any of the instructions pending in the pipeline impact the shared resources and if not, then the thread disable status is presented to the other threads via a state change in a thread status register. Upon receiving an indication that a particular hardware thread is to be disabled, control logic halts the dispatch of instructions for the particular hardware thread, and then waits until any indication that a shared resource is impacted by an instruction has cleared. Then the control logic updates the thread status to indicate the thread is disabled.
摘要翻译：用于指示关于被禁用线程的安全共享资源状况的技术提供了一种用于向其他硬件线程提供快速指示的机制，临时禁用的线程不再影响共享资源，例如共享专用寄存器和翻译查找，处理器核心内的缓冲区。来自核心内的流水线的信号表示流水线中的任何待执行的任何指示是否影响共享资源，如果没有，则通过线程状态寄存器中的状态更改将线程禁用状态呈现给其他线程。在接收到特定硬件线程被禁用的指示时，控制逻辑停止对特定硬件线程的指令的分派，然后等待直到由指令影响共享资源的任何指示已经被清除。然后控制逻辑更新线程状态以指示线程被禁用。

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