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1. 发明授权

US09489207B2 Processor and method for partially flushing a dispatched instruction group including a mispredicted branch 有权
标题翻译：用于部分刷新分派指令组的处理器和方法，包括错误预测的分支
公开(公告)号：US09489207B2
公开(公告)日：2016-11-08
申请号：US12423495
申请日：2009-04-14
申请人： William E. Burky , Brian R. Mestan , Dung Q. Nguyen , Balaram Sinharoy , Benjamin W. Stolt
发明人： William E. Burky , Brian R. Mestan , Dung Q. Nguyen , Balaram Sinharoy , Benjamin W. Stolt
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3861 , G06F9/3842 , G06F9/3851 , G06F9/3855 , G06F9/3857
摘要： Mechanisms are provided for partial flush handling with multiple branches per instruction group. The instruction fetch unit sorts instructions into groups. A group may include a floating branch instruction and a boundary branch instruction. For each group of instructions, the instruction sequencing unit creates an entry in a global completion table (GCT), which may also be referred to herein as a group completion table. The instruction sequencing unit uses the GCT to manage completion of instructions within each outstanding group. Because each group may include up to two branches, the instruction sequencing unit may dispatch instructions beyond the first branch, i.e. the floating branch. Therefore, if the floating branch results in a misprediction, the processor performs a partial flush of that group, as well as a flush of every group younger than that group.
摘要翻译：提供了用于部分刷新处理的机制，每个指令组具有多个分支。指令提取单元将指令分组分组。组可以包括浮动分支指令和边界分支指令。对于每组指令，指令排序单元在全局完成表（GCT）中创建条目，其也可以在此被称为组完成表。指令排序单元使用GCT来管理每个优秀组内的指令完成。因为每个组可以包括多达两个分支，所以指令排序单元可以分派指令超出第一分支，即浮动分支。因此，如果浮动分支导致错误预测，则处理器将对该组进行部分刷新，以及每个小于该组的组的刷新。

2. 发明申请

US20100262807A1 Partial Flush Handling with Multiple Branches Per Group 有权
标题翻译：部分冲洗处理与每个分支
公开(公告)号：US20100262807A1
公开(公告)日：2010-10-14
申请号：US12423495
申请日：2009-04-14
申请人： William E. Burky , Brian R. Mestan , Dung Q. Nguyen , Balaram Sinharoy , Benjamin W. Stolt
发明人： William E. Burky , Brian R. Mestan , Dung Q. Nguyen , Balaram Sinharoy , Benjamin W. Stolt
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3861 , G06F9/3842 , G06F9/3851 , G06F9/3855 , G06F9/3857
摘要： Mechanisms are provided for partial flush handling with multiple branches per instruction group. The instruction fetch unit sorts instructions into groups. A group may include a floating branch instruction and a boundary branch instruction. For each group of instructions, the instruction sequencing unit creates an entry in a global completion table (GCT), which may also be referred to herein as a group completion table. The instruction sequencing unit uses the GCT to manage completion of instructions within each outstanding group. Because each group may include up to two branches, the instruction sequencing unit may dispatch instructions beyond the first branch, i.e. the floating branch. Therefore, if the floating branch results in a misprediction, the processor performs a partial flush of that group, as well as a flush of every group younger than that group.
摘要翻译：提供了用于部分刷新处理的机制，每个指令组具有多个分支。指令提取单元将指令分组分组。组可以包括浮动分支指令和边界分支指令。对于每组指令，指令排序单元在全局完成表（GCT）中创建条目，其也可以在此被称为组完成表。指令排序单元使用GCT来管理每个优秀组内的指令完成。因为每个组可以包括多达两个分支，所以指令排序单元可以分派指令超出第一分支，即浮动分支。因此，如果浮动分支导致错误预测，则处理器将对该组进行部分刷新，以及每个小于该组的组的刷新。

3. 发明授权

US08131976B2 Tracking effective addresses in an out-of-order processor 有权
标题翻译：跟踪无序处理器中的有效地址
公开(公告)号：US08131976B2
公开(公告)日：2012-03-06
申请号：US12422595
申请日：2009-04-13
申请人： Richard W. Doing , Susan E. Eisen , David S. Levitan , Kevin N. Magill , Brian R. Mestan , Balaram Sinharoy , Benjamin W. Stolt , Jeffrey R. Summers , Albert J. Van Norstrand, Jr.
发明人： Richard W. Doing , Susan E. Eisen , David S. Levitan , Kevin N. Magill , Brian R. Mestan , Balaram Sinharoy , Benjamin W. Stolt , Jeffrey R. Summers , Albert J. Van Norstrand, Jr.
IPC分类号： G06F9/30 , G06F9/40 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/26 , G06F9/34
CPC分类号： G06F9/3802 , G06F9/322 , G06F9/3806 , G06F9/3853 , G06F9/3855 , G06F9/3861
摘要： Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag.
摘要翻译：在数据处理系统中提供用于通过数据处理系统的处理器流水线跟踪有效地址的机制。这些机制包括用于从指令高速缓存取出指令的逻辑，并通过数据处理系统中的有效地址表逻辑将有效地址表（EAT）数据结构中的条目与获取的指令相关联。所述机制还包括用于将有效地址标签（eatag）与所述获取的指令相关联的逻辑，所述标签包括指向所述EAT中的条目的基本食品，以及食品标签偏移量。此外，这些机制包括通过处理eatag来处理通过处理器管线的指令的逻辑。

4. 发明申请

US20100262806A1 Tracking Effective Addresses in an Out-of-Order Processor 有权
标题翻译：跟踪无序处理器中的有效地址
公开(公告)号：US20100262806A1
公开(公告)日：2010-10-14
申请号：US12422595
申请日：2009-04-13
申请人： Richard W. Doing , Susan E. Eisen , David S. Levitan , Kevin N. Magill , Brian R. Mestan , Balaram Sinharoy , Benjamin W. Stolt , Jeffrey R. Summers , Albert J. Van Norstrand, JR.
发明人： Richard W. Doing , Susan E. Eisen , David S. Levitan , Kevin N. Magill , Brian R. Mestan , Balaram Sinharoy , Benjamin W. Stolt , Jeffrey R. Summers , Albert J. Van Norstrand, JR.
IPC分类号： G06F9/30
CPC分类号： G06F9/3802 , G06F9/322 , G06F9/3806 , G06F9/3853 , G06F9/3855 , G06F9/3861
摘要： Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag.
摘要翻译：在数据处理系统中提供用于通过数据处理系统的处理器流水线跟踪有效地址的机制。这些机制包括用于从指令高速缓存取出指令的逻辑，并通过数据处理系统中的有效地址表逻辑将有效地址表（EAT）数据结构中的条目与获取的指令相关联。所述机制还包括用于将有效地址标签（eatag）与所述获取的指令相关联的逻辑，所述标签包括指向所述EAT中的条目的基本食品，以及食品标签偏移量。此外，这些机制包括通过处理eatag来处理通过处理器管线的指令的逻辑。

5. 发明申请

US20090063819A1 Method and Apparatus for Dynamically Managing Instruction Buffer Depths for Non-Predicted Branches 失效
标题翻译：用于动态管理非预测分支的指令缓冲区深度的方法和装置
公开(公告)号：US20090063819A1
公开(公告)日：2009-03-05
申请号：US11845838
申请日：2007-08-28
申请人： Richard W. Doing , Michael O. Klett , Kevin N. Magill , Brian R. Mestan , David Mui , Balaram Sinharoy , Jeffrey R. Summers
发明人： Richard W. Doing , Michael O. Klett , Kevin N. Magill , Brian R. Mestan , David Mui , Balaram Sinharoy , Jeffrey R. Summers
IPC分类号： G06F9/312 , G06F9/38
CPC分类号： G06F9/3804
摘要： A method and apparatus for dynamically managing instruction buffer depths for non-predicted branches reduces wasted energy and resources associated with low confidence branch prediction conditions. A portion of the instruction buffer for a instruction thread is allocated for storing predicted branch instruction streams and another portion, which may be zero-sized during high prediction confidence conditions, is allocated to the non-predicted branch instruction stream. The size of the buffers is adjusted dynamically in conformity with an on-going prediction confidence that provides a measure of how well branch prediction mechanisms are working for a given instruction thread. An alternate instruction fetch address table can be maintained and multiplexed with the main fetch address register for addressing the instruction cache, so that the instruction stream can be quickly shifted to the non-predicted path when a branch instruction is resolved to the non-predicted path.
摘要翻译：用于动态管理非预测分支的指令缓冲器深度的方法和装置减少与低置信度分支预测条件相关联的浪费的能量和资源。分配用于指令线程的指令缓冲器的一部分用于存储预测的分支指令流，并且在高预测置信度条件下可以为零大小的另一部分被分配给非预测分支指令流。缓冲区的大小根据正在进行的预测置信度动态调整，提供了分支预测机制对给定指令线程的工作原理的测量。替代指令提取地址表可以与主提取地址寄存器保持多路复用，用于对指令高速缓存进行寻址，使得当分支指令被解析为非预测路径时，可以将指令流快速移位到非预测路径。

6. 发明申请

US20100262813A1 Detecting and Handling Short Forward Branch Conversion Candidates 审中-公开
标题翻译：检测和处理短期分支转换候选人
公开(公告)号：US20100262813A1
公开(公告)日：2010-10-14
申请号：US12423608
申请日：2009-04-14
申请人： Mary D. Brown , Richard W. Doing , Kevin N. Magill , Brian R. Mestan , Wolfram M. Sauer , Balaram Sinharoy , Jeffrey R. Summers , Albert J. Van Norstrand, JR.
发明人： Mary D. Brown , Richard W. Doing , Kevin N. Magill , Brian R. Mestan , Wolfram M. Sauer , Balaram Sinharoy , Jeffrey R. Summers , Albert J. Van Norstrand, JR.
IPC分类号： G06F9/38
CPC分类号： G06F9/30003 , G06F8/433 , G06F9/30058 , G06F9/30072 , G06F9/3017 , G06F9/30174 , G06F9/3844 , G06F9/3846 , G06F9/3855
摘要： Mechanisms, in a processor, are provided for detecting and handling short forward branch conversion candidates. The mechanisms identify a conditional branch in the computer code and determine if the short forward conditional branch is to be converted to a non-branching conditional sequence of instructions. Moreover, the mechanisms convert the conditional branch to a non-branching conditional sequence of instructions comprising a resolve instruction and one or more conditional instructions dependent on the resolve instruction. In addition, the mechanisms execute the non-branching conditional sequence of instructions in place of the conditional branch in the computer code and generate an output of the computer code based on the execution of the non-branching conditional sequence of instructions.
摘要翻译：在处理器中提供用于检测和处理短前进分支转换候选的机制。机制识别计算机代码中的条件分支，并确定短向前向条件分支是否要转换为非分支条件指令序列。此外，机制将条件分支转换为包括解决指令和取决于解析指令的一个或多个条件指令的非分支条件指令序列。此外，这些机制代替计算机代码中的条件分支执行非分支条件指令序列，并且基于非分支条件指令序列的执行生成计算机代码的输出。

7. 发明授权

US07779232B2 Method and apparatus for dynamically managing instruction buffer depths for non-predicted branches 失效
标题翻译：用于动态管理非预测分支的指令缓冲区深度的方法和装置
公开(公告)号：US07779232B2
公开(公告)日：2010-08-17
申请号：US11845838
申请日：2007-08-28
申请人： Richard W. Doing , Michael O. Klett , Kevin N. Magill , Brian R. Mestan , David Mui , Balaram Sinharoy , Jeffrey R. Summers
发明人： Richard W. Doing , Michael O. Klett , Kevin N. Magill , Brian R. Mestan , David Mui , Balaram Sinharoy , Jeffrey R. Summers
IPC分类号： G06F9/42 , G06F9/312
CPC分类号： G06F9/3804
摘要： A method and apparatus for dynamically managing instruction buffer depths for non-predicted branches reduces wasted energy and resources associated with low confidence branch prediction conditions. A portion of the instruction buffer for a instruction thread is allocated for storing predicted branch instruction streams and another portion, which may be zero-sized during high prediction confidence conditions, is allocated to the non-predicted branch instruction stream. The size of the buffers is adjusted dynamically in conformity with an on-going prediction confidence that provides a measure of how well branch prediction mechanisms are working for a given instruction thread. An alternate instruction fetch address table can be maintained and multiplexed with the main fetch address register for addressing the instruction cache, so that the instruction stream can be quickly shifted to the non-predicted path when a branch instruction is resolved to the non-predicted path.
摘要翻译：用于动态管理非预测分支的指令缓冲器深度的方法和装置减少与低置信度分支预测条件相关联的浪费的能量和资源。分配用于指令线程的指令缓冲器的一部分用于存储预测的分支指令流，并且在高预测置信度条件下可以为零大小的另一部分被分配给非预测分支指令流。缓冲区的大小根据正在进行的预测置信度动态调整，提供了分支预测机制对给定指令线程的工作原理的测量。替代指令提取地址表可以与主提取地址寄存器保持多路复用，用于对指令高速缓存进行寻址，使得当分支指令被解析为非预测路径时，可以将指令流快速移位到非预测路径。

8. 发明授权

US09342432B2 Hardware performance-monitoring facility usage after context swaps 有权
标题翻译：情景交换后的硬件性能监控设备使用情况
公开(公告)号：US09342432B2
公开(公告)日：2016-05-17
申请号：US13313557
申请日：2011-12-07
申请人： Giles R. Frazier , Brian R. Mestan
发明人： Giles R. Frazier , Brian R. Mestan
IPC分类号： G06F11/34
CPC分类号： G06F11/348 , G06F2201/865
摘要： A performance monitoring technique provides task-switch immune operation without requiring storage and retrieval of the performance monitor state when a task switch occurs and provides accurate performance monitoring information. When a hypervisor signals that a task is being resumed and the application privilege level has been entered, it provides an indication, which starts a delay timer. The delay timer is resettable in case a predetermined time period has not elapsed when the next task switch occurs. After the delay timer expires, analysis of the performance monitor measurements is resumed, which prevents an initial state, a state due to execution of the operating system or hypervisor, or a state remaining from a previous task from corrupting the performance monitoring results. The performance monitor may be or include an execution trace unit that collects branch information in a current program execution trace.
摘要翻译：性能监控技术提供任务切换免疫操作，而不需要在任务切换发生时存储和检索性能监视状态，并提供准确的性能监视信息。当管理程序发出信号指示正在恢复任务并且已经输入了应用程序权限级别时，它提供指示，其启动延迟定时器。在发生下一任务切换的情况下，在没有经过预定时间段的情况下，可以将延迟定时器复位。在延迟定时器到期后，恢复对性能监视器测量的分析，这阻止了初始状态，由于执行操作系统或管理程序的状态，或者从前一任务中剩余的状态破坏性能监视结果。性能监视器可以是或包括在当前程序执行跟踪中收集分支信息的执行跟踪单元。

9. 发明申请

US20120005462A1 Hardware Assist for Optimizing Code During Processing 审中-公开
标题翻译：处理过程中优化代码的硬件辅助
公开(公告)号：US20120005462A1
公开(公告)日：2012-01-05
申请号：US12828697
申请日：2010-07-01
申请人： Ronald P. Hall , Brian R. Konigsburg , David S. Levitan , Brian R. Mestan
发明人： Ronald P. Hall , Brian R. Konigsburg , David S. Levitan , Brian R. Mestan
IPC分类号： G06F9/38
CPC分类号： G06F11/3466 , G06F9/3808 , G06F9/3844 , G06F11/348 , G06F2201/88
摘要： A method, data processing system, and computer program product for obtaining information about instructions. Instructions are processed. In response to processing a branch instruction in the instructions, a determination is made as to whether a result from processing the branch instruction follows a prediction of whether a branch is predicted to occur for the branch instruction. In response to the result following the prediction, the branch instruction is added to a current segment in a trace. In response to an absence of the result following the prediction, the branch instruction is added to the current segment in the trace and a first new segment and a second new segment are created. The first new segment includes a first branch instruction reached in the instructions from following the prediction. The second new segment includes a second branch instruction in the instructions reached from not following the prediction.
摘要翻译：一种用于获取关于指令的信息的方法，数据处理系统和计算机程序产品。处理说明。响应于在指令中处理分支指令，确定来自处理分支指令的结果是否遵循预测分支指令是否为分支指令发生的预测。响应于预测结果，分支指令被添加到跟踪中的当前段。响应于预测之后没有结果，分支指令被添加到跟踪中的当前段，并且创建第一新段和第二新段。第一个新的段包括在跟随预测的指令中达到的第一个分支指令。第二个新的段包括从不遵循预测到达的指令中的第二个分支指令。

10. 发明申请

US20130055033A1 HARDWARE-ASSISTED PROGRAM TRACE COLLECTION WITH SELECTABLE CALL-SIGNATURE CAPTURE 审中-公开
标题翻译：硬件辅助程序跟踪采集与可选择的呼叫签名捕获
公开(公告)号：US20130055033A1
公开(公告)日：2013-02-28
申请号：US13300863
申请日：2011-11-21
申请人： Giles R. Frazier , David S. Levitan , Brian R. Mestan , Mauricio J. Serrano
发明人： Giles R. Frazier , David S. Levitan , Brian R. Mestan , Mauricio J. Serrano
IPC分类号： G06F11/34
CPC分类号： G06F11/3466 , G06F11/348 , G06F11/3636 , G06F2201/83 , G06F2201/865
摘要： Hardware-assisted program tracing is facilitated by a processor that includes a root instruction address register, a program trace signature computation unit and a call signature register. When a program instruction having an address matching the root instruction address register is executed, a program trace signature is captured in the call signature register and capture of branch history is commenced. By accumulating different values of the call signature register, for example in response to an interrupt generated when the root instruction is executed, software that performs program tracing can obtain signatures of all of the multiple execution paths that lead to the root instruction, which is also specified by software in order to set different root instructions for program tracing. In an alternative implementation, a storage for multiple call signatures is provided in the processor and read at once by the software.
摘要翻译：硬件辅助程序跟踪由包括根指令地址寄存器，程序跟踪签名计算单元和呼叫签名寄存器的处理器来促进。当执行具有与根指令地址寄存器匹配的地址的程序指令时，在呼叫签名寄存器中捕获程序跟踪签名，并且开始分支历史记录的捕获。通过累积呼叫签名寄存器的不同值，例如响应于执行根指令时产生的中断，执行程序跟踪的软件可以获得导致根指令的所有多个执行路径的签名，这也是由软件指定，以便为程序跟踪设置不同的根指令。在替代实现中，在处理器中提供用于多个呼叫签名的存储器，并由软件一次读取。

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