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1. 发明授权

US08386747B2 Processor and method for dynamic and selective alteration of address translation 有权
标题翻译：用于动态和选择性地改变地址转换的处理器和方法
公开(公告)号：US08386747B2
公开(公告)日：2013-02-26
申请号：US12483051
申请日：2009-06-11
申请人： William C. Moyer , James B. Eifert
发明人： William C. Moyer , James B. Eifert
IPC分类号： G06F13/00 , G06F13/28 , G06F9/46 , G06F9/00 , G11C8/00
CPC分类号： G06F12/1036 , G06F12/0284 , G06F12/109
摘要： Non-intrusive techniques have been developed to dynamically and selectively alter address translations performed by, or for, a processor. For example, in some embodiments, a memory management unit is configured to map from effective addresses in respective effective (or virtual) address spaces to physical addresses in the memory, wherein the mappings performed by the memory management unit are based on address translation entries of an address translation table. For a subset of less than all processes, entry selection logic selects from amongst plural alternative mappings coded in respective ones of the address translation entries. For at least some effective addresses mapped for a particular process of the subset, selection of a particular address translation entry is based on an externally sourced value. In some embodiments, only a subset of effective addresses mapped for the particular process are subject to dynamic runtime alteration of the address translation entry selection.
摘要翻译：已经开发了非侵入性技术来动态地和选择性地改变由处理器执行的或为处理器执行的地址转换。例如，在一些实施例中，存储器管理单元被配置为将相应的有效（或虚拟）地址空间中的有效地址映射到存储器中的物理地址，其中由存储器管理单元执行的映射基于地址转换条目地址转换表。对于少于所有进程的子集，条目选择逻辑从在各个地址转换条目中编码的多个备选映射中进行选择。对于为子集的特定过程映射的至少一些有效地址，特定地址转换条目的选择基于外部来源的值。在一些实施例中，仅为特定进程映射的有效地址的子集经受地址转换条目选择的动态运行时间更改。

2. 发明申请

US20100318761A1 PROCESSOR AND METHOD FOR DYNAMIC AND SELECTIVE ALTERATION OF ADDRESS TRANSLATION 有权
标题翻译：地址翻译的动态和选择性修改的处理器和方法
公开(公告)号：US20100318761A1
公开(公告)日：2010-12-16
申请号：US12483051
申请日：2009-06-11
申请人： William C. Moyer , James B. Eifert
发明人： William C. Moyer , James B. Eifert
IPC分类号： G06F12/06
CPC分类号： G06F12/1036 , G06F12/0284 , G06F12/109
摘要： Non-intrusive techniques have been developed to dynamically and selectively alter address translations performed by, or for, a processor. For example, in some embodiments, a memory management unit is configured to map from effective addresses in respective effective (or virtual) address spaces to physical addresses in the memory, wherein the mappings performed by the memory management unit are based on address translation entries of an address translation table. For a subset of less than all processes, entry selection logic selects from amongst plural alternative mappings coded in respective ones of the address translation entries. For at least some effective addresses mapped for a particular process of the subset, selection of a particular address translation entry is based on an externally sourced value. In some embodiments, only a subset of effective addresses mapped for the particular process are subject to dynamic runtime alteration of the address translation entry selection.
摘要翻译：已经开发了非侵入性技术来动态地和选择性地改变由处理器执行的或为处理器执行的地址转换。例如，在一些实施例中，存储器管理单元被配置为将相应有效（或虚拟）地址空间中的有效地址映射到存储器中的物理地址，其中由存储器管理单元执行的映射基于地址转换条目地址转换表。对于少于所有进程的子集，条目选择逻辑从在各个地址转换条目中编码的多个备选映射中进行选择。对于为子集的特定过程映射的至少一些有效地址，特定地址转换条目的选择基于外部来源的值。在一些实施例中，仅为特定进程映射的有效地址的子集经受地址转换条目选择的动态运行时间更改。

3. 发明授权

US07809980B2 Error detector in a cache memory using configurable way redundancy 有权
标题翻译：使用可配置方式冗余的缓存中的错误检测器
公开(公告)号：US07809980B2
公开(公告)日：2010-10-05
申请号：US11951924
申请日：2007-12-06
申请人： Jehoda Refaeli , Florian Bogenberger , James B. Eifert
发明人： Jehoda Refaeli , Florian Bogenberger , James B. Eifert
IPC分类号： G06F11/00
CPC分类号： G06F11/1064 , G06F12/0864 , G06F12/126 , G06F2212/601
摘要： A data processing system includes a processor having a multi-way cache which has a first and a second way. The second way is configurable to either be redundant to the first way or to operate as an associative way independent of the first way. The system may further include a memory, where the processor, in response to a read address missing in the cache, provides the read address to the memory. The second way may be dynamically configured to be redundant to the first way during operation of the processor in response to an error detection signal. In one aspect, when the second way is configured to be redundant, in response to the read address hitting in the cache, data addressed by an index portion of the read address is provided from both the first and second way and compared to each other to determine if a comparison error exists.
摘要翻译：数据处理系统包括具有第一和第二方式的多路缓存的处理器。第二种方式是配置为第一种方式是冗余的，或作为独立于第一种方式的关联方式运行。系统还可以包括存储器，其中响应于高速缓存中缺少的读取地址的处理器将读取地址提供给存储器。响应于错误检测信号，在处理器的操作期间，第二种方式可被动态配置为在第一种方式中是冗余的。在一个方面，当第二种方式被配置为冗余时，响应于高速缓存中的读取地址，由读取地址的索引部分寻址的数据从第一和第二方式提供并相互比较确定是否存在比较错误。

4. 发明授权

US06240493B1 Method and apparatus for performing access censorship in a data processing system 失效
标题翻译：用于在数据处理系统中执行访问审查的方法和装置
公开(公告)号：US06240493B1
公开(公告)日：2001-05-29
申请号：US09061974
申请日：1998-04-17
申请人： Wallace B. Hardwood, III , James B. Eifert , Thomas R. Toms
发明人： Wallace B. Hardwood, III , James B. Eifert , Thomas R. Toms
IPC分类号： G06F1214
CPC分类号： G06F21/71 , G06F21/62
摘要： Method and apparatus for performing access censorship in a data processing system (10). In one embodiment, a digital data processing system (10) has a sub-system (34) that can be protected against intrusions, yet is still accessible and/or alterable under certain defined conditions. In a non-volatile storage portion (48) of the data processing system (10), censorship information is stored to enable an access control mechanism. Access control information (42) to selectively disable the access control mechanism is programmably generated. Additional access control information (44) can be employed to reprogram a data processing system (10) containing access protected data in a secure mode.
摘要翻译：用于在数据处理系统（10）中执行访问审查的方法和装置。在一个实施例中，数字数据处理系统（10）具有子系统（34），其可以被保护免受入侵，但是在某些限定的条件下仍可访问和/或可变。在数据处理系统（10）的非易失性存储部分（48）中，存储检查信息以实现访问控制机制。可编程地产生用于选择性地禁用访问控制机制的访问控制信息（42）。可以采用额外的访问控制信息（44）来重新编程包含安全模式的访问保护数据的数据处理系统（10）。

5. 发明授权

US5727172A Method and apparatus for performing atomic accesses in a data processing system 失效
标题翻译：用于在数据处理系统中执行原子访问的方法和装置
公开(公告)号：US5727172A
公开(公告)日：1998-03-10
申请号：US431943
申请日：1995-05-01
申请人： James B. Eifert , Adi Sapir , Wallace B. Harwood, III
发明人： James B. Eifert , Adi Sapir , Wallace B. Harwood, III
IPC分类号： G06F13/36 , G06F13/40 , G06F13/14
CPC分类号： G06F13/4036 , G06F13/36
摘要： A method and apparatus for performing atomic accesses in a data processing system (10). In one embodiment, a small number of control signals (e.g. 100-102; or 103-104; or 105-108 from FIG. 3 ) are used to provide information regarding the status of reservations between bus masters (e.g. 80), bus interfaces (e.g. 84, 86, and 92), and snoop logic (e.g. 82,88, and 90). Snoop logic (e.g. 40 in FIG. 2) is required if multiple bus masters (12 and 46) are used. The control signals allow atomic accesses to be performed in a multi-master data processing system (10), while minimizing the circuitry required to be built on-board each bus master integrated circuit processor (e.g. 152 in FIG. 3). The result is lower cost processors (152) which can operate in multi-processor systems, but which are optimized for use in single-processor systems.
摘要翻译：一种用于在数据处理系统（10）中执行原子访问的方法和装置。在一个实施例中，使用少量控制信号（例如，图10中的100-102;或103-104;或105-108）来提供关于总线主控（例如80），总线接口（例如84,86和92）和窥探逻辑（例如82,88和90）。如果使用多个总线主机（12和46），则需要侦听逻辑（如图2中的40）。控制信号允许在多主数据处理系统（10）中执行原子访问，同时使需要构建在板上的每个总线主集成电路处理器（例如图3中的152）所需的电路最小化。其结果是可以在多处理器系统中运行的成本较低的处理器（152），但是它们被优化用于单处理器系统。

6. 发明授权

US5675749A Method and apparatus for controlling show cycles in a data processing system 失效
标题翻译：用于控制数据处理系统中的显示周期的方法和装置
公开(公告)号：US5675749A
公开(公告)日：1997-10-07
申请号：US460484
申请日：1995-06-02
申请人： Jay A. Hartvigsen , James B. Eifert , Wallace B. Harwood, III , Jeffrey A. Hopkins
发明人： Jay A. Hartvigsen , James B. Eifert , Wallace B. Harwood, III , Jeffrey A. Hopkins
IPC分类号： G06F11/34 , G06F11/36 , G06F9/00
CPC分类号： G06F11/3648 , G06F11/349
摘要： The present invention relates in general to a data processing system (10), and more particularly to a method and apparatus for controlling showcycles in a data processing system (10) to provide user control over the tradeoff between internal bus visibility and operating performance. In one embodiment, the functionality of one or more register control bits (100, 102) can be combined with the functionality of one or more externally provided signals (78) to allow the user to have a wide range of control over the show cycles provided on external bus 12. The user is thus able to continuously select and change which information is provided by way of show cycles on external bus 12. As a result, the difficulty of debugging software program code can potentially be reduced.
摘要翻译：本发明一般涉及一种数据处理系统（10），更具体地涉及一种用于控制数据处理系统（10）中的显示的方法和装置，以提供用户对内部总线可见性和操作性能之间权衡的控制。在一个实施例中，一个或多个寄存器控制位（100,102）的功能可以与一个或多个外部提供的信号（78）的功能组合，以允许用户对所提供的显示循环进行宽范围的控制因此，用户能够连续地选择和改变通过外部总线12上的显示周期来提供哪些信息。结果，可以有可能降低调试软件程序代码的难度。

7. 发明申请

US20110167198A1 NON-VOLATILE STORAGE ALTERATION TRACKING 有权
标题翻译：非易失性存储变换跟踪
公开(公告)号：US20110167198A1
公开(公告)日：2011-07-07
申请号：US12683549
申请日：2010-01-07
申请人： Richard Soja , James B. Eifert , Timothy J. Strauss
发明人： Richard Soja , James B. Eifert , Timothy J. Strauss
IPC分类号： G06F12/02
CPC分类号： G06F12/1425
摘要： A method for tracking alteration of a non-volatile storage includes receiving a request to modify a tracked region of the non-volatile storage. In response to the request, it is determined whether or not a modification of data stored in a non-erasable one-time programmable (NEOTP) alteration log region has occurred. In response to determining that the modification of the data stored in the NEOTP alteration log region has occurred, the tracked region of non-volatile storage is modified in response to the request. In response to determining that the modification of the data stored in the NEOTP alteration log region has not occurred, the request to modify the tracked region of the non-volatile memory is denied.
摘要翻译：用于跟踪非易失性存储器的改变的方法包括接收修改非易失性存储器的被跟踪区域的请求。响应于该请求，确定是否发生存储在不可擦除的一次性可编程（NEOTP）改变对数区域中的数据的修改。响应于确定存储在NEOTP改变日志区域中的数据的修改已经发生，响应于该请求来修改非易失性存储的跟踪区域。响应于确定没有发生存储在NEOTP改变日志区域中的数据的修改，修改非易失性存储器的跟踪区域的请求被拒绝。

8. 发明授权

US6079015A Data processing system having selectable exception table relocation and method therefor 失效
标题翻译：具有可选异常表重定位的数据处理系统及其方法
公开(公告)号：US6079015A
公开(公告)日：2000-06-20
申请号：US62952
申请日：1998-04-20
申请人： Wallace B. Harwood, III , James B. Eifert , Rami Natan , Yossi Asher , Avi Ginsberg
发明人： Wallace B. Harwood, III , James B. Eifert , Rami Natan , Yossi Asher , Avi Ginsberg
IPC分类号： G06F9/48 , G06F12/02
CPC分类号： G06F9/4812 , G06F9/3861
摘要： A data processing system (20) has a central processing unit (CPU) (22) and a memory (30) for storing an exception table. The exception table is mapped in the memory (30) in consecutive segments, with each segment for storing a predetermined number of instructions for executing the exception. By asserting a control bit, the exception table can be relocated, or remapped, and compressed into a jump table. The jump table stores only jump instruction for branching to the exception routines, which are relocated to other memory locations. The jump table is generated from the starting addresses of the exception routines. Relocating the exception routines allows for more efficient use of internal memory space of the data processing system (20).
摘要翻译：数据处理系统（20）具有中央处理单元（CPU）（22）和用于存储异常表的存储器（30）。异常表以连续的段映射到存储器（30）中，每个段用于存储用于执行异常的预定数量的指令。通过断言控制位，异常表可以重新定位或重新映射，并被压缩成跳转表。跳转表仅存储用于分支到异常例程的跳转指令，这些例程被重新定位到其他内存位置。跳转表是从异常例程的起始地址生成的。重新定位异常例程允许更有效地使用数据处理系统（20）的内部存储器空间。

9. 发明授权

US5717931A Method and apparatus for communicating between master and slave electronic devices where the slave device may be hazardous 失效
标题翻译：主从电子设备之间进行通信的方法和装置，其中从设备可能是危险的
公开(公告)号：US5717931A
公开(公告)日：1998-02-10
申请号：US359969
申请日：1994-12-20
申请人： Adi Sapir , Ilan Pardo , James B. Eifert , Wallace B. Harwood, III , John J. Vaglica , Danny Shterman
发明人： Adi Sapir , Ilan Pardo , James B. Eifert , Wallace B. Harwood, III , John J. Vaglica , Danny Shterman
IPC分类号： G06F9/38 , G06F11/28 , G06F13/16 , G06F9/40
CPC分类号： G06F13/1605
摘要： A master device (11) can access slave devices (12) either speculatively or non-speculatively. The slave devices (12) can be either non-hazardous devices or hazardous devices which exhibit status changes on reading. The master device (11) issues an access request including information as to whether the request is speculative or non-speculative, the slave device (12) then responds to the master device (11) with a negative acknowledgment that access is denied if the access request is speculative and the slave device (12) is hazardous. Otherwise, if the slave device (12) can deal with the request, a positive acknowledgment is sent. If the master device (11) receives a negative acknowledgment, it continues to reissue updated access requests until a positive acknowledgment is received.
摘要翻译：主设备（11）可以以推测或非推测方式访问从设备（12）。从设备（12）可以是非危险设备或在读取时显示状态变化的危险设备。主设备（11）发布包括关于请求是否是推测性的信息的访问请求，从设备（12）随后以否定确认来响应主设备（11），如果访问被拒绝则访问被拒绝请求是推测性的，从设备（12）是危险的。否则，如果从设备（12）可以处理请求，则发送肯定确认。如果主设备（11）接收到否定确认，则继续重新发送更新的接入请求，直到收到肯定确认。

10. 发明授权

US5699516A Method and apparatus for implementing a in-order termination bus protocol within a data processing system 失效
标题翻译：用于在数据处理系统内实现按顺序终端总线协议的方法和装置
公开(公告)号：US5699516A
公开(公告)日：1997-12-16
申请号：US363435
申请日：1994-12-22
申请人： Adi Sapir , James B. Eifert
发明人： Adi Sapir , James B. Eifert
IPC分类号： G06F13/36
CPC分类号： G06F13/36
摘要： A bus protocol is provided for pipelined and/or split transaction buses (18,48) which have in-order data bus termination and which do not require data bus arbitration. The present invention solves the problem of matching the initial address request by a bus master (12, 13, 42) to the corresponding data response from a bus slave (14, 15, 44) when the bus (18, 48) used for master-slave communication is a split-transaction bus and/or a pipelined bus. Each bus master (12, 13, 42) and each bus slave (14, 15, 44) has a counter (30-33, 75-76) which is used to store a current pipe depth value (21, 51) from a central pipe counter (16, 72). A transaction start signal (20, 50) and a transaction end signal (22, 52) are used to selectively increment and decrement the counters (30-33, 75-76).
摘要翻译：为流水线和/或分离事务总线（18,48）提供总线协议，这些总线协议具有按顺序数据总线终止并且不需要数据总线仲裁。本发明解决了当用于主机的总线（18,48）时，总线主机（12,13,42）将初始地址请求与来自总线从机（14,15,44）的相应数据响应匹配的问题 -slave通信是分组交易总线和/或流水线总线。每个总线主控器（12,13,42）和每个总线从机（14,15,44）具有一个计数器（30-33,75-76），用于存储当前管道深度值（21,51）中央管道计数器（16,72）。交易开始信号（20,50）和交易结束信号（22,52）用于选择性地递增和递减计数器（30-33,75-76）。

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