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1. 发明申请

US20120036398A1 MULTIPLE CORE DATA PROCESSOR WITH USAGE MONITORING 审中-公开
标题翻译：多核心数据处理器使用监控
公开(公告)号：US20120036398A1
公开(公告)日：2012-02-09
申请号：US13272725
申请日：2011-10-13
申请人： William C. Moyer , David R. Bearden , Ravindraraj Ramaraju
发明人： William C. Moyer , David R. Bearden , Ravindraraj Ramaraju
IPC分类号： G06F11/14 , G06F9/312
CPC分类号： G06F9/505 , G06F16/217 , G06F2209/504 , G06F2209/508 , Y02D10/22
摘要： A data processor with a plurality of processor cores. Accumulated usage information of each of the plurality of processor cores is stored in a storage device within the data processor, wherein the accumulated usage information is indicative of accumulated usage of each processor core of the plurality of processor cores. The processor uses the accumulated usage information in selecting processor cores to perform processor operations.
摘要翻译：具有多个处理器核心的数据处理器。多个处理器核心中的每一个的累积使用信息被存储在数据处理器内的存储设备中，其中累积的使用信息指示多个处理器核心的每个处理器核心的累积使用。处理器使用累积的使用信息来选择处理器核心来执行处理器操作。

2. 发明授权

US08566836B2 Multi-core system on chip 有权
标题翻译：多芯片系统芯片
公开(公告)号：US08566836B2
公开(公告)日：2013-10-22
申请号：US12618311
申请日：2009-11-13
申请人： Ravindraraj Ramaraju , David R. Bearden , William C. Moyer
发明人： Ravindraraj Ramaraju , David R. Bearden , William C. Moyer
IPC分类号： G06F9/46 , G06F7/38
CPC分类号： G06F9/5044 , Y02D10/22
摘要： A multi-core system on a chip (200) is described in which a speed information for each core (210, 220, 230, 240), such as the maximum operation speed (Fmax), is extracted and stored in a storage device, such as a device control registry (215), where it may be accessed and used by the operating system when allocating workload among the cores by selecting the fasted core (e.g, 210) to run any applications or tasks that can not be executed on a plurality of cores.
摘要翻译：描述了一种芯片上的多核系统（200），其中提取每个核心（210,220,230,240）的速度信息（如最大运行速度（Fmax））并将其存储在存储装置中，例如设备控制注册表（215），其中当通过选择禁止的核心（例如，210）来运行任何不能执行的应用程序或任务时，操作系统可以在操作系统之间分配工作负载时，访问和使用它们多个核心。

3. 发明申请

US20110191602A1 PROCESSOR WITH SELECTABLE LONGEVITY 审中-公开
标题翻译：具有可选择长度的处理器
公开(公告)号：US20110191602A1
公开(公告)日：2011-08-04
申请号：US12696633
申请日：2010-01-29
申请人： David R. Bearden , Ravindraraj Ramaraju , Peter P. Abramowitz , William C. Moyer
发明人： David R. Bearden , Ravindraraj Ramaraju , Peter P. Abramowitz , William C. Moyer
IPC分类号： G06F1/26
CPC分类号： G06F1/26
摘要： A processor and method has at least one processor core for processing information and receives an operating voltage for powering circuitry of the processor. A selector receives a value indicative of a temperature within the processor and receives a value from a plurality of possible longevity values that each indicates a predetermined desired longevity of valid operation of the processor. An output provides an identifier that controls at least one of an operating voltage or an operating frequency of the processor, wherein the identifier provided is at least based on the value indicative of temperature and the predetermined desired longevity. A reliability storage device coupled to the selector stores the value from the plurality of possible longevity values that each indicates the predetermined desired longevity of valid operation of the processor.
摘要翻译：处理器和方法具有用于处理信息的至少一个处理器核心并且接收用于为处理器的电路供电的工作电压。选择器接收指示处理器内的温度的值，并从多个可能的寿命值接收值，每个可能的寿命值指示处理器的有效操作的预定期望寿命。输出提供控制处理器的操作电压或操作频率中的至少一个的标识符，其中提供的标识符至少基于指示温度和预定期望寿命的值。耦合到选择器的可靠性存储设备存储来自多个可能的寿命值的值，每个可能的寿命值指示处理器的有效操作的预定期望寿命。

4. 发明申请

US20110265090A1 MULTIPLE CORE DATA PROCESSOR WITH USAGE MONITORING 审中-公开
标题翻译：多核心数据处理器使用监控
公开(公告)号：US20110265090A1
公开(公告)日：2011-10-27
申请号：US12765534
申请日：2010-04-22
申请人： WILLIAM C. MOYER , Ravindraraj Ramaraju , David R. Bearden
发明人： WILLIAM C. MOYER , Ravindraraj Ramaraju , David R. Bearden
IPC分类号： G06F9/46 , G06F17/30
CPC分类号： G06F9/5027 , G06F1/3203 , G06F11/3423 , G06F11/3433 , G06F16/217 , G06F2209/508
摘要： A data processor with a plurality of processor cores. Accumulated usage information of each of the plurality of processor cores is stored in a storage device within the data processor, wherein the accumulated usage information is indicative of accumulated usage of each processor core of the plurality of processor cores. Accumulated usage information for a core of the plurality of processor cores is updated in response to a determined use of the core.
摘要翻译：具有多个处理器核心的数据处理器。多个处理器核心中的每一个的累积使用信息被存储在数据处理器内的存储设备中，其中累积的使用信息指示多个处理器核心的每个处理器核心的累积使用。响应于所确定的核心的使用，更新多个处理器核心的累积使用信息。

5. 发明申请

US20110119672A1 Multi-Core System on Chip 有权
标题翻译：多核芯片系统
公开(公告)号：US20110119672A1
公开(公告)日：2011-05-19
申请号：US12618311
申请日：2009-11-13
申请人： Ravindraraj Ramaraju , David R. Bearden , William C. Moyer
发明人： Ravindraraj Ramaraju , David R. Bearden , William C. Moyer
IPC分类号： G06F9/46
CPC分类号： G06F9/5044 , Y02D10/22
摘要： A multi-core system on a chip (200) is described in which a speed information for each core (210, 220, 230, 240), such as the maximum operation speed (Fmax), is extracted and stored in a storage device, such as a device control registry (215), where it may be accessed and used by the operating system when allocating workload among the cores by selecting the fasted core (e.g, 210) to run any applications or tasks that can not be executed on a plurality of cores.
摘要翻译：描述了一种芯片上的多核系统（200），其中提取每个核心（210,220,230,240）的速度信息（如最大运行速度（Fmax））并将其存储在存储装置中，例如设备控制注册表（215），其中当通过选择禁止的核心（例如，210）来运行任何不能执行的应用程序或任务时，操作系统可以在操作系统之间分配工作负载时，访问和使用它们多个核心。

6. 发明授权

US09367475B2 System and method for cache access 有权
标题翻译：用于缓存访问的系统和方法
公开(公告)号：US09367475B2
公开(公告)日：2016-06-14
申请号：US13440728
申请日：2012-04-05
申请人： Ravindraraj Ramaraju , David R. Bearden , Andrew C. Russell
发明人： Ravindraraj Ramaraju , David R. Bearden , Andrew C. Russell
IPC分类号： G06F12/00 , G06F13/00 , G06F12/08 , G06F1/32
CPC分类号： G06F12/0895 , G06F1/3225 , G06F1/3275 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： The rows of a cache are generally maintained in a low power state. In response to a memory access operation, the data processor predicts a plurality of cache rows that may be targeted by the operation, and transitions each of the plurality of cache rows to an active state to prepare them for access. The plurality of cache rows are predicted based on speculatively decoding a portion of a base address and a corresponding portion of an offset without performing a full addition of the portions. Because a full addition is not performed, the speculative decoding can be performed at sufficient speed to allow the set of rows to be transitioned to the active state before full decoding of the memory address is completed. The cache row associated with the memory address is therefore ready for access when decoding is complete, maintaining low latency for cache accesses.
摘要翻译：缓存的行通常维持在低功率状态。响应于存储器访问操作，数据处理器预测可能由操作定向的多个高速缓存行，并且将多个高速缓存行中的每一个转换为活动状态以准备它们进行访问。基于对基本地址的一部分和偏移的对应部分的推测性解码来预测多个高速缓存行，而不执行部分的完全添加。由于没有执行完全相加，所以可以以足够的速度执行推测解码，以便在存储器地址的完全解码完成之前允许该组行转换到活动状态。因此，当解码完成时，与存储器地址相关联的高速缓存行可以进行访问，从而保持高速缓存访问的低延迟。

7. 发明申请

US20120200336A1 ELECTRONIC CIRCUIT HAVING SHARED LEAKAGE CURRENT REDUCTION CIRCUITS 有权
标题翻译：具有共享漏电流减少电路的电子电路
公开(公告)号：US20120200336A1
公开(公告)日：2012-08-09
申请号：US13020565
申请日：2011-02-03
申请人： Ravindraraj Ramaraju , David R. Bearden , Andrew C. Russell , Shayan Zhang
发明人： Ravindraraj Ramaraju , David R. Bearden , Andrew C. Russell , Shayan Zhang
IPC分类号： H03K3/011 , G05F1/10
CPC分类号： H03K19/0008 , H03K19/0016
摘要： An electronic circuit includes a plurality of circuit blocks, a plurality of bias circuits, a switching circuit, and plurality of transistors. The plurality of circuit blocks each includes a high power terminal and a low power terminal. The switching circuit includes a plurality of switches for selectively coupling a bias circuit of the plurality of bias circuits to the low power terminal of a circuit block of the plurality of circuit blocks. Each bias circuit of the plurality of bias circuits is selectively couplable to the low power terminal of each of the plurality of circuit blocks. Each transistor of the plurality of transistors has a first current terminal coupled to a circuit ground terminal, and each transistor of the plurality of transistors has a control terminal for controlling the conductivity of the plurality of the transistors by a bias circuit of the plurality of bias circuits.
摘要翻译：电子电路包括多个电路块，多个偏置电路，开关电路和多个晶体管。多个电路块各自包括高功率端子和低功率端子。开关电路包括多个开关，用于将多个偏置电路的偏置电路选择性地耦合到多个电路块的电路块的低功率端子。多个偏置电路的每个偏置电路可以选择性地耦合到多个电路块中的每一个的低功率端子。多个晶体管的每个晶体管具有耦合到电路接地端子的第一电流端子，并且多个晶体管中的每个晶体管具有控制端子，用于通过多个偏置的偏置电路来控制多个晶体管的导电性电路。

8. 发明授权

US08189408B2 Memory device having shifting capability and method thereof 有权
标题翻译：具有移动能力的存储装置及其方法
公开(公告)号：US08189408B2
公开(公告)日：2012-05-29
申请号：US12620314
申请日：2009-11-17
申请人： Ravi Gupta , David R. Bearden , Ravindraraj Ramaraju
发明人： Ravi Gupta , David R. Bearden , Ravindraraj Ramaraju
IPC分类号： G11C7/00
CPC分类号： G11C7/1006 , G11C7/1075 , G11C7/18 , G11C19/00 , G11C19/28
摘要： An array of memory bit cells are operable to provide a memory device having data shifting capability, so that data can be flexibly stored and retrieved from the memory device in both parallel and serial fashions. The memory array can thus be used for conventional memory storage operations, and also for operations, such as matrix operations, that provide for the alteration of the arrangement of stored data elements.
摘要翻译：存储器位单元阵列可操作以提供具有数据移位能力的存储器件，从而能够以并行和串行方式从存储器件灵活地存储和检索数据。因此，存储器阵列可以用于常规存储器存储操作，并且还可以用于提供对存储的数据元素的布置的改变的诸如矩阵操作的操作。

9. 发明申请

US20130268732A1 SYSTEM AND METHOD FOR CACHE ACCESS 有权
标题翻译：用于缓存访问的系统和方法
公开(公告)号：US20130268732A1
公开(公告)日：2013-10-10
申请号：US13440728
申请日：2012-04-05
申请人： Ravindraraj Ramaraju , David R. Bearden , Andrew C. Russell
发明人： Ravindraraj Ramaraju , David R. Bearden , Andrew C. Russell
IPC分类号： G06F12/08
CPC分类号： G06F12/0895 , G06F1/3225 , G06F1/3275 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： The rows of a cache are generally maintained in a low power state. In response to a memory access operation, the data processor predicts a plurality of cache rows that may be targeted by the operation, and transitions each of the plurality of cache rows to an active state to prepare them for access. The plurality of cache rows are predicted based on speculatively decoding a portion of a base address and a corresponding portion of an offset without performing a full addition of the portions. Because a full addition is not performed, the speculative decoding can be performed at sufficient speed to allow the set of rows to be transitioned to the active state before full decoding of the memory address is completed. The cache row associated with the memory address is therefore ready for access when decoding is complete, maintaining low latency for cache accesses.
摘要翻译：缓存的行通常维持在低功率状态。响应于存储器访问操作，数据处理器预测可能由操作定向的多个高速缓存行，并且将多个高速缓存行中的每一个转换为活动状态以准备它们进行访问。基于对基本地址的一部分和偏移的对应部分的推测性解码来预测多个高速缓存行，而不执行部分的完全添加。由于没有执行完全相加，所以可以以足够的速度执行推测解码，以便在存储器地址的完全解码完成之前允许该组行转换到活动状态。因此，当解码完成时，与存储器地址相关联的高速缓存行可以进行访问，从而保持高速缓存访问的低延迟。

10. 发明申请

US20130046928A1 Memory Management Unit Tag Memory 有权
标题翻译：内存管理单元标签内存
公开(公告)号：US20130046928A1
公开(公告)日：2013-02-21
申请号：US13213900
申请日：2011-08-19
申请人： Ravindraraj Ramaraju , David R. Bearden , Prashant U. Kenkare , Jogendra C. Sarker
发明人： Ravindraraj Ramaraju , David R. Bearden , Prashant U. Kenkare , Jogendra C. Sarker
IPC分类号： G06F12/02
CPC分类号： G06F12/1027 , G06F9/355 , G06F9/3824 , G06F9/3832 , G11C15/04
摘要： A method and data processing system for accessing an entry in a memory array by placing a tag memory unit (114) in parallel with an operand adder circuit (112) to enable tag lookup and generation of speculative way hit/miss information (126) directly from the operands (111, 113) without using the output sum of the operand adder. PGZ-encoded address bits (0:51) from the operands (111, 113) are applied with a carry-out value (Cout48) to a content-addressable memory array (114) to generate two speculative hit/miss signals. A sum value (EA51) computed from the least significant base and offset address bits determines which of the speculative hit/miss signals is selected for output (126).
摘要翻译：一种方法和数据处理系统，用于通过将标记存储器单元（114）与操作数加法器电路（112）并行放置来访问存储器阵列中的入口，以使标签查找和直接产生投机方式命中/未命中信息（126）不使用操作数加法器的输出和从操作数（111,113）中读出。将来自操作数（111,113）的PGZ编码的地址位（0:51）与进位值（Cout48）一起施加到内容寻址存储器阵列（114），以产生两个推测的命中/未命中信号。从最低有效基址和偏移地址位计算的和值（EA51）确定选择哪种推测性命中/未命中信号用于输出（126）。

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