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1. 发明申请

US20130046928A1 Memory Management Unit Tag Memory 有权
标题翻译：内存管理单元标签内存
公开(公告)号：US20130046928A1
公开(公告)日：2013-02-21
申请号：US13213900
申请日：2011-08-19
申请人： Ravindraraj Ramaraju , David R. Bearden , Prashant U. Kenkare , Jogendra C. Sarker
发明人： Ravindraraj Ramaraju , David R. Bearden , Prashant U. Kenkare , Jogendra C. Sarker
IPC分类号： G06F12/02
CPC分类号： G06F12/1027 , G06F9/355 , G06F9/3824 , G06F9/3832 , G11C15/04
摘要： A method and data processing system for accessing an entry in a memory array by placing a tag memory unit (114) in parallel with an operand adder circuit (112) to enable tag lookup and generation of speculative way hit/miss information (126) directly from the operands (111, 113) without using the output sum of the operand adder. PGZ-encoded address bits (0:51) from the operands (111, 113) are applied with a carry-out value (Cout48) to a content-addressable memory array (114) to generate two speculative hit/miss signals. A sum value (EA51) computed from the least significant base and offset address bits determines which of the speculative hit/miss signals is selected for output (126).
摘要翻译：一种方法和数据处理系统，用于通过将标记存储器单元（114）与操作数加法器电路（112）并行放置来访问存储器阵列中的入口，以使标签查找和直接产生投机方式命中/未命中信息（126）不使用操作数加法器的输出和从操作数（111,113）中读出。将来自操作数（111,113）的PGZ编码的地址位（0:51）与进位值（Cout48）一起施加到内容寻址存储器阵列（114），以产生两个推测的命中/未命中信号。从最低有效基址和偏移地址位计算的和值（EA51）确定选择哪种推测性命中/未命中信号用于输出（126）。

2. 发明授权

US09021194B2 Memory management unit tag memory 有权
标题翻译：内存管理单元标签内存
公开(公告)号：US09021194B2
公开(公告)日：2015-04-28
申请号：US13213900
申请日：2011-08-19
申请人： Ravindraraj Ramaraju , David R. Bearden , Prashant U. Kenkare , Jogendra C. Sarker
发明人： Ravindraraj Ramaraju , David R. Bearden , Prashant U. Kenkare , Jogendra C. Sarker
IPC分类号： G06F9/355 , G06F9/38 , G06F12/10
CPC分类号： G06F12/1027 , G06F9/355 , G06F9/3824 , G06F9/3832 , G11C15/04
摘要： A method and data processing system for accessing an entry in a memory array by placing a tag memory unit (114) in parallel with an operand adder circuit (112) to enable tag lookup and generation of speculative way hit/miss information (126) directly from the operands (111, 113) without using the output sum of the operand adder. PGZ-encoded address bits (0:51) from the operands (111, 113) are applied with a carry-out value (Cout48) to a content-addressable memory array (114) to generate two speculative hit/miss signals. A sum value (EA51) computed from the least significant base and offset address bits determines which of the speculative hit/miss signals is selected for output (126).
摘要翻译：一种方法和数据处理系统，用于通过将标记存储器单元（114）与操作数加法器电路（112）并行放置来访问存储器阵列中的入口，以使标签查找和直接产生投机方式命中/未命中信息（126）不使用操作数加法器的输出和从操作数（111,113）中读出。将来自操作数（111,113）的PGZ编码的地址位（0:51）与进位值（Cout48）一起施加到内容寻址存储器阵列（114），以产生两个推测的命中/未命中信号。从最低有效基址和偏移地址位计算的和值（EA51）确定选择哪种推测性命中/未命中信号用于输出（126）。

3. 发明授权

US07161827B2 SRAM having improved cell stability and method therefor 有权
标题翻译：具有改善细胞稳定性的SRAM及其方法
公开(公告)号：US07161827B2
公开(公告)日：2007-01-09
申请号：US11033934
申请日：2005-01-12
申请人： Ravindraraj Ramaraju , Prashant U. Kenkare , Jogendra C. Sarker
发明人： Ravindraraj Ramaraju , Prashant U. Kenkare , Jogendra C. Sarker
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A SRAM (14) includes a SRAM cell (26), the cell (26) includes a first storage node (N1), a second storage node (N2), and a cross coupled latch (40) including a first primary source current path to the first storage node, a first primary sink current path to the first storage node, a second primary source current path to the second storage node, a second primary sink current path to the second storage node, a fifth primary current path to the first storage node, and a sixth primary current path to the second storage node. During standby and/or a read operation of the SRAM cell (26), one of the fifth primary current path and the sixth primary current path is conductive. During a write operation, the fifth primary current path and the sixth primary current path are non-conductive.
摘要翻译： SRAM（14）包括SRAM单元（26），单元（26）包括第一存储节点（N 1），第二存储节点（N 2）和交叉耦合的锁存器（40），其包括第一主源到第一存储节点的当前路径，到第一存储节点的第一主宿当前路径，到第二存储节点的第二主源电流路径，到第二存储节点的第二主宿宿电流路径，第五主要电流路径第一存储节点和到第二存储节点的第六主要电流路径。在SRAM单元（26）的待机和/或读取操作期间，第五初级电流路径和第六初级电流路径之一是导电的。在写入操作期间，第五初级电流路径和第六初级电流路径是非导通的。

4. 发明授权

US07193924B2 Dual-port static random access memory having improved cell stability and write margin 有权
标题翻译：双端口静态随机存取存储器具有改善的单元稳定性和写裕度
公开(公告)号：US07193924B2
公开(公告)日：2007-03-20
申请号：US11123514
申请日：2005-05-06
申请人： Ravindraraj Ramaraju , Prashant U. Kenkare , Jogendra C. Sarker
发明人： Ravindraraj Ramaraju , Prashant U. Kenkare , Jogendra C. Sarker
IPC分类号： G11C8/00 , G11C7/10
CPC分类号： G11C8/16 , G11C11/412 , G11C11/413
摘要： A dual-port memory includes a plurality of memory cells coupled to a row decoder and column logic. Each memory cell includes two storage nodes, where each storage node is coupled to a bit line via an access transistor. Each memory cell also includes a logic gate for logically combining a word line signal with a column address signal and providing the resulting output signal to the gates of the access transistors. In one embodiment, the logic gate is a NOR logic gate and in another embodiment, the logic gate is a transmission gate. This prevents a potential read disturb problem with unselected memory cells of a row. This also reduces power consumption in the memory.
摘要翻译：双端口存储器包括耦合到行解码器和列逻辑的多个存储器单元。每个存储单元包括两个存储节点，其中每个存储节点经由存取晶体管耦合到位线。每个存储单元还包括用于逻辑地组合字线信号和列地址信号的逻辑门，并将得到的输出信号提供给存取晶体管的栅极。在一个实施例中，逻辑门是NOR逻辑门，在另一个实施例中，逻辑门是传输门。这可以防止一行的未选择的存储单元发生潜在的读取干扰问题。这也降低了内存中的功耗。

5. 发明授权

US08943292B2 System and method for memory array access with fast address decoder 有权
标题翻译：具有快速地址解码器的存储器阵列访问的系统和方法
公开(公告)号：US08943292B2
公开(公告)日：2015-01-27
申请号：US11552817
申请日：2006-10-25
申请人： Ravindraraj Ramaraju , David R. Bearden , Prashant U. Kenkare
发明人： Ravindraraj Ramaraju , David R. Bearden , Prashant U. Kenkare
IPC分类号： G06F12/02 , G06F9/355 , G06F9/345
CPC分类号： G06F9/355 , G06F9/345
摘要： A method includes storing a first transaction entry to a first software configurable storage location, storing a second transaction entry to a second software configurable storage location, determining that a first transaction indicated by the first transaction entry has occurred, determining that a second transaction indicated by the second transaction entry has occurred subsequent to the first transaction, and, in response to determining that the first transaction occurred and the second transaction occurred, storing at least one transaction attribute captured during at least one clock cycle subsequent to the second transaction. The first and second software configurable storage locations may be located in a trace buffer, where the at least one transaction attribute is stored to the trace buffer and overwrites the first and second transaction attributes. Each transaction entry may include a dead cycle field, a consecutive transaction requirement field, and a last entry field.
摘要翻译：一种方法包括将第一交易条目存储到第一软件可配置存储位置，将第二交易条目存储到第二软件可配置存储位置，确定由第一交易条目指示的第一交易已经发生，确定由第一交易条目指示的第二交易第二交易条目已经在第一交易之后发生，并且响应于确定第一交易发生和第二交易发生，存储在第二交易之后的至少一个时钟周期期间捕获的至少一个交易属性。第一和第二软件可配置存储位置可以位于跟踪缓冲器中，其中至少一个事务属性被存储到跟踪缓冲器并且覆盖第一和第二事务属性。每个交易条目可以包括死循环字段，连续交易需求字段和最后输入字段。

6. 发明授权

US07984229B2 Pipelined tag and information array access with speculative retrieval of tag that corresponds to information access 有权
标题翻译：流水线标签和信息数组访问，与信息访问相对应的标签的推测检索
公开(公告)号：US07984229B2
公开(公告)日：2011-07-19
申请号：US11684529
申请日：2007-03-09
申请人： Ravindraraj Ramaraju , Ambica Ashok , David R. Bearden , Prashant U. Kenkare
发明人： Ravindraraj Ramaraju , Ambica Ashok , David R. Bearden , Prashant U. Kenkare
IPC分类号： G06F12/00
CPC分类号： G06F12/0895 , Y02D10/13
摘要： A cache design is described in which corresponding accesses to tag and information arrays are phased in time, and in which tags are retrieved (typically speculatively) from a tag array without benefit of an effective address calculation subsequently used for a corresponding retrieval from an information array. In some exploitations, such a design may allow cycle times (and throughput) of a memory subsystem to more closely match demands of some processor and computation system architectures. Our techniques seek to allow early (indeed speculative) retrieval from the tag array without delays that would otherwise be associated with calculation of an effective address eventually employed for a corresponding retrieval from the information array. Speculation can be resolved using the eventually calculated effective address or using separate functionality. In some embodiments, we use calculated effective addresses for way selection based on tags retrieved from the tag array.
摘要翻译：描述了一种高速缓存设计，其中对标签和信息数组的相应访问在时间上是相位的，并且其中从标签数组中检索（通常是推测性地）的标签，而不受随后用于从信息数组的相应检索的有效地址计算的益处。在一些开发中，这样的设计可以允许存储器子系统的周期时间（和吞吐量）更接近地匹配一些处理器和计算系统架构的需求。我们的技术旨在允许从标签数组中提前（确实是推测性的）检索，而不会延迟，否则将与从信息数组中相应检索最终采用的有效地址的计算相关联。可以使用最终计算的有效地址或使用单独的功能来解决投机。在一些实施例中，我们使用基于从标签阵列检索的标签的方法选择的计算的有效地址。

7. 发明申请

US20080222361A1 PIPELINED TAG AND INFORMATION ARRAY ACCESS WITH SPECULATIVE RETRIEVAL OF TAG THAT CORRESPONDS TO INFORMATION ACCESS 有权
标题翻译：管道标签和信息阵列访问与信息访问相关的标签的检索
公开(公告)号：US20080222361A1
公开(公告)日：2008-09-11
申请号：US11684529
申请日：2007-03-09
申请人： Ravindraraj Ramaraju , Ambica Ashok , David R. Bearden , Prashant U. Kenkare
发明人： Ravindraraj Ramaraju , Ambica Ashok , David R. Bearden , Prashant U. Kenkare
IPC分类号： G06F12/08
CPC分类号： G06F12/0895 , Y02D10/13
摘要： A cache design is described in which corresponding accesses to tag and information arrays are phased in time, and in which tags are retrieved (typically speculatively) from a tag array without benefit of an effective address calculation subsequently used for a corresponding retrieval from an information array. In some exploitations, such a design may allow cycle times (and throughput) of a memory subsystem to more closely match demands of some processor and computation system architectures. In some cases, phased access can be described as pipelined tag and information array access, though strictly speaking, indexing into the information array need not depend on results of the tag array access. Our techniques seek to allow early (indeed speculative) retrieval from the tag array without delays that would otherwise be associated with calculation of an effective address eventually employed for a corresponding retrieval from the information array. Speculation can be resolved using the eventually calculated effective address or using separate functionality. In some embodiments, we use calculated effective addresses for way selection based on tags retrieved from the tag array.
摘要翻译：描述了一种高速缓存设计，其中对标签和信息数组的相应访问在时间上是相位的，并且其中从标签数组中检索（通常是推测性地）的标签，而不受随后用于从信息数组的相应检索的有效地址计算的益处。在一些开发中，这样的设计可以允许存储器子系统的周期时间（和吞吐量）更接近地匹配一些处理器和计算系统架构的需求。在某些情况下，分阶段访问可以被描述为流水线标签和信息数组访问，但严格来说，索引到信息数组不需要依赖于标签数组访问的结果。我们的技术旨在允许从标签数组中提前（确实是推测性的）检索，而不会延迟，否则将与从信息数组中相应检索最终采用的有效地址的计算相关联。可以使用最终计算的有效地址或使用单独的功能来解决投机。在一些实施例中，我们使用基于从标签阵列检索的标签的方法选择的计算的有效地址。

8. 发明授权

US07843218B1 Data latch with structural hold 有权
标题翻译：数据锁存结构保持
公开(公告)号：US07843218B1
公开(公告)日：2010-11-30
申请号：US12607657
申请日：2009-10-28
申请人： Ravindraraj Ramaraju , David R. Bearden , Cody B. Croxton , Prashant U. Kenkare
发明人： Ravindraraj Ramaraju , David R. Bearden , Cody B. Croxton , Prashant U. Kenkare
IPC分类号： H03K19/173
CPC分类号： G01R31/318541
摘要： A multiplexed data flip-flop circuit (500) is described in which a multiplexer (510) outputs functional or scan data, a master latch (520) generates a master latch output signal at a hold time under control of a master clock signal, a slave latch (540) generates a flip flop output signal at a launch time under control of a slave clock signal, clock generation circuitry (550) generates a second clock signal that has a DC state during a functional mode and has a switching state during a scan mode, and data propagation logic circuitry (564) uses the first and second clock signals to generate the master and slave clock signals during a scan mode to delay the launch time of the slave latch with respect to the hold time of the master latch.
摘要翻译：描述了多路复用数据触发器电路（500），其中复用器（510）输出功能或扫描数据，主锁存器（520）在主时钟信号的控制下在保持时间产生主锁存器输出信号，从锁存器（540）在从时钟信号的控制下在启动时产生触发器输出信号，时钟产生电路（550）产生在功能模式期间具有DC状态的第二时钟信号，并且在第一时钟信号期间具有开关状态扫描模式和数据传播逻辑电路（564）在扫描模式期间使用第一和第二时钟信号来产生主时钟信号和从时钟信号，以相对于主锁存器的保持时间延迟从锁存器的启动时间。

9. 发明申请

US20080109508A1 SYSTEM HAVING A CARRY LOOK-AHEAD (CLA) ADDER 审中-公开
标题翻译：系统有一个携带的前瞻性（CLA）ADDER
公开(公告)号：US20080109508A1
公开(公告)日：2008-05-08
申请号：US11550835
申请日：2006-10-19
申请人： Prashant U. Kenkare , Jogendra C. Sarker
发明人： Prashant U. Kenkare , Jogendra C. Sarker
IPC分类号： G06F7/50
CPC分类号： G06F7/508
摘要： In a system having stored operands in various locations, addition is performed without having to store the operands in preparation for an add operation. Bitwise propagate and generate terms are efficiently created to speed up additions in the system. Combinational logic circuitry has a plurality of inputs and provides a first operand and a second operand during a first phase of a cycle of a clock signal. A carry look-ahead adder (CLA) has first and second inputs directly connected to the combinational logic circuitry for respectively receiving the first operand and the second operand during the first phase of the cycle of the clock signal and creates generate bits and propagate bits prior to beginning of a second phase of the cycle of the clock signal. The adder uses the generate bits and propagate bits to provide a sum of the first operand and the second operand.
摘要翻译：在具有各种位置的存储操作数的系统中，执行相加操作，而不必存储操作数以准备添加操作。有效创建按位传播和生成术语以加速系统中的添加。组合逻辑电路具有多个输入，并且在时钟信号的周期的第一阶段期间提供第一操作数和第二操作数。进位预读加法器（CLA）具有直接连接到组合逻辑电路的第一和第二输入，用于在时钟信号的周期的第一阶段期间分别接收第一操作数和第二操作数，并创建生成位和传播位到时钟信号的周期的第二阶段的开始。加法器使用生成位和传播位来提供第一操作数和第二操作数的和。

10. 发明申请

US20140306745A1 FLIP-FLOP HAVING SHARED FEEDBACK AND METHOD OF OPERATION 有权
标题翻译：具有共享反馈的翻转和操作方法
公开(公告)号：US20140306745A1
公开(公告)日：2014-10-16
申请号：US14316315
申请日：2014-06-26
申请人： RAVINDRARAJ RAMARAJU , Prashant U. Kenkare
发明人： RAVINDRARAJ RAMARAJU , Prashant U. Kenkare
IPC分类号： H03K3/037
CPC分类号： H03K3/0372 , H03K3/0375 , H03K3/356156 , H03K3/356173
摘要： A method of operating a circuit includes receiving a first data signal at a first node. The first node is coupled to a second node to couple the first data signal to the second node. After coupling the first node to the second node, an inversion is enabled from the second node to a third node. An inversion from the third node to the fourth node is provided. After the enabling the inversion from the second node to the third node, the first node is decoupled from the second node. After the enabling the inversion from the second node to the third node, the second node is coupled to the third node. An inversion from the fourth node to the third node is enabled and the second node is decoupled from the fourth node.
摘要翻译：一种操作电路的方法包括在第一节点处接收第一数据信号。第一节点耦合到第二节点以将第一数据信号耦合到第二节点。在将第一节点耦合到第二节点之后，从第二节点到第三节点启用反转。提供从第三节点到第四节点的反转。在启用从第二节点到第三节点的反转之后，第一节点与第二节点分离。在启用从第二节点到第三节点的反转之后，第二节点耦合到第三节点。启用从第四节点到第三节点的反转，并且第二节点与第四节点分离。

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