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1. 发明授权

US06974983B1 Isolated FinFET P-channel/N-channel transistor pair 有权
标题翻译：隔离型FinFET P沟道/ N沟道晶体管对
公开(公告)号：US06974983B1
公开(公告)日：2005-12-13
申请号：US10768660
申请日：2004-02-02
申请人： Wiley Eugene Hill , Shibly S. Ahmed , Haihong Wang , Bin Yu
发明人： Wiley Eugene Hill , Shibly S. Ahmed , Haihong Wang , Bin Yu
IPC分类号： H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786 , H01L21/062
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/66795
摘要： A semiconductor device includes an N-channel device and a P-channel device. The N-channel device includes a first source region, a first drain region, a first fin structure, and a gate. The P-channel device includes a second source region, a second drain region, a second fin structure, and the gate. The second source region, the second drain region, and the second fin structure are separated from the first source region, the first drain region, and the first fin structure by a channel stop layer.
摘要翻译：半导体器件包括N沟道器件和P沟道器件。 N沟道器件包括第一源极区，第一漏极区，第一鳍结构和栅极。 P沟道器件包括第二源极区，第二漏极区，第二鳍结构和栅极。第二源极区域，第二漏极区域和第二鳍状结构通过沟道阻挡层与第一源极区域，第一漏极区域和第一鳍片结构分离。

2. 发明授权

US06914277B1 Merged FinFET P-channel/N-channel pair 有权
标题翻译：合并FinFET P沟道/ N沟道对
公开(公告)号：US06914277B1
公开(公告)日：2005-07-05
申请号：US10674400
申请日：2003-10-01
申请人： Wiley Eugene Hill , Shibly S. Ahmed , Haihong Wang , Bin Yu
发明人： Wiley Eugene Hill , Shibly S. Ahmed , Haihong Wang , Bin Yu
IPC分类号： H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786 , H01L29/76
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/66795
摘要： A semiconductor device includes an N-channel device and a P-channel device. The N-channel device includes a first source region, a first drain region, a first fin structure, and a gate. The P-channel device includes a second source region, a second drain region, a second fin structure, and the gate. The second source region, the second drain region, and the second fin structure are separated from the first source region, the first drain region, and the first fin structure by an insulating layer.
摘要翻译：半导体器件包括N沟道器件和P沟道器件。 N沟道器件包括第一源极区，第一漏极区，第一鳍结构和栅极。 P沟道器件包括第二源极区，第二漏极区，第二鳍结构和栅极。第二源极区域，第二漏极区域和第二鳍状结构通过绝缘层与第一源极区域，第一漏极区域和第一鳍片结构分离。

3. 发明授权

US06787406B1 Systems and methods for forming dense n-channel and p-channel fins using shadow implanting 有权
标题翻译：使用阴影植入形成致密的n通道和p通道翅片的系统和方法
公开(公告)号：US06787406B1
公开(公告)日：2004-09-07
申请号：US10638334
申请日：2003-08-12
申请人： Wiley Eugene Hill , Shibly S. Ahmed , Haihong Wang , Bin Yu
发明人： Wiley Eugene Hill , Shibly S. Ahmed , Haihong Wang , Bin Yu
IPC分类号： H01L2184
CPC分类号： H01L29/785 , H01L21/26586 , H01L21/84 , H01L27/1203 , H01L29/66795 , H01L29/66803 , Y10S438/944
摘要： A method facilitates the doping of fins of a semiconductor device that includes a substrate. The method includes forming fin structures on the substrate, where each of the fin structures includes a cap formed on a fin. The method further includes performing a first tilt angle implant process to dope a first one of the fins with n-type impurities and performing a second tilt angle implant process to dope a second one of the fins with p-type impurities.
摘要翻译：一种方法有助于掺杂包括衬底的半导体器件的散热片。该方法包括在基板上形成翅片结构，其中每个翅片结构都包括形成在翅片上的盖。该方法还包括执行第一倾斜角度注入工艺以用n型杂质掺杂第一个翅片，并执行第二倾斜角度注入工艺，以使p型杂质掺杂第二个翅片。

4. 发明授权

US06933558B2 Flash memory device 有权
标题翻译：闪存设备
公开(公告)号：US06933558B2
公开(公告)日：2005-08-23
申请号：US10726508
申请日：2003-12-04
申请人： Wiley Eugene Hill , Haihong Wang , Yider Wu , Bin Yu
发明人： Wiley Eugene Hill , Haihong Wang , Yider Wu , Bin Yu
IPC分类号： G11C16/04 , H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/792
CPC分类号： H01L21/28273 , H01L27/115 , H01L27/11556 , H01L29/785
摘要： A memory device includes a conductive structure, a number of dielectric layers and a control gate. The dielectric layers are formed around the conductive structure and the control gate is formed over the dielectric layers. A portion of the conductive structure functions as a drain region for the memory device and at least one of the dielectric layers functions as a charge storage structure for the memory device. The dielectric layers may include oxide-nitride-oxide layers.
摘要翻译：存储器件包括导电结构，多个电介质层和控制栅极。电介质层形成在导电结构周围，并且控制栅极形成在电介质层上。导电结构的一部分用作存储器件的漏极区，并且至少一个介电层用作存储器件的电荷存储结构。电介质层可以包括氧化物 - 氮化物 - 氧化物层。

5. 发明授权

US07298007B1 SRAM formation using shadow implantation 有权
标题翻译：使用阴影植入的SRAM形成
公开(公告)号：US07298007B1
公开(公告)日：2007-11-20
申请号：US11171399
申请日：2005-07-01
申请人： Wiley Eugene Hill , Bin Yu
发明人： Wiley Eugene Hill , Bin Yu
IPC分类号： H01L29/76
CPC分类号： H01L27/1108 , H01L21/845 , H01L27/11 , H01L27/1211 , H01L29/66803 , H01L29/785 , Y10S257/903 , Y10S438/944
摘要： A memory device includes multiple fins formed adjacent to one another, a source region, a drain region, a gate, a wordline, and a bitline contact. At least one of the multiple fins is doped with a first type of impurities and at least one other one of the fins is doped with a second type of impurities. The source region is formed at one end of each of the fins and the drain region is formed at an opposite end of each of the fins. The gate is formed over two of the multiple fins, the wordline is formed over each of the multiple fins, and a bitline contact is formed adjacent at least one of the multiple fins.
摘要翻译：存储器件包括彼此相邻形成的多个鳍，源极区，漏极区，栅极，字线和位线接触。多个翅片中的至少一个被掺杂有第一类型的杂质，并且至少另外一个翅片掺杂有第二类型的杂质。源区域形成在每个散热片的一端，并且漏极区域形成在每个散热片的相对端。栅极形成在多个散热片的两个之上，字线形成在多个散热片的每一个上，并且与多个散热片中的至少一个相邻地形成有位线接触。

6. 发明授权

US07064022B1 Method of forming merged FET inverter/logic gate 有权
标题翻译：形成合并FET逆变器/逻辑门的方法
公开(公告)号：US07064022B1
公开(公告)日：2006-06-20
申请号：US10728844
申请日：2003-12-08
申请人： Wiley Eugene Hill , Ming-Ren Lin , Bin Yu
发明人： Wiley Eugene Hill , Ming-Ren Lin , Bin Yu
IPC分类号： H01L21/00 , H01L21/84 , H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/7854 , H01L21/26586 , H01L21/845 , H01L27/11 , H01L27/1203 , H01L29/66795
摘要： A method forms a semiconductor device from a device that includes a first source region, a first drain region, and a first fin structure that are separated from a second source region, a second drain region, and a second fin structure by an insulating layer. The method may include forming a dielectric layer over the device and removing portions of the dielectric layer to create covered portions and bare portions. The method may also include depositing a gate material over the covered portions and bare portions, doping the first fin structure, the first source region, and the first drain region with a first material, and doping the second fin structure, the second source region, and the second drain region with a second material. The method may further include removing a portion of the gate material over at least one covered portion to form the semiconductor device.
摘要翻译：一种方法从包括通过绝缘层与第二源极区域，第二漏极区域和第二鳍状结构分离的第一源极区域，第一漏极区域和第一鳍状物结构的器件形成半导体器件。该方法可以包括在器件上形成电介质层并去除介电层的部分以产生被覆盖部分和裸露部分。该方法还可以包括在覆盖部分和裸露部分上沉积栅极材料，用第一材料掺杂第一鳍片结构，第一源极区域和第一漏极区域，并掺杂第二鳍片结构，第二源极区域，和具有第二材料的第二漏区。该方法还可以包括在至少一个被覆部分上去除栅极材料的一部分以形成半导体器件。

7. 发明授权

US07297581B1 SRAM formation using shadow implantation 有权
标题翻译：使用阴影植入的SRAM形成
公开(公告)号：US07297581B1
公开(公告)日：2007-11-20
申请号：US11130161
申请日：2005-05-17
申请人： Wiley Eugene Hill , Bin Yu
发明人： Wiley Eugene Hill , Bin Yu
IPC分类号： H01L21/338
CPC分类号： H01L27/1108 , H01L21/845 , H01L27/11 , H01L27/1211 , H01L29/66803 , H01L29/785 , Y10S257/903 , Y10S438/944
摘要： A method of doping fins of a semiconductor device that includes a substrate includes forming multiple fin structures on the substrate, each of the fin structures including a cap formed on a fin. The method further includes performing a first tilt angle implant process to dope a first pair of the multiple fin structures with n-type impurities and performing a second tilt angle implant process to dope a second pair of the multiple fin structures with p-type impurities.
摘要翻译：掺杂包括衬底的半导体器件的散热片的方法包括在衬底上形成多个翅片结构，每个翅片结构包括形成在翅片上的盖。该方法还包括执行第一倾斜角度注入过程以用n型杂质掺杂第一对多鳍片结构，并执行第二倾斜角度注入工艺以将第二对多鳍片结构与p型杂质掺杂。

8. 发明授权

US06924561B1 SRAM formation using shadow implantation 有权
标题翻译：使用阴影植入的SRAM形成
公开(公告)号：US06924561B1
公开(公告)日：2005-08-02
申请号：US10728910
申请日：2003-12-08
申请人： Wiley Eugene Hill , Bin Yu
发明人： Wiley Eugene Hill , Bin Yu
IPC分类号： H01L21/336 , H01L21/8244 , H01L21/84 , H01L27/11 , H01L27/12 , H01L29/786
CPC分类号： H01L27/1108 , H01L21/845 , H01L27/11 , H01L27/1211 , H01L29/66803 , H01L29/785 , Y10S257/903 , Y10S438/944
摘要： A memory device includes multiple fins formed adjacent to one another, a source region, a drain region, a gate, a wordline, and a bitline contact. At least one of the multiple fins is doped with a first type of impurities and at least one other one of the fins is doped with a second type of impurities. The source region is formed at one end of each of the fins and the drain region is formed at an opposite end of each of the fins. The gate is formed over two of the multiple fins, the wordline is formed over each of the multiple fins, and a bitline contact is formed adjacent at least one of the multiple fins.
摘要翻译：存储器件包括彼此相邻形成的多个鳍，源极区，漏极区，栅极，字线和位线接触。多个翅片中的至少一个被掺杂有第一类型的杂质，并且至少另外一个翅片掺杂有第二类型的杂质。源区域形成在每个散热片的一端，并且漏极区域形成在每个散热片的相对端。栅极形成在多个散热片的两个之上，字线形成在多个散热片的每一个上，并且与多个散热片中的至少一个相邻地形成有位线接触。

9. 发明授权

US06516450B1 Variable design rule tool 有权
标题翻译：可变设计规则工具
公开(公告)号：US06516450B1
公开(公告)日：2003-02-04
申请号：US09476955
申请日：2000-01-03
申请人： Wiley Eugene Hill , Kurt Taylor , Chern-Jiann Lee , Rithy Hang , Todd Lukanc
发明人： Wiley Eugene Hill , Kurt Taylor , Chern-Jiann Lee , Rithy Hang , Todd Lukanc
IPC分类号： G06F1750
CPC分类号： G06F17/5081
摘要： A variable design tool utilizes memory units to determine at which point a design rule fails. The variable design tool can provide a bit map indicating the points of failures for particular rules. The bit map can also be utilized to determine misalignment errors. The memory cells, typically SRAM units are arranged in 4×4 matrices which are arranged in four 16×16 matrices.
摘要翻译：可变设计工具利用内存单元来确定设计规则在哪一时刻失败。变量设计工具可以提供指示特定规则的故障点的位图。位图也可用于确定不对准误差。存储单元（通常为SRAM单元）以4×4矩阵的形式排列成四个16×16矩阵。

10. 发明授权

US07101722B1 In-line voltage contrast determination of tunnel oxide weakness in integrated circuit technology development 失效
标题翻译：集成电路技术开发中隧道氧化物薄弱的在线电压对比度测定
公开(公告)号：US07101722B1
公开(公告)日：2006-09-05
申请号：US10839444
申请日：2004-05-04
申请人： John J. Wang , Jeffrey P. Erhardt , Wiley Eugene Hill
发明人： John J. Wang , Jeffrey P. Erhardt , Wiley Eugene Hill
IPC分类号： H01L21/00
CPC分类号： G01R31/307 , G01R31/2831 , G11C16/04 , G11C29/006 , G11C29/50 , G11C29/56 , G11C29/56008 , G11C2029/0403 , G11C2029/4002 , G11C2029/5004 , G11C2029/5602
摘要： A method for determination of tunnel oxide weakness is provided. A tunnel oxide layer is formed on a semiconductor wafer. At least one poly gate is formed on the tunnel oxide layer in a flash memory region of the semiconductor wafer. At least one poly island, which is substantially larger than the poly gate, is formed on the tunnel oxide layer in a voltage contrast cell region of the semiconductor wafer. The poly island and the tunnel oxide layer therebeneath form a voltage contrast tunnel oxide cell. A voltage contrast measurement is performed on the voltage contrast tunnel oxide cell. The voltage contrast measurement is then compared with prior such voltage contrast measurements on other such voltage contrast tunnel oxide cells. The tunnel oxide weakness of the tunnel oxide layer is then determined from the voltage contrast measurement comparisons.
摘要翻译：提供了一种确定隧道氧化物弱化的方法。在半导体晶片上形成隧道氧化物层。在半导体晶片的闪存区域中的隧道氧化物层上形成至少一个多晶硅栅极。在半导体晶片的电压对比单元区域中的隧道氧化物层上形成至少一个大于多晶硅栅极的多晶硅岛。其上的多岛和隧道氧化物层形成电压对比隧道氧化物电池。对电压对比度隧道氧化物电池进行电压对比度测量。然后将电压对比度测量与其他这样的电压对比隧道氧化物电池的先前的这种电压对比度测量进行比较。然后从电压对比度测量比较确定隧道氧化物层的隧道氧化物弱点。

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