专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06588000B2 Method of partitioning large transistor design to facilitate transistor level timing 失效
公开(公告)号：US06588000B2
公开(公告)日：2003-07-01
申请号：US09682248
申请日：2001-08-09
申请人： Paul T. Gutwin , Peter J. Osler
发明人： Paul T. Gutwin , Peter J. Osler
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A method and system for partitioning a large transistor design including transistors and transistor networks, and of the type having a top hierarchical design level and a second, lower hierarchical design level. The method comprises the steps of identifying a desired number of blocks for the second hierarchical level, representing the second hierarchical level as the desired number of blocks, each of the blocks having a boundary, and identifying transistor networks that extend across block boundaries. The method further comprises the steps of assigning transistor networks that cross block boundaries into the top hierarchical level to reduce cross boundary transistor networks, and re-assigning some of the transistors among the blocks to reduce the maximum number of transistors in any one block. Preferably, the transistors are assigned from one block to another by identifying partitions for groups of transistors; and then reassigning assigning transistors on the basis of said partitions. For example, the transistors may be partitioned on the basis of functionality, by name, to minimize connectivity, or to duplicate pre-existing hierarchy.

2. 发明授权

US06829755B2 Variable detail automatic invocation of transistor level timing for application specific integrated circuit static timing analysis 失效
标题翻译：可变细节自动调用晶体管级定时，用于专用集成电路静态时序分析
公开(公告)号：US06829755B2
公开(公告)日：2004-12-07
申请号：US09682294
申请日：2001-08-16
申请人： Paul T. Gutwin , Peter J. Osler
发明人： Paul T. Gutwin , Peter J. Osler
IPC分类号： G06F1750
CPC分类号： G06F17/5031
摘要： A method and system for designing static timing analysis for application specific-type integrated circuits (ASIC). The method includes use of transistor level timing (TLT) methods that are used only when open channel circuit inputs are detected during the generation of the timing graph.
摘要翻译：一种用于专用型集成电路（ASIC）的静态时序分析的方法和系统。该方法包括使用晶体管电平定时（TLT）方法，仅在定时图生成期间检测到开放通道电路输入时才使用。

3. 发明授权

US06449693B1 Method and apparatus for improving caching within a processor system 失效
标题翻译：用于改善处理器系统内的缓存的方法和装置
公开(公告)号：US06449693B1
公开(公告)日：2002-09-10
申请号：US09286708
申请日：1999-04-05
申请人： John W. Goetz , Paul T. Gutwin , Stephen W. Mahin , Wilbur D. Pricer
发明人： John W. Goetz , Paul T. Gutwin , Stephen W. Mahin , Wilbur D. Pricer
IPC分类号： G06F1200
CPC分类号： G06F9/3824 , G06F12/0848 , G06F12/0897
摘要： A processor system is provided that comprises a plurality of L0 caches, a processor having a plurality of execution units, and an L1 cache for caching any data and instructions used by the processor. A portion of the execution units provided are configured so that each execution unit within the portion accesses one of the L0 caches. Each of the L0 caches is accessible by only one of the portion of the execution units, and each L0 cache caches a subset of any data used by the processor which is not cacheable by any of the other L0 caches. The processor system preferably comprises an instruction dispatcher that dispatches instructions executable by the processor and that selectively designates data as cacheable by only one of the L0 caches, preferably at dispatch time.
摘要翻译：提供了包括多个L0高速缓存的处理器系统，具有多个执行单元的处理器和用于缓存由处理器使用的任何数据和指令的L1高速缓存。所提供的执行单元的一部分被配置为使得该部分内的每个执行单元访问L0高速缓存之一。每个L0高速缓存只能由执行单元的一部分访问，并且每个L0高速缓存缓存由处理器使用的任何数据的子集，其不能由任何其他L0高速缓存缓存。处理器系统优选地包括指派分派器，其分派由处理器执行的指令，并且优选地在调度时间内，仅通过L0高速缓存中的一个来选择性地指定数据可高速缓存。

4. 发明授权

US06532520B1 Method and apparatus for allocating data and instructions within a shared cache 失效
标题翻译：用于在共享缓存内分配数据和指令的方法和装置
公开(公告)号：US06532520B1
公开(公告)日：2003-03-11
申请号：US09394965
申请日：1999-09-10
申请人： Alvar A. Dean , Marc R. Faucher , John W. Goetz , Kenneth J. Goodnow , Paul T. Gutwin , Stephen W. Mahin , Wilbur D. Pricer
发明人： Alvar A. Dean , Marc R. Faucher , John W. Goetz , Kenneth J. Goodnow , Paul T. Gutwin , Stephen W. Mahin , Wilbur D. Pricer
IPC分类号： G06F1200
CPC分类号： G06F12/121 , G06F12/127 , G06F2212/1021 , G06F2212/6042
摘要： A method and apparatus are provided for managing cache allocation for a plurality of data types in a unified cache having dynamically allocable lines for first type data and for second type data. Cache allocation is managed by counting misses to first type data and misses to second type data in the unified cache, and by determining when a difference between a number of first type data misses and a number of second type data misses crosses a preselected threshold. A replacement algorithm of the unified cache then is adjusted in response to the detected crossing of the preselected threshold, the adjusting step including increasing a replacement priority of the first type data lines in the cache. The replacement algorithm preferably is an LRU algorithm wherein the adjusting step includes incrementing an age indication of the first type data lines. Hardware for implementing the inventive cache allocation management method comprises a miss counter configured to increment its count in response to a miss to first type data signal on a first counter input and to output a first logic state on a first counter output when the counter's count exceeds a first predetermined count. A priority adjustment circuit coupled to the first counter output increases the replacement priority of the first type data relative to the replacement priority of the second type data in response to the first logic state output by the miss counter.
摘要翻译：提供了一种方法和装置，用于管理具有用于第一类型数据和第二类型数据的动态可分配行的统一高速缓存中的多个数据类型的高速缓存分配。高速缓存分配通过对统一高速缓存中的第一类型数据和第二类型数据的丢失进行计数，并且通过确定多个第一类型数据丢失与多个第二类型数据丢失之间的差异何时穿过预选阈值来管理高速缓存分配。然后，响应于检测到的预选阈值的交叉，调整统一高速缓存的替换算法，该调整步骤包括增加高速缓存中的第一类型数据线的替换优先级。替换算法优选地是LRU算法，其中调整步骤包括递增第一类型数据线的年龄指示。用于实现本发明的高速缓存分配管理方法的硬件包括错误计数器，其配置为响应于第一计数器输入上的第一类型数据信号的未命中而增加其计数，并且当计数器的计数超过时，在第一计数器输出上输出第一逻辑状态第一预定计数。耦合到第一计数器输出的优先级调整电路响应于未命中计数器输出的第一逻辑状态，增加第一类型数据相对于第二类型数据的替换优先级的替换优先级。

5. 发明授权

US06178467B1 Microprocessor system requests burstable access to noncacheable memory areas and transfers noncacheable address on a bus at burst mode 失效
标题翻译：微处理器系统要求对不可缓存的存储区进行可突发访问，并在突发模式下在总线上传输非缓冲地址
公开(公告)号：US06178467B1
公开(公告)日：2001-01-23
申请号：US09111611
申请日：1998-07-07
申请人： Marc R. Faucher , Paul T. Gutwin
发明人： Marc R. Faucher , Paul T. Gutwin
IPC分类号： G06F1300
CPC分类号： G06F12/0888
摘要： A method and system for transferring data between a processor and a device residing at a non-cacheable address. The method includes the steps of asserting the non-cacheable address onto an address bus, asserting a first signal indicating that the processor has data ready for burst mode transfer between the processor and a device residing at the non-cacheable address, asserting a second signal indicating that the device is ready for the burst mode transfer, and performing a burst mode transfer of a plurality of bytes between the processor and the non-cacheable address. The method of the invention provides both sequential and non-sequential burst transfer modes. The system of the invention provides a processor, a device, bus control logic, and non-cacheable address logic. The bus control logic and the non-cacheable address logic are configured to implement new semantic meanings for the CACHE# and KEN# signals that eliminate the distinction between cacheable and non-cacheable address space for purposes of allowing burst mode transfers.
摘要翻译：一种用于在处理器和驻留在不可缓存地址的设备之间传送数据的方法和系统。该方法包括以下步骤：将不可缓存地址置于地址总线上，断言指示处理器具有数据准备好的处理器与位于不可缓存地址的设备之间的突发模式传输的第一信号，断言第二信号指示该设备已准备好进行突发模式传输，并且在处理器与不可缓存地址之间执行多个字节的突发模式传输。本发明的方法提供顺序和非顺序突发传送模式。本发明的系统提供处理器，设备，总线控制逻辑和不可缓存地址逻辑。总线控制逻辑和不可缓存地址逻辑被配置为为CACHE＃和KEN＃信号实现新的语义含义，消除了可缓存和不可缓存地址空间之间的区别，以便允许突发模式传输。

6. 发明授权

US5796621A Circuit delay abstraction tool 失效
标题翻译：电路延迟抽象工具
公开(公告)号：US5796621A
公开(公告)日：1998-08-18
申请号：US688936
申请日：1996-07-31
申请人： Peter E. Dudley , Paul T. Gutwin , Gara Pruesse
发明人： Peter E. Dudley , Paul T. Gutwin , Gara Pruesse
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： What is provided is a system and method for reducing the storage requirements for delay networks used in performing timing analysis. A circuit delay network is transformed by processing all the possible hubs of the input pairs which are created from a bipartite delay graph of the circuit. A smaller delay network is formed by iteratively selecting the hub with the largest edge-saving and removing the conflicts from the remaining unselected hubs. The selections continues until there are no longer any unselected hubs. Further processing can occur using the selected hubs as inputs to insure that there are no further layers of hubs. The composite of all selected hubs and any inputs and outputs that do not contained hubs is an abstracted delay model for the circuit which can be efficiently stored. These models are subsequently used to reduce the computational requirements for timing analysis performed on delay networks at a higher level.
摘要翻译：提供的是用于减少用于执行时序分析的延迟网络的存储要求的系统和方法。通过处理从电路的二分延迟图形创建的输入对的所有可能的集线器来变换电路延迟网络。通过迭代地选择具有最大边缘节省并且从剩余的未选择的集线器中消除冲突的集线器来形成较小的延迟网络。选择继续，直到不再有任何未选择的集线器。可以使用所选择的集线器作为输入来进行进一步的处理，以确保没有更多的集线器层。所有选择的集线器和不包含集线器的任何输入和输出的组合是用于可以有效存储的电路的抽象延迟模型。随后，这些模型用于降低在更高级别的延迟网络上执行的时序分析的计算需求。

7. 发明授权

US5239481A Method for measuring pulse distortion 失效
标题翻译：测量脉冲失真的方法
公开(公告)号：US5239481A
公开(公告)日：1993-08-24
申请号：US752394
申请日：1991-08-30
申请人： Thomas W. Brooks , Paul T. Gutwin , Caryn G. Melrose , Frank A. Nemec, Jr. , James J. Tomczak
发明人： Thomas W. Brooks , Paul T. Gutwin , Caryn G. Melrose , Frank A. Nemec, Jr. , James J. Tomczak
IPC分类号： G01R29/027
CPC分类号： G01R29/0273
摘要： A method for measuring pulse distortion in a digital logic design. A digital logic block of interest is divided into its component primary logic functions. The pulse width distortion characteristics are determined for each primary logic function. The pulse width distortion characteristics are used to develop values representing the minimum pulse width required to guarantee full pulse amplitude propagation through each primary logic function. Thus, pulse distortion is characterized in terms of both width and amplitude components. Pulse width distortion for the entire logic block is then determined by following each logic path through the logic block and statistically summing the pulse width distortion characteristics for each occurrence of each primary logic function in the logic path. Pulse amplitude integrity is checked at the input to each primary logic function by referencing the pre-calculated values for minimum pulse width required to guarantee full pulse amplitude propagation through the primary logic function.
摘要翻译：一种用于测量数字逻辑设计中的脉冲失真的方法。感兴趣的数字逻辑块被分为其组成的主要逻辑功能。确定每个主要逻辑功能的脉冲宽度失真特性。脉冲宽度失真特性用于显示表示通过每个主要逻辑功能保证全脉冲幅度传播所需的最小脉冲宽度的值。因此，脉冲失真以宽度和振幅分量为特征。然后通过跟随通过逻辑块的每个逻辑路径来确定整个逻辑块的脉冲宽度失真，并且对逻辑路径中的每个主要逻辑功能的每次出现的脉冲宽度失真特性进行统计学上的求和。在每个主要逻辑功能的输入端检查脉冲幅度完整性，参考通过主要逻辑功能保证全脉冲幅度传播所需的最小脉冲宽度的预先计算值。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式