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    • 1. 发明授权
    • Logical to physical address mapping in storage systems comprising solid state memory devices
    • 在包含固态存储器件的存储系统中的逻辑到物理地址映射
    • US09256527B2
    • 2016-02-09
    • US13812377
    • 2011-07-25
    • Werner BuxRobert HaasXiao-Yu HuRoman Pletka
    • Werner BuxRobert HaasXiao-Yu HuRoman Pletka
    • G06F12/02G06F12/08
    • G06F12/0246G06F12/0848G06F12/0866G06F2212/214G06F2212/221G06F2212/222G06F2212/466G06F2212/7201
    • The present idea provides a high read and write performance from/to a solid state memory device. The main memory of the controller is not blocked by a complete address mapping table covering the entire memory device. Instead such table is stored in the memory device itself, and only selected portions of address mapping information are buffered in the main memory in a read cache and a write cache. A separation of the read cache from the write cache enables an address mapping entry being evictable from the read cache without the need to update the related flash memory page storing such entry in the flash memory device. By this design, the read cache may advantageously be stored on a DRAM even without power down protection, while the write cache may preferably be implemented in nonvolatile or other fail-safe memory. This leads to a reduction of the overall provisioning of nonvolatile or fail-safe memory and to an improved scalability and performance.
    • 本想法提供了从/到固态存储器件的高读/写性能。 控制器的主存储器不被覆盖整个存储器件的完整地址映射表阻止。 相反,这样的表被存储在存储器设备本身中,并且只有地址映射信息的选定部分被缓存在读取高速缓存和写入高速缓存中的主存储器中。 读取高速缓存与写入高速缓存的分离使得能够从读取的高速缓存中取出地址映射条目,而不需要在闪存设备中更新存储这样的条目的相关闪存页面。 通过这种设计,读取高速缓存可以有利地存储在DRAM上,即使没有掉电保护,而写入高速缓存也可以优选地被实现在非易失性或其它故障安全存储器中。 这导致了非易失性或故障安全存储器的总体配置的减少以及改进的可扩展性和性能。
    • 2. 发明申请
    • LOGICAL TO PHYSICAL ADDRESS MAPPING IN STORAGE SYSTEMS COMPRISING SOLID STATE MEMORY DEVICES
    • 在包含固态存储器件的存储系统中逻辑地址映射
    • US20130124794A1
    • 2013-05-16
    • US13812377
    • 2011-07-25
    • Werner BuxRobert HaasXiao-Yu HuRoman Pletka
    • Werner BuxRobert HaasXiao-Yu HuRoman Pletka
    • G06F12/02
    • G06F12/0246G06F12/0848G06F12/0866G06F2212/214G06F2212/221G06F2212/222G06F2212/466G06F2212/7201
    • The present idea provides a high read and write performance from/to a solid state memory device. The main memory of the controller is not blocked by a complete address mapping table covering the entire memory device. Instead such table is stored in the memory device itself, and only selected portions of address mapping information are buffered in the main memory in a read cache and a write cache. A separation of the read cache from the write cache enables an address mapping entry being evictable from the read cache without the need to update the related flash memory page storing such entry in the flash memory device. By this design, the read cache may advantageously be stored on a DRAM even without power down protection, while the write cache may preferably be implemented in nonvolatile or other fail-safe memory. This leads to a reduction of the overall provisioning of nonvolatile or fail-safe memory and to an improved scalability and performance.
    • 本想法提供了从/到固态存储器件的高读/写性能。 控制器的主存储器不被覆盖整个存储器件的完整地址映射表阻止。 相反,这样的表被存储在存储器设备本身中,并且只有地址映射信息的选定部分被缓存在读取高速缓存和写入高速缓存中的主存储器中。 读取高速缓存与写入高速缓存的分离使得能够从读取的高速缓存中取出地址映射条目,而不需要在闪存设备中更新存储这样的条目的相关闪存页面。 通过这种设计,读取高速缓存可以有利地存储在DRAM上,即使没有掉电保护,而写入高速缓存也可以优选地被实现在非易失性或其它故障安全存储器中。 这导致了非易失性或故障安全存储器的总体配置的减少以及改进的可扩展性和性能。