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1. 发明授权

US08495258B2 Implementing storage adapter performance optimization with hardware accelerators offloading firmware for buffer allocation and automatically DMA 失效
标题翻译：实现存储适配器性能优化与硬件加速器卸载固件的缓冲区分配和自动DMA
公开(公告)号：US08495258B2
公开(公告)日：2013-07-23
申请号：US13114124
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A method and controller for implementing storage adapter performance optimization with automatic chained hardware operations eliminating firmware operations, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines and a control store configured to store a plurality of control blocks. Each control block is designed to control a hardware operation in one of the plurality of hardware engines. A plurality of the control blocks is selectively arranged in a respective predefined chain to define sequences of hardware operations. An automatic hardware structure is configured to build the respective predefined chain controlling the hardware operations for a predefined hardware function. The predefined hardware function includes buffer allocation and automatic DMA data from a host system to the controller for write operations, eliminating firmware operations.
摘要翻译：一种用于实现存储适配器性能优化的方法和控制器，其具有消除固件操作的自动链接硬件操作以及提供主题控制器电路所在的设计结构。控制器包括多个硬件引擎和被配置为存储多个控制块的控制存储器。每个控制块被设计成控制多个硬件引擎之一的硬件操作。多个控制块被选择性地布置在相应的预定链中以定义硬件操作的顺序。自动硬件结构被配置为构建控制用于预定义硬件功能的硬件操作的相应预定义链。预定义的硬件功能包括从主机系统到控制器的写入操作的缓冲区分配和自动DMA数据，从而消除了固件操作。

2. 发明申请

US20130046930A1 OPTIMIZING LOCATIONS OF DATA ACCESSED BY CLIENT APPLICATIONS INTERACTING WITH A STORAGE SYSTEM 有权
标题翻译：优化客户应用程序访问数据的位置与存储系统交互
公开(公告)号：US20130046930A1
公开(公告)日：2013-02-21
申请号：US13606932
申请日：2012-09-07
申请人： Evangelos S. Eleftheriou , Robert Galbraith , Adrian C. Gerhard , Robert Haas , Xiao-Yu Hu , Murali N. Iyer , Ioannis Koltsidas , Timothy J. Larson , Steven P. Norgaard , Roman Pletka
发明人： Evangelos S. Eleftheriou , Robert Galbraith , Adrian C. Gerhard , Robert Haas , Xiao-Yu Hu , Murali N. Iyer , Ioannis Koltsidas , Timothy J. Larson , Steven P. Norgaard , Roman Pletka
IPC分类号： G06F12/08
CPC分类号： G06F11/1076 , G06F3/061 , G06F3/0662 , G06F3/0685
摘要： A method for optimizing locations of physical data accessed by one or more client applications interacting with a storage system, with the storage system comprising at least two redundancy groups having physical memory spaces and data bands. Each of the data bands corresponds to physical data stored on several of the physical memory spaces. A virtualized logical address space includes client data addresses utilizable by the one or more client applications. A storage controller is configured to map the client data addresses onto the data bands, such that a mapping is obtained, wherein the one or more client applications can access physical data corresponding to the data bands.
摘要翻译：一种用于优化由与存储系统交互的一个或多个客户端应用访问的物理数据的位置的方法，其中所述存储系统包括具有物理存储器空间和数据带的至少两个冗余组。每个数据带对应于存储在几个物理存储器空间上的物理数据。虚拟化逻辑地址空间包括由一个或多个客户端应用程序可使用的客户机数据地址。存储控制器被配置为将客户端数据地址映射到数据带上，使得获得映射，其中一个或多个客户端应用可以访问对应于数据带的物理数据。

3. 发明申请

US20120303883A1 IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH CACHE DATA/DIRECTORY MIRRORING 有权
标题翻译：使用缓存数据/目录映射实现存储适配器性能优化
公开(公告)号：US20120303883A1
公开(公告)日：2012-11-29
申请号：US13114185
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/00 , G06F11/108 , G06F11/2071 , G06F12/08 , G06F12/0868 , G06F2211/1009 , G06F2211/1059 , G06F2212/1016 , G06F2212/225 , G06F2212/286
摘要： A method and controller for implementing storage adapter performance optimization with cache data and cache directory mirroring between dual adapters minimizing firmware operations, and a design structure on which the subject controller circuit resides are provided. One of the first controller or the second controller operates in a first initiator mode includes firmware to set up an initiator write operation building a data frame for transferring data and a respective cache line (CL) for each page index to the other controller operating in a second target mode. Respective initiator hardware engines transfers data, reading CLs from an initiator control store, and writing updated CLs to an initiator data store, and simultaneously sends data and updated CLs to the other controller. Respective target hardware engines write data and updated CLs to the target data store, eliminating firmware operations of the controller operating in the second target mode.
摘要翻译：一种用于实现存储适配器性能优化的方法和控制器，其中缓存数据和双重适配器之间的缓存目录镜像最小化固件操作，以及提供主题控制器电路所在的设计结构。第一控制器或第二控制器中的一个以第一启动器模式操作，包括固件，用于建立向每个页索引建立数据帧的启动器写入操作和用于每个页索引的相应高速缓存行（CL）到另一控制器第二目标模式。各发起者硬件引擎传送数据，从启动器控制存储器读取CL，并将更新后的CL写入发起者数据存储器，同时向其他控制器发送数据和更新的CL。各个目标硬件引擎将数据和更新的CL写入目标数据存储，消除了在第二目标模式下操作的控制器的固件操作。

4. 发明申请

US20120297272A1 IMPLEMENTING ENHANCED IO DATA CONVERSION WITH PROTECTION INFORMATION MODEL INCLUDING PARITY FORMAT OF DATA INTEGRITY FIELDS 有权
标题翻译：实施具有保护信息模型的增强IO数据转换，包括数据完整性字段的特殊格式
公开(公告)号：US20120297272A1
公开(公告)日：2012-11-22
申请号：US13108097
申请日：2011-05-16
申请人： Brian E. Bakke , Robert E. Galbraith , Adrian C. Gerhard , Daniel F. Moertl , Rick A. Weckwerth
发明人： Brian E. Bakke , Robert E. Galbraith , Adrian C. Gerhard , Daniel F. Moertl , Rick A. Weckwerth
IPC分类号： G06F11/20
CPC分类号： G06F11/1076
摘要： A method and controller for implementing enhanced input/output (IO) data conversion with an enhanced protection information model including an enhanced parity format of the data integrity fields (DIF), and a design structure on which the subject controller circuit resides are provided. The controller implements a protection information model including a unique parity data integrity fields (DIF) format. The unique parity DIF format enables corruption detection for RAID parity blocks. The unique parity DIF format includes a predefined size for a protection information model logical block guard cyclic redundancy check (CRC) field and a logical block Reference Tag (RT) field. A plurality of storage devices in a RAID configuration are coupled to the controller, and configured to store data and RAID parity redundancy data, and wherein a strength of RAID parity redundancy data is not reduced when a loss of a single storage device in the plurality of storage devices occurs.
摘要翻译：一种用于通过增强的保护信息模型实现增强的输入/输出（IO）数据转换的方法和控制器，该增强的保护信息模型包括数据完整性字段（DIF）的增强的奇偶校验格式，以及提供了对象控制器电路所在的设计结构。控制器实现包括唯一奇偶校验数据完整性字段（DIF）格式的保护信息模型。唯一的奇偶校验DIF格式可以对RAID奇偶校验块进行故障检测。唯一奇偶校验DIF格式包括用于保护信息模型逻辑块保护循环冗余校验（CRC）字段和逻辑块参考标签（RT）字段的预定义大小。 RAID配置中的多个存储设备被耦合到控制器，并且被配置为存储数据和RAID奇偶校验冗余数据，并且其中当多个存储设备中的单个存储设备的丢失时，RAID奇偶校验冗余数据的强度不会降低存储设备发生。

5. 发明授权

US08661196B2 Optimizing locations of data accessed by client applications interacting with a storage system 有权
标题翻译：优化与存储系统交互的客户端应用程序访问的数据的位置
公开(公告)号：US08661196B2
公开(公告)日：2014-02-25
申请号：US13209514
申请日：2011-08-15
申请人： Evangelos S. Eleftheriou , Robert Galbraith , Adrian C. Gerhard , Robert Haas , Xiao-Yu Hu , Murali N. Iyer , Ioannis Koltsidas , Timothy J. Larson , Steven P. Norgaard , Roman Pletka
发明人： Evangelos S. Eleftheriou , Robert Galbraith , Adrian C. Gerhard , Robert Haas , Xiao-Yu Hu , Murali N. Iyer , Ioannis Koltsidas , Timothy J. Larson , Steven P. Norgaard , Roman Pletka
IPC分类号： G06F12/00
CPC分类号： G06F11/1076 , G06F3/061 , G06F3/0662 , G06F3/0685
摘要： A method for optimizing locations of physical data accessed by one or more client applications interacting with a storage system, with the storage system comprising at least two redundancy groups having physical memory spaces and data bands. Each of the data bands corresponds to physical data stored on several of the physical memory spaces. A virtualized logical address space includes client data addresses utilizable by the one or more client applications. A storage controller is configured to map the client data addresses onto the data bands, such that a mapping is obtained, wherein the one or more client applications can access physical data corresponding to the data bands.
摘要翻译：一种用于优化由与存储系统交互的一个或多个客户端应用访问的物理数据的位置的方法，其中所述存储系统包括具有物理存储器空间和数据带的至少两个冗余组。每个数据带对应于存储在几个物理存储器空间上的物理数据。虚拟化逻辑地址空间包括由一个或多个客户端应用程序可使用的客户机数据地址。存储控制器被配置为将客户端数据地址映射到数据带上，使得获得映射，其中一个或多个客户端应用可以访问对应于数据带的物理数据。

6. 发明授权

US08656213B2 Implementing storage adapter performance optimization with chained hardware operations and error recovery firmware path 失效
标题翻译：通过链接的硬件操作和错误恢复固件路径实现存储适配器性能优化
公开(公告)号：US08656213B2
公开(公告)日：2014-02-18
申请号：US13114354
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F11/00
CPC分类号： G06F11/0727 , G06F3/061 , G06F3/0658 , G06F3/0659 , G06F3/0689 , G06F11/0793
摘要： A method and controller for implementing storage adapter performance optimization with a predefined chain of hardware operations configured to minimize hardware and firmware interactions and a bridge code configured to select a firmware sequence for error recovery to complete the operations responsive to an identified error in the predefined chain, and a design structure on which the subject controller circuit resides are provided. A selected predefined chain is configured to implement a particular performance path to maximize performance. Responsive to an identified predefined error during hardware operations in the predefined hardware chain, a bridge code is configured to select a non-performance path firmware sequence for error recovery completion of remaining operations.
摘要翻译：一种用于利用预定义的硬件操作链来实现存储适配器性能优化的方法和控制器，其被配置为最小化硬件和固件交互以及配置成选择用于错误恢复的固件序列的桥接代码，以响应于所述预定链中的所识别的错误来完成操作，并且设置有主体控制器电路所在的设计结构。所选择的预定义链被配置为实现特定的性能路径以最大化性能。响应于在预定义硬件链中的硬件操作期间识别的预定义错误，桥接代码被配置为选择用于其余操作的错误恢复完成的非性能路径固件序列。

7. 发明授权

US08544029B2 Implementing storage adapter performance optimization with chained hardware operations minimizing hardware/firmware interactions 有权
标题翻译：通过链接的硬件操作实现存储适配器性能优化，从而最大限度地减少硬件/固件交互
公开(公告)号：US08544029B2
公开(公告)日：2013-09-24
申请号：US13114107
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F9/44 , G06F13/28
CPC分类号： G06F3/0611 , G06F3/0656 , G06F3/0689
摘要： A method and controller for implementing storage adapter performance optimization with chained hardware operations minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and one or more processors. An event queue is coupled to at least one processor notifying the processor of a plurality of predefined events. A control block is designed to control an operation in one of the plurality of hardware engines including the hardware engine writing an event queue entry. A plurality of the control blocks are selectively arranged in a predefined chain to minimize the hardware engine writing event queue entries to the processor.
摘要翻译：一种用于实现存储适配器性能优化的方法和控制器，其具有最小化硬件和固件交互的链接硬件操作，以及提供主题控制器电路所在的设计结构。控制器包括多个硬件引擎; 和一个或多个处理器。事件队列被耦合到至少一个处理器通知多个预定义事件的处理器。控制块被设计成控制多个硬件引擎中的一个的操作，包括写入事件队列条目的硬件引擎。多个控制块被选择性地布置在预定义的链中以最小化硬件引擎将事件队列条目写入处理器。

8. 发明申请

US20120304001A1 IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH CHAINED HARDWARE OPERATIONS AND ERROR RECOVERY FIRMWARE PATH 失效
标题翻译：实施存储适配器性能优化与链接硬件操作和错误恢复固件路径
公开(公告)号：US20120304001A1
公开(公告)日：2012-11-29
申请号：US13114354
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F11/20
CPC分类号： G06F11/0727 , G06F3/061 , G06F3/0658 , G06F3/0659 , G06F3/0689 , G06F11/0793
摘要： A method and controller for implementing storage adapter performance optimization with a predefined chain of hardware operations configured to minimize hardware and firmware interactions and a bridge code configured to select a firmware sequence for error recovery to complete the operations responsive to an identified error in the predefined chain, and a design structure on which the subject controller circuit resides are provided. A selected predefined chain is configured to implement a particular performance path to maximize performance. Responsive to an identified predefined error during hardware operations in the predefined hardware chain, a bridge code is configured to select a non-performance path firmware sequence for error recovery completion of remaining operations.
摘要翻译：一种用于利用预定义的硬件操作链来实现存储适配器性能优化的方法和控制器，其被配置为最小化硬件和固件交互以及配置成选择用于错误恢复的固件序列的桥接代码，以响应于所述预定链中的所识别的错误来完成操作，并且设置有主体控制器电路所在的设计结构。所选择的预定义链被配置为实现特定的性能路径以最大化性能。响应于在预定义硬件链中的硬件操作期间识别的预定义错误，桥接代码被配置为选择用于其余操作的错误恢复完成的非性能路径固件序列。

9. 发明申请

US20120303922A1 IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH ENHANCED RESOURCE POOL ALLOCATION 有权
标题翻译：实施存储适配器性能优化与增强资源池分配
公开(公告)号：US20120303922A1
公开(公告)日：2012-11-29
申请号：US13114427
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F12/02
CPC分类号： G06F3/0617 , G06F3/0631 , G06F3/0689
摘要： A method and controller for implementing storage adapter performance optimization with enhanced resource pool allocation, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; a processor, and a plurality of resource pools. A plurality of work queues is associated with the resource pools. The processor initializes a list of types, and the associated amount of pages for each allocate type. The hardware engines maintain a count of allocate types, specifying a type on each allocation and deallocation, and performing allocation from the resource pools for deadlock avoidance.
摘要翻译：一种用于实现具有增强的资源池分配的存储适配器性能优化的方法和控制器，以及提供了主题控制器电路所在的设计结构。控制器包括多个硬件引擎; 处理器和多个资源池。多个工作队列与资源池相关联。处理器初始化类型列表，以及每种分配类型的相关联的页面数量。硬件引擎维护分配类型的计数，指定每个分配和解除分配的类型，并从资源池执行死锁避免的分配。

10. 发明申请

US20100262868A1 Managing Possibly Logically Bad Blocks in Storage Devices 有权
标题翻译：在存储设备中管理逻辑错误的块
公开(公告)号：US20100262868A1
公开(公告)日：2010-10-14
申请号：US12421671
申请日：2009-04-10
申请人： Robert E. Galbraith , Adrian C. Gerhard , Daniel F. Moertl
发明人： Robert E. Galbraith , Adrian C. Gerhard , Daniel F. Moertl
IPC分类号： G06F11/00 , G06F11/16
CPC分类号： G06F11/1092 , G06F2211/1057 , G06F2211/1059
摘要： If data is lost a possibly logically bad pattern is placed in a standard size data block in a storage device, and the Logical Block Address associated with the data block is inserted in a Bad Block Table. The possibly logically bad pattern is able to be detected, and the Bad Block Table is checked to determine if the data block to be read is in fact Logically Bad. A data check response may be given to a host if a Logical Block Address associated with the standard size data block is present in a Bad Block Table. The possibly logically bad pattern may have a first predefined data portion and a second predefined data portion and may be repeated the requisite number of instances to fill the standard size data block.
摘要翻译：如果数据丢失，则存储设备中的标准尺寸数据块中可能存在逻辑上不良的模式，并且将与数据块相关联的逻辑块地址插入到坏块表中。可以检测到可能的逻辑不良图案，并且检查坏块表以确定要读取的数据块是否实际上是逻辑不良的。如果与标准尺寸数据块相关联的逻辑块地址存在于坏块表中，则可向主机提供数据检查响应。可能逻辑上不良的图案可以具有第一预定义数据部分和第二预定义数据部分，并且可以重复必需数量的实例以填充标准尺寸数据块。

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