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1. 发明授权

US06363013B1 Auto-stopped page soft-programming method with voltage limited component 有权
标题翻译：具有电压限制的自动停止页面软编程方法
公开(公告)号：US06363013B1
公开(公告)日：2002-03-26
申请号：US09652230
申请日：2000-08-29
申请人： Wenpin Lu , Ying-Che Lo , Ming-Shang Chen , Baw-Chyuan Lin , Chun-Lien Su
发明人： Wenpin Lu , Ying-Che Lo , Ming-Shang Chen , Baw-Chyuan Lin , Chun-Lien Su
IPC分类号： G11C1604
CPC分类号： G11C16/12
摘要： Method for soft-programming at least one floating gate memory cell in at least one page of a persistent memory device by converging the low threshold voltages of the several cells of the page within an optimal range, and apparatus implementing the method. The methodology of the present invention teaches connecting the individual drains of the several memory cells of the device of a given page, or block, to a voltage limited constant current circuitry component. The methodology applies a first positive voltage to the word line of the page and a second positive voltage to the common source in a fixed time period to converge the pages low threshold voltage distribution. The methodology is capable of implementation on either the source or drain side of the memory array.
摘要翻译：用于通过将页面的几个单元的低阈值电压收敛在最佳范围内来软编程永久存储器件的至少一页中的至少一个浮动栅极存储单元的方法，以及实现该方法的装置。本发明的方法教导了将给定页面或块的装置的多个存储器单元的各个漏极连接到电压限制恒流电路部件。该方法在固定时间段内将第一正电压施加到页的字线和第二正电压到公共源，以使页低收集阈值电压分布。该方法能够在存储器阵列的源极或漏极侧实现。

2. 发明授权

US06614687B2 Current source component with process tracking characteristics for compact programmed Vt distribution of flash EPROM 有权
标题翻译：具有过程跟踪特性的电流源组件用于闪存EPROM的紧凑编程Vt分布
公开(公告)号：US06614687B2
公开(公告)日：2003-09-02
申请号：US09848786
申请日：2001-05-03
申请人： Ming-Shang Chen , Wenpin Lu , Baw-Chyuan Lin , Mam-Tsung Wang
发明人： Ming-Shang Chen , Wenpin Lu , Baw-Chyuan Lin , Mam-Tsung Wang
IPC分类号： G11C1134
CPC分类号： G11C16/12 , G11C11/5628 , G11C2211/565
摘要： A new structure and method with a process tracking current source component to program a flash EPROM memory is proposed. By applying a current source which varies not only with the process variation but also with the source bias of the cell being programmed, a self-convergent and high-efficiency programming can be achieved. This process tracking current source component provides less current for cells with higher erased Vt and larger current for cells with lower erased Vt. A circuit for programming a floating gate transistor includes a current source component. The current source component couples in series between the floating gate transistor and an electrical sink during a programming interval. The current source component includes an electrical characteristic substantially matching the electrical characteristic of the floating gate transistor. An integrated circuit memory module on a semiconductor substrate is disclosed. The integrated circuit memory module includes: an array of floating gate memory cells, decoders, and a plurality of current source components. The array of floating gate memory cells is arranged in M rows and N columns. The decoders couple to the M rows and N columns of memory cells to provide for reading and programming floating gate memory cells within a selected one of the M rows of the memory array. The plurality of current source components each couple in series between an electrical sink and a corresponding one of the floating gate memory cells within the selected one of the M rows during a programming interval. Each of the plurality of current source components includes an electrical characteristic substantially matching the electrical characteristic of the corresponding one of the floating gate memory cells to be programmed.
摘要翻译：提出了一种具有过程跟踪电流源组件来编程闪存EPROM存储器的新结构和方法。通过应用电流源，其不仅随工艺变化而变化，而且随着被编程的电池的源偏置而变化，可以实现自收敛和高效率的编程。该过程跟踪电流源组件为具有较高擦除Vt的电池的电池提供更少的电流，并且具有较低擦除Vt的电池的电流较小。用于编程浮动栅晶体管的电路包括电流源组件。在编程间隔期间，电流源元件串联耦合在浮栅晶体管和电汇之间。电流源组件包括基本上与浮栅晶体管的电特性匹配的电特性。公开了半导体衬底上的集成电路存储器模块。集成电路存储器模块包括：浮动栅极存储器单元，解码器和多个电流源组件的阵列。浮栅存储单元的阵列排列成M行N列。解码器耦合到存储器单元的M行和N列，以提供在存储器阵列的M行中选定的一个中的读取和编程浮动栅极存储器单元。在编程间隔期间，多个电流源分量各自串联在电汇与所选择的M行之一内的浮动栅极存储单元中的对应的一个浮动栅极存储单元之间。多个电流源组件中的每一个包括基本上匹配要编程的浮动栅极存储单元中的相应一个的电特性的电特性。

3. 发明授权

US6166955A Apparatus and method for programming of flash EPROM memory 有权
标题翻译：闪存EPROM存储器编程的装置和方法
公开(公告)号：US6166955A
公开(公告)日：2000-12-26
申请号：US350862
申请日：1999-07-09
申请人： Wenpin Lu , Ming-Shang Chen , Mam-Tsung Wang , Baw-Chyuan Lin
发明人： Wenpin Lu , Ming-Shang Chen , Mam-Tsung Wang , Baw-Chyuan Lin
IPC分类号： G11C16/04 , G11C16/12
CPC分类号： G11C16/0416 , G11C16/12
摘要： An apparatus for programming selected floating gate storage transistors in a data storage device includes a voltage supply circuit, coupled to the control gate and the source of a selected floating gate storage transistor, to supply a gate programming potential across the control gate and the source to move charge in the floating gate. Circuitry, coupled to the selected floating gate storage transistor, maintains drain current of the selected floating gate transistor at a substantially stable value during programming. In one example, the circuitry is a stable current source in parallel with a load coupled to the source of the selected floating gate transistor. The stable current source, in one embodiment, is a current mirror designed to supply a fixed current level. The load may be a resistor chosen to control a slope of a curve of source current versus source voltage such that drain current variation is limited. The load may be a diode chosen to control a slope of a curve of source current versus source voltage such that drain current variation is limited.
摘要翻译：一种用于在数据存储设备中编程所选择的浮置栅极存储晶体管的装置包括耦合到所述控制栅极和所选择的浮置栅极存储晶体管的源极的电压供应电路，以将控制栅极和源极的栅极编程电位提供给在浮动门上移动电荷。耦合到所选择的浮栅存储晶体管的电路在编程期间将所选择的浮栅晶体管的漏极电流保持在基本上稳定的值。在一个示例中，电路是与耦合到所选择的浮置栅极晶体管的源极的负载并联的稳定电流源。在一个实施例中，稳定电流源是设计成提供固定电流电平的电流镜。负载可以是被选择用于控制源电流与电源电压的曲线的斜率的电阻器，使得漏极电流变化受到限制。负载可以是被选择用于控制源电流与源电压的曲线的斜率的二极管，使得漏极电流变化受到限制。

4. 发明授权

US5912845A Method and circuit for substrate current induced hot e.sup.- injection (SCIHE) approach for V.sub.T convergence at low V.sub.CC voltage 失效
标题翻译：用于在低VCC电压下VT收敛的衬底电流感应热电子注入（SCIHE）方法和电路
公开(公告)号：US5912845A
公开(公告)日：1999-06-15
申请号：US926554
申请日：1997-09-10
申请人： Chia-Shing Chen , Mam-Tsung Wang , Wenpin Lu , Ming-Hung Chou , Ying-Che Lo , Ming-Shang Chen
发明人： Chia-Shing Chen , Mam-Tsung Wang , Wenpin Lu , Ming-Hung Chou , Ying-Che Lo , Ming-Shang Chen
IPC分类号： G11C16/34 , G11C16/04
CPC分类号： G11C16/107 , G11C16/3404 , G11C16/3409 , G11C16/3445
摘要： A method for soft programming memory cells and floating gate memory device. During soft programming, a gate voltage is supplied to the control gate, a drain voltage it supplied to the drain, a well voltage is supplied to the well, and an active current limiter is coupled to the source. A circuit for soft programming supplies a gate voltage to the control gate, couples a constant current source to the drain, supplies a well voltage to the well, and supplies a source voltage to the source. The gate voltage may be approximately 2 V, the drain voltage may be approximately 4 V, and the well voltage may be approximately -2 V. According to another embodiment of the invention, the gate voltage is approximately 2 V lower than the drain voltage, and the well voltage is approximately 4 V lower than the gate voltage.
摘要翻译：一种用于软编程存储单元和浮动栅极存储器件的方法。在软编程期间，向控制栅极提供栅极电压，将其提供给漏极的漏极电压，将阱电压提供给阱，并且有源限流器耦合到源极。用于软编程的电路向控制栅极提供栅极电压，将恒定电流源耦合到漏极，将阱电压提供给阱，并将源电压提供给源极。栅极电压可以为约2V，漏极电压可以为约4V，并且阱电压可以为约-2V。根据本发明的另一实施例，栅极电压比漏极电压低约2V，并且阱电压比栅极电压低约4V。

5. 发明授权

US6031766A Method and circuit for substrate current induced hot e-injection (SCIHE) approach for V.sub.T convergence at low V.sub.cc voltage 有权
标题翻译：用于在低Vcc电压下VT收敛的衬底电流感应热电子注入（SCIHE）方法和电路
公开(公告)号：US6031766A
公开(公告)日：2000-02-29
申请号：US289697
申请日：1999-04-09
申请人： Chia-Shing Chen , Mam-Tsung Wang , Wenpin Lu , Ming-Hung Chou , Ying-Che Lo , Ming-Shang Chen
发明人： Chia-Shing Chen , Mam-Tsung Wang , Wenpin Lu , Ming-Hung Chou , Ying-Che Lo , Ming-Shang Chen
IPC分类号： G11C16/34 , G11C16/04
CPC分类号： G11C16/107 , G11C16/3404 , G11C16/3409 , G11C16/3445
摘要： A method for soft programming memory cells and floating gate memory device. During soft programming, a gate voltage is supplied to the control gate, a drain voltage it supplied to the drain, a well voltage is supplied to the well, and an active current limiter is coupled to the source. A circuit for soft programming supplies a gate voltage to the control gate, couples a constant current source to the drain, supplies a well voltage to the well, and supplies a source voltage to the source. The gate voltage may be approximately 2 V, the drain voltage may be approximately 4 V, and the well voltage may be approximately -2 V. According to another embodiment of the invention, the gate voltage is approximately 2 V lower than the drain voltage, and the well voltage is approximately 4 V lower than the gate voltage.
摘要翻译：一种用于软编程存储单元和浮动栅极存储器件的方法。在软编程期间，向控制栅极提供栅极电压，将其提供给漏极的漏极电压，将阱电压提供给阱，并且有源限流器耦合到源极。用于软编程的电路向控制栅极提供栅极电压，将恒定电流源耦合到漏极，将阱电压提供给阱，并将源电压提供给源极。栅极电压可以为约2V，漏极电压可以为约4V，并且阱电压可以为约-2V。根据本发明的另一实施例，栅极电压比漏极电压低约2V，并且阱电压比栅极电压低约4V。

6. 发明授权

US06723646B2 Method for controlling and monitoring a chemical mechanical polishing process 有权
标题翻译：控制和监测化学机械抛光工艺的方法
公开(公告)号：US06723646B2
公开(公告)日：2004-04-20
申请号：US10054962
申请日：2002-01-25
申请人： Chun-Lien Su , Chi-Yuan Chin , Shih-Keng Cho , Ming-Shang Chen , Yih-Shi Lin
发明人： Chun-Lien Su , Chi-Yuan Chin , Shih-Keng Cho , Ming-Shang Chen , Yih-Shi Lin
IPC分类号： H01L21302
CPC分类号： H01L22/34 , H01L21/31053 , H01L21/76819
摘要： The present invention relates a method of controlling and monitoring the thickness variation of the film structure of a semiconductor wafer by monitoring the thickness variation of the film structure of a testing region. The method is characterized by etching the film structure of the testing region with a pattern density substantially compatible with that of the device region in order to precisely simulate the thickness variation of the film structure of a device region in a chemical mechanical polishing process.
摘要翻译：本发明涉及通过监测测试区域的膜结构的厚度变化来控制和监测半导体晶片的膜结构的厚度变化的方法。该方法的特征在于以与器件区域基本相容的图案密度蚀刻测试区域的膜结构，以精确地模拟化学机械抛光工艺中的器件区域的膜结构的厚度变化。

7. 发明授权

US06620714B2 Method for reducing oxidation encroachment of stacked gate layer 有权
标题翻译：减少层叠栅层氧化侵蚀的方法
公开(公告)号：US06620714B2
公开(公告)日：2003-09-16
申请号：US10043147
申请日：2002-01-14
申请人： Chun-Lien Su , Chun-Chi Wang , Ming-Shang Chen
发明人： Chun-Lien Su , Chun-Chi Wang , Ming-Shang Chen
IPC分类号： H01L213205
CPC分类号： H01L27/11521 , H01L21/26506 , H01L21/26586 , H01L21/28247 , H01L21/28273 , H01L27/115
摘要： A method for reducing oxidation encroachment of stacked gate layer is provided by forming a silicon oxynitride layer on the sidewall surface of the stacked gate layer. A tilted ion implantation step is performed to implant nitrogen ions into the sidewall surface of the stacked gate layer to rich nitrogen containing in the sidewall surface of the stacked gate layer. An oxygen-annealing step is subsequently performed to form a silicon oxynitride layer on the sidewall surface of the stacked gate layer. The silicon oxynitride layer can prevent the polysilicon layer in the stacked gate layer being continuously encroached from the oxygen.
摘要翻译：通过在堆叠的栅极层的侧壁表面上形成氧氮化硅层来提供减少层叠栅极层的氧化侵蚀的方法。进行倾斜离子注入步骤，以将氮离子注入层叠栅极层的侧壁表面，从而在堆叠的栅极层的侧壁表面中含有富含氮。随后进行氧退火步骤以在堆叠的栅极层的侧壁表面上形成氧氮化硅层。氧氮化硅层可以防止层叠栅极层中的多晶硅层从氧气中连续侵入。

8. 发明申请

US20070269947A1 Method for manufacturing NAND flash memory 有权
标题翻译：制造NAND闪存的方法
公开(公告)号：US20070269947A1
公开(公告)日：2007-11-22
申请号：US11435459
申请日：2006-05-16
申请人： Kuei-Yun Chen , Chun-Lien Su , Yin-Jen Chen , Ming-Shang Chen
发明人： Kuei-Yun Chen , Chun-Lien Su , Yin-Jen Chen , Ming-Shang Chen
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521
摘要： A method for manufacturing a NAND flash memory is provided. First, a substrate is provided. Next, a tunneling dielectric layer, a first conductive layer and a mask layer are sequentially formed on the substrate. Next, a plurality of isolation structures is formed in the mask layer, the first conductive layer, the tunneling dielectric layer and the substrate. Next, the mask layer is removed, so that the top surface of each isolation structure is higher than that of the first conductive layer. Next, a second conductive layer is formed on the exposed sidewalls of the isolation structures. Next, an inter-gate dielectric layer and a third conductive layer are sequentially formed on the substrate.
摘要翻译：提供一种制造NAND闪速存储器的方法。首先，提供基板。接下来，在衬底上依次形成隧穿介质层，第一导电层和掩模层。接下来，在掩模层，第一导电层，隧道电介质层和基板中形成多个隔离结构。接下来，去除掩模层，使得每个隔离结构的顶表面高于第一导电层的顶表面。接下来，在隔离结构的暴露的侧壁上形成第二导电层。接下来，在衬底上依次形成栅极间电介质层和第三导电层。

9. 发明授权

US07592036B2 Method for manufacturing NAND flash memory 有权
标题翻译：制造NAND闪存的方法
公开(公告)号：US07592036B2
公开(公告)日：2009-09-22
申请号：US11435459
申请日：2006-05-16
申请人： Kuei-Yun Chen , Chun-Lien Su , Yin-Jen Chen , Ming-Shang Chen
发明人： Kuei-Yun Chen , Chun-Lien Su , Yin-Jen Chen , Ming-Shang Chen
IPC分类号： B05D5/12
CPC分类号： H01L27/115 , H01L27/11521
摘要： A method for manufacturing a NAND flash memory is provided. First, a substrate is provided. Next, a tunneling dielectric layer, a first conductive layer and a mask layer are sequentially formed on the substrate. Next, a plurality of isolation structures is formed in the mask layer, the first conductive layer, the tunneling dielectric layer and the substrate. Next, the mask layer is removed, so that the top surface of each isolation structure is higher than that of the first conductive layer. Next, a second conductive layer is formed on the exposed sidewalls of the isolation structures. Next, an inter-gate dielectric layer and a third conductive layer are sequentially formed on the substrate.
摘要翻译：提供一种制造NAND闪速存储器的方法。首先，提供基板。接下来，在衬底上依次形成隧穿介质层，第一导电层和掩模层。接下来，在掩模层，第一导电层，隧道电介质层和基板中形成多个隔离结构。接下来，去除掩模层，使得每个隔离结构的顶表面高于第一导电层的顶表面。接下来，在隔离结构的暴露的侧壁上形成第二导电层。接下来，在衬底上依次形成栅极间电介质层和第三导电层。

10. 发明授权

US06677211B2 Method for eliminating polysilicon residue 有权
标题翻译：消除多晶硅残渣的方法
公开(公告)号：US06677211B2
公开(公告)日：2004-01-13
申请号：US10043144
申请日：2002-01-14
申请人： Chun-Lien Su , Chun-Chi Wang , Ming-Shang Chen
发明人： Chun-Lien Su , Chun-Chi Wang , Ming-Shang Chen
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L21/28123 , H01L21/3211 , H01L21/32155 , H01L21/76888 , H01L21/76895 , H01L27/115
摘要： A method for eliminating polysilicon residue is provided by converting the polysilicon residue into silicon nitride in two steps. A tilted ion implantation step is performed to implant nitrogen ions into the polysilicon residue to rich nitrogen containing of the polysilicon residue. A nitrogen anneal step is subsequently performed to completely convert the rich nitrogen containing polysilicon residue into silicon nitride that can eliminate the conductivity of the polysilicon residue and prevent conventional oxygen encroachment occurring.
摘要翻译：通过两步来将多晶硅残渣转化为氮化硅来提供消除多晶硅残渣的方法。进行倾斜离子注入步骤以将氮离子注入到多晶硅残渣中以富含多晶硅残渣的氮。随后进行氮退火步骤以将富含氮的多晶硅残留物完全转化成氮化硅，其可以消除多晶硅残余物的导电性并防止发生常规的氧侵蚀。

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