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1. 发明授权

US07002177B2 Test region layout for shallow trench isolation 失效
标题翻译：浅沟槽隔离测试区域布局
公开(公告)号：US07002177B2
公开(公告)日：2006-02-21
申请号：US10701824
申请日：2003-11-05
申请人： Weng Chang , Chih-Cheng Lu , Stacey Fu , Syun-Ming Jang
发明人： Weng Chang , Chih-Cheng Lu , Stacey Fu , Syun-Ming Jang
IPC分类号： H01L23/58 , H01L27/14 , G01R31/26
CPC分类号： H01L22/34 , H01L21/76229
摘要： A test region layout for testing shallow trench isolation gap fill characteristics is disclosed. Each test region further comprises at least one test pattern disposed in an interior portion of the test region. In a preferred embodiment, the test pattern is a square shape or, more preferably, two diametrically opposed “L” shapes which are discontinuous with respect to each other. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：公开了一种用于测试浅沟槽隔离间隙填充特性的测试区域布局。每个测试区域还包括设置在测试区域的内部部分中的至少一个测试图案。在优选实施例中，测试图案是相对于彼此不连续的正方形或更优选的两个直径相对的“L”形。要强调的是，该摘要被提供以符合要求摘要的规则，这将允许搜索者或其他读者快速确定技术公开的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

2. 发明申请

US20050095727A1 Test region layout for shallow trench isolation 失效
标题翻译：浅沟槽隔离测试区域布局
公开(公告)号：US20050095727A1
公开(公告)日：2005-05-05
申请号：US10701824
申请日：2003-11-05
申请人： Weng Chang , Chih-Cheng Lu , Chu-Yun Fu , Syun-Ming Jang
发明人： Weng Chang , Chih-Cheng Lu , Chu-Yun Fu , Syun-Ming Jang
IPC分类号： H01L21/762 , H01L23/544 , H01L21/66 , G01R31/26 , H01L21/76
CPC分类号： H01L22/34 , H01L21/76229
摘要： A test region layout for testing shallow trench isolation gap fill characteristics is disclosed. Each test region further comprises at least one test pattern disposed in an interior portion of the test region. In a preferred embodiment, the test pattern is a square shape or, more preferably, two diametrically opposed “L” shapes which are discontinuous with respect to each other. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：公开了一种用于测试浅沟槽隔离间隙填充特性的测试区域布局。每个测试区域还包括设置在测试区域的内部部分中的至少一个测试图案。在优选实施例中，测试图案是相对于彼此不连续的正方形或更优选的两个直径相对的“L”形。要强调的是，该摘要被提供以符合要求摘要的规则，这将允许搜索者或其他读者快速确定技术公开的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

3. 发明授权

US07118987B2 Method of achieving improved STI gap fill with reduced stress 有权
标题翻译：实现改善STI间隙填充减少应力的方法
公开(公告)号：US07118987B2
公开(公告)日：2006-10-10
申请号：US10767657
申请日：2004-01-29
申请人： Chu-Yun Fu , Chih-Cheng Lu , Syun-Ming Jang
发明人： Chu-Yun Fu , Chih-Cheng Lu , Syun-Ming Jang
IPC分类号： H01L21/76
CPC分类号： H01L21/76235 , A61F2/958 , A61F2002/9583 , A61F2250/0098 , A61M25/001 , A61M25/005 , A61M25/0054 , A61M25/0068 , A61M25/0069 , A61M25/008 , A61M25/0108 , A61M25/0127 , A61M25/1027 , A61M2025/1079 , A61M2025/1093 , A61M2205/32
摘要： A shallow trench isolation (STI) structure and method of forming the same with reduced stress to improve charge mobility the method including providing a semiconductor substrate comprising at least one patterned hardmask layer overlying the semiconductor substrate; dry etching a trench in the semiconductor substrate according to the at least one patterned hardmask layer; forming one or more liner layers to line the trench selected from the group consisting of silicon dioxide, silicon nitride, and silicon oxynitride; forming one or more layers of trench filling material comprising silicon dioxide to backfill the trench; carrying out at least one thermal annealing step to relax accumulated stress in the trench filling material; carrying out at least one of a CMP and dry etch process to remove excess trench filling material above the trench level; and, removing the at least one patterned hardmask layer.
摘要翻译：一种浅沟槽隔离（STI）结构及其形成方法，其具有减小的应力以改善电荷迁移率，该方法包括提供包括覆盖在半导体衬底上的至少一个图案化硬掩模层的半导体衬底; 根据所述至少一个图案化硬掩模层干蚀刻所述半导体衬底中的沟槽; 形成一个或多个衬垫层以使选自二氧化硅，氮化硅和氮氧化硅的沟槽的沟槽; 形成包含二氧化硅的一层或多层沟槽填充材料以回填沟槽; 进行至少一个热退火步骤以缓和沟槽填充材料中的累积应力; 执行CMP和干蚀刻工艺中的至少一个以去除沟槽高度上的多余沟槽填充材料; 以及去除所述至少一个图案化的硬掩模层。

4. 发明授权

US06350694B1 Reducing CMP scratch, dishing and erosion by post CMP etch back method for low-k materials 有权
标题翻译：对于低k材料，通过后CMP回蚀法减少CMP划痕，凹陷和侵蚀
公开(公告)号：US06350694B1
公开(公告)日：2002-02-26
申请号：US09814038
申请日：2001-03-22
申请人： Weng Chang , Tien-I Bao , Syun-Ming Jang
发明人： Weng Chang , Tien-I Bao , Syun-Ming Jang
IPC分类号： H01L21302
CPC分类号： G11C11/406 , G11C11/404 , G11C11/40603 , G11C11/4096 , H01L21/02074 , H01L21/31055 , H01L21/31058 , H01L21/3212 , H01L21/76819 , H01L21/7684
摘要： A new plasma etch back is provided that is applied to the surface of a low-k dielectric after the process of CMP of a copper surface has been completed. The copper surface is the surface of interconnect metal, the interconnect metal is embedded in the layer of low-k dielectric.
摘要翻译：提供了一种新的等离子体回蚀，其在铜表面的CMP处理已经完成之后被施加到低k电介质的表面。铜表面是互连金属的表面，互连金属嵌入在低k电介质层中。

5. 发明申请

US20050245100A1 Reliability improvement of SiOC etch with trimethylsilane gas passivation in Cu damascene interconnects 有权
标题翻译：在Cu大马士革互连中三甲基硅烷气体钝化的SiOC蚀刻的可靠性提高
公开(公告)号：US20050245100A1
公开(公告)日：2005-11-03
申请号：US10835788
申请日：2004-04-30
申请人： Zhen-Cheng Wu , Bi-Troug Chen , Weng Chang , Syun-Ming Jang , Su-Horng Lin
发明人： Zhen-Cheng Wu , Bi-Troug Chen , Weng Chang , Syun-Ming Jang , Su-Horng Lin
IPC分类号： H01L21/306 , H01L21/314 , H01L21/316 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/31633 , H01L21/02046 , H01L21/02126 , H01L21/02211 , H01L21/02274 , H01L21/02304 , H01L21/02315 , H01L21/3144 , H01L21/3145 , H01L21/3148 , H01L21/76807 , H01L21/76829 , H01L21/76832
摘要： A method of forming a SiCOH etch stop layer in a copper damascene process is described. A substrate with an exposed metal layer is treated with H2 or NH3 plasma to remove metal oxides. Trimethylsilane is flowed into a chamber with no RF power at about 350° C. to form at least a monolayer on the exposed metal layer. The SiCOH layer is formed by a PECVD process including trimethylsilane and CO2 source gases. Optionally, a composite SiCOH layer comprised of a low compressive stress layer on a high compressive stress layer is formed on the substrate. A conventional damascene sequence is then used to form a second metal layer on the exposed metal layer. Via Rc stability is improved and a lower leakage current is achieved with the trimethylsilane passivation layer. A composite SiCOH etch stop layer provides improved stress migration resistance compared to a single low stress SiCOH layer.
摘要翻译：描述了在铜镶嵌工艺中形成SiCOH蚀刻停止层的方法。具有暴露的金属层的衬底用H 2 N 3或NH 3 3等离子体处理以除去金属氧化物。三甲基硅烷在约350℃下流入没有RF功率的室，以在暴露的金属层上形成至少单层。 SiCOH层通过包括三甲基硅烷和CO 2原子气体的PECVD工艺形成。任选地，在基底上形成由高压缩应力层上的低压应力层构成的复合SiCOH层。然后使用常规的镶嵌序列在暴露的金属层上形成第二金属层。通过Rc稳定性提高，并且用三甲基硅烷钝化层实现较低的漏电流。与单个低应力SiCOH层相比，复合SiCOH蚀刻停止层提供改进的应力迁移阻力。

6. 发明申请

US20050050708A1 Embedded fastener apparatus and method for preventing particle contamination 审中-公开
标题翻译：嵌入式紧固件装置和防止颗粒污染的方法
公开(公告)号：US20050050708A1
公开(公告)日：2005-03-10
申请号：US10656586
申请日：2003-09-04
申请人： Yu-Lien Huang , Weng Chang , Syun-Ming Jang , Mong Song Liang
发明人： Yu-Lien Huang , Weng Chang , Syun-Ming Jang , Mong Song Liang
IPC分类号： B21D39/03 , B23P11/00 , C23C16/44
CPC分类号： C23C16/45565 , C23C16/4401 , Y10T29/49826 , Y10T29/49947
摘要： A novel embedded fastener apparatus and method for fastening components to the interior of a process chamber of a semiconductor fabrication apparatus. In one embodiment, an apparatus having a showerhead or gas distribution plate which is mounted to the interior of the process chamber using multiple fasteners which are embedded in respective fastener openings in the showerhead. In another embodiment, an apparatus having a showerhead which is mounted to the interior of the process chamber using multiple exterior fasteners which extend into the showerhead through the walls of the process chamber. Accordingly, the regions of the showerhead which surround the fasteners are physically separated from the interior of the process chamber.
摘要翻译：一种用于将部件固定到半导体制造装置的处理室的内部的新颖的嵌入式紧固装置和方法。在一个实施例中，一种具有喷头或气体分配板的装置，其使用嵌入在喷头中的相应紧固件开口中的多个紧固件安装到处理室的内部。在另一个实施例中，一种具有喷头的装置，其使用多个外部紧固件安装到处理室的内部，多个外部紧固件通过处理室的壁延伸到喷头中。因此，围绕紧固件的喷头的区域在物理上与处理室的内部分离。

7. 发明授权

US06271138B1 Chemical mechanical polish (CMP) planarizing method with enhanced chemical mechanical polish (CMP) planarized layer planarity 有权
标题翻译：化学机械抛光（CMP）平面化方法，具有增强的化学机械抛光（CMP）平面化层平面度
公开(公告)号：US06271138B1
公开(公告)日：2001-08-07
申请号：US09405058
申请日：1999-09-27
申请人： Weng Chang , Syun-Ming Jang
发明人： Weng Chang , Syun-Ming Jang
IPC分类号： H01L21302
CPC分类号： H01L21/31053
摘要： A chemical mechanical polish (CMP) planarizing method for forming a chemical mechanical polish (CMP) planarized microelectronic layer within a microelectronic fabrication employs first a substrate. There is then formed over the substrate a microelectronic layer. There is then planarized, while employing a chemical mechanical polish (CMP) planarizing method, the microelectronic layer to form a chemical mechanical polish (CMP) planarized microelectronic layer. Within the method, the microelectronic layer when formed over the substrate is formed with a thickness variation which compensates for a chemical mechanical polish (CM) rate non-uniformity when forming while employing the chemical mechanical polish (CMP) planarizing method the chemical mechanical polish (CMP) planarized microelectronic layer from the microelectronic layer.
摘要翻译：用于在微电子制造中形成化学机械抛光（CMP）平面化微电子层的化学机械抛光（CMP）平面化方法首先使用衬底。然后在衬底上形成微电子层。然后平面化，同时采用化学机械抛光（CMP）平面化方法，微电子层形成化学机械抛光（CMP）平面化微电子层。在该方法中，当形成在衬底上的微电子层形成厚度变化，其在成形时补偿化学机械抛光（CM）速率不均匀性，同时使用化学机械抛光（CMP）平面化方法化学机械抛光 CMP）平面化微电子层。

8. 发明授权

US07375040B2 Etch stop layer 有权
标题翻译：蚀刻停止层
公开(公告)号：US07375040B2
公开(公告)日：2008-05-20
申请号：US11325935
申请日：2006-01-05
申请人： Simon S. H. Lin , Weng Chang , Syun-Ming Jang , Mong Song Liang
发明人： Simon S. H. Lin , Weng Chang , Syun-Ming Jang , Mong Song Liang
IPC分类号： H01L21/205
CPC分类号： H01L21/76829 , H01L21/02126 , H01L21/02167 , H01L21/31116 , H01L21/3148 , H01L21/76801 , H01L21/76802 , H01L21/76807 , H01L21/76813
摘要： A SiOC layer and/or a SiC layer of an etch stop layer may be improved by altering the process used to form them. In a bi-layer structure, a SiOC layer and/or a SiC layer may be improved to provide better reliability. A silicon carbide (SiC) layer may be used to form a single-layer etch stop layer, while also acting as a glue layer to improve interface adhesion. Preferably, the SiC layer is formed in a reaction chamber having a flow of substantially pure trimetholsilane (3MS) streamed into and through the reaction chamber under a pressure of less than about 2 torr therein. Preferably, the reaction chamber is energized with high frequency RF power of about 100 watts or more. Preferably, the SiOC layer is formed in a reaction chamber having a flow of 3MS and CO2, and is energized with low frequency RF power of about 100 watts or more.
摘要翻译：蚀刻停止层的SiOC层和/或SiC层可以通过改变用于形成它们的工艺来改进。在双层结构中，可以改善SiOC层和/或SiC层以提供更好的可靠性。可以使用碳化硅（SiC）层来形成单层蚀刻停止层，同时还用作胶层以改善界面附着力。优选地，在反应室中形成具有基本上纯的三甲基硅烷（3MS）的流动的反应室，该三甲基硅烷（3MS）在小于约2托的压力下流入反应室并通过反应室。优选地，反应室以约100瓦或更高的高频RF功率通电。优选地，在具有3MS和CO 2 2的流量的反应室中形成SiOC层，并且以约100瓦特或更高的低频RF功率通电。

9. 发明授权

US07193325B2 Reliability improvement of SiOC etch with trimethylsilane gas passivation in Cu damascene interconnects 有权
标题翻译：在Cu大马士革互连中三甲基硅烷气体钝化的SiOC蚀刻的可靠性提高
公开(公告)号：US07193325B2
公开(公告)日：2007-03-20
申请号：US10835788
申请日：2004-04-30
申请人： Zhen-Cheng Wu , Bi-Troug Chen , Weng Chang , Syun-Ming Jang , Su-Horng Lin
发明人： Zhen-Cheng Wu , Bi-Troug Chen , Weng Chang , Syun-Ming Jang , Su-Horng Lin
IPC分类号： H01L23/48
CPC分类号： H01L21/31633 , H01L21/02046 , H01L21/02126 , H01L21/02211 , H01L21/02274 , H01L21/02304 , H01L21/02315 , H01L21/3144 , H01L21/3145 , H01L21/3148 , H01L21/76807 , H01L21/76829 , H01L21/76832
摘要： A method of forming a SiCOH etch stop layer in a copper damascene process is described. A substrate with an exposed metal layer is treated with H2 or NH3 plasma to remove metal oxides. Trimethylsilane is flowed into a chamber with no RF power at about 350° C. to form at least a monolayer on the exposed metal layer. The SiCOH layer is formed by a PECVD process including trimethylsilane and CO2 source gases. Optionally, a composite SiCOH layer comprised of a low compressive stress layer on a high compressive stress layer is formed on the substrate. A conventional damascene sequence is then used to form a second metal layer on the exposed metal layer. Via Rc stability is improved and a lower leakage current is achieved with the trimethylsilane passivation layer. A composite SiCOH etch stop layer provides improved stress migration resistance compared to a single low stress SiCOH layer.
摘要翻译：描述了在铜镶嵌工艺中形成SiCOH蚀刻停止层的方法。具有暴露的金属层的衬底用H 2 N 3或NH 3 3等离子体处理以除去金属氧化物。三甲基硅烷在约350℃下流入没有RF功率的室，以在暴露的金属层上形成至少单层。 SiCOH层通过包括三甲基硅烷和CO 2原子气体的PECVD工艺形成。任选地，在基底上形成由高压缩应力层上的低压应力层构成的复合SiCOH层。然后使用常规的镶嵌序列在暴露的金属层上形成第二金属层。通过Rc稳定性提高，并且用三甲基硅烷钝化层实现较低的漏电流。与单个低应力SiCOH层相比，复合SiCOH蚀刻停止层提供改进的应力迁移阻力。

10. 发明授权

US06319809B1 Method to reduce via poison in low-k Cu dual damascene by UV-treatment 有权
标题翻译：通过紫外线处理减少低k Cu双镶嵌物的通过毒物的方法
公开(公告)号：US06319809B1
公开(公告)日：2001-11-20
申请号：US09614595
申请日：2000-07-12
申请人： Weng Chang , Lain-Jong Li , Shwang Ming Jeng , Syun-Ming Jang
发明人： Weng Chang , Lain-Jong Li , Shwang Ming Jeng , Syun-Ming Jang
IPC分类号： H01L2144
CPC分类号： H01L21/76825 , H01L21/76807 , H01L21/76814
摘要： A method to reduce via poisoning in low-k copper dual damascene interconnects through ultraviolet (UV) irradiation of the damascene structure is disclosed. This is accomplished by irradiating the insulative layers each time the layers are etched to form a portion of the damascene structure. Thus, irradiation is performed once after the forming of a trench or a via, and again for the second time when the insulative layers are etched to form the remaining trench or via. The trench and hole openings of the dual damascene structure are exposed to UV light in a dry ozone environment, which then favorably alters the surface characteristics of the low-k dielectric walls which are normally hydrophobic. Hence, during etching, moisture is not absorbed into the walls. Furthermore, it is found that the UV treatment inhibits reaction between the walls and the photoresist used during the forming of the damascene structure, thereby providing clean openings without any photoresist residue, and hence, much less poisoned contacts/vias. Consequently, as copper is deposited into the clean damascene, voids are avoided, and a Cu dual damascene interconnect with low RC delay characteristics is obtained.
摘要翻译：公开了一种通过紫外（UV）照射大马士革结构来减少低k铜双镶嵌互连中的通孔中毒的方法。这是通过在每次蚀刻层以形成镶嵌结构的一部分时照射绝缘层来实现的。因此，在形成沟槽或通孔之后进行一次照射，并且再次在绝缘层被蚀刻以形成剩余的沟槽或通孔时再次进行。双重镶嵌结构的沟槽和孔洞在干燥臭氧环境中暴露于紫外线，这有利地改变通常是疏水性的低k电介质壁的表面特性。因此，在蚀刻期间，水分不会被吸收到壁中。此外，发现UV处理抑制在形成镶嵌结构期间使用的壁和光致抗蚀剂之间的反应，从而提供清洁的开口，而没有任何光致抗蚀剂残留物，因此，更少中毒的触点/通孔。因此，当铜沉积到清洁的镶嵌中时，避免了空隙，并且获得具有低RC延迟特性的铜双镶嵌互连。

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