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1. 发明申请

US20070101033A1 Priority control in resource allocation for low request rate, latency-sensitive units 失效
标题翻译：低请求率，延迟敏感单位的资源分配优先级控制
公开(公告)号：US20070101033A1
公开(公告)日：2007-05-03
申请号：US11260579
申请日：2005-10-27
申请人： Wen-Tzer Chen , Charles Johns , Ram Raghavan , Andrew Wottreng
发明人： Wen-Tzer Chen , Charles Johns , Ram Raghavan , Andrew Wottreng
IPC分类号： G06F13/14
CPC分类号： G06F13/362
摘要： A mechanism for priority control in resource allocation for low request rate, latency-sensitive units is provided. With this mechanism, when a unit makes a request to a token manager, the unit identifies the priority of its request as well as the resource which it desires to access and the unit's resource access group (RAG). This information is used to set a value of a storage device associated with the resource, priority, and RAG identified in the request. When the token manager generates and grants a token to the RAG, the token is in turn granted to a unit within the RAG based on a priority of the pending requests identified in the storage devices associated with the resource and RAG. Priority pointers are utilized to provide a round-robin fairness scheme between high and low priority requests within the RAG for the resource.
摘要翻译：提供了一种用于低请求率，延迟敏感单元的资源分配中的优先级控制机制。利用该机制，当单元向令牌管理器发出请求时，该单元识别其请求的优先级以及它希望访问的资源和单元的资源访问组（RAG）。该信息用于设置与请求中标识的资源，优先级和RAG相关联的存储设备的值。当令牌管理器生成并向RAG授予令牌时，根据在与资源和RAG相关联的存储设备中标识的未决请求的优先级，将令牌授予RAG内的单元。优先级指针用于在资源的RAG内提供高优先级请求和低优先级请求之间的循环公平性方案。

2. 发明申请

US20050138621A1 Method of resource allocation using an access control mechanism 失效
标题翻译：使用访问控制机制的资源分配方法
公开(公告)号：US20050138621A1
公开(公告)日：2005-06-23
申请号：US10738720
申请日：2003-12-17
申请人： Scott Clark , Michael Day , Charles Johns , Andrew Wottreng
发明人： Scott Clark , Michael Day , Charles Johns , Andrew Wottreng
IPC分类号： G06F9/46
CPC分类号： G06F9/52 , G06F9/5011
摘要： A method and apparatus are provided for efficiently managing limited resources is a given computer system. The system utilizes a token manager that assigns tokens to groups of associated requestors. The tokens are then utilized by the requesters to occupy the given resource. The allocation of these tokens, thus, prevents such problems as denial of service due to a lack of available resources.
摘要翻译：提供用于有效地管理有限资源的方法和装置是给定的计算机系统。该系统利用令牌管理器，将令牌分配给相关联的请求者的组。然后请求者利用令牌来占用给定的资源。因此，这些令牌的分配可以防止由于缺乏可用资源而导致拒绝服务的问题。

3. 发明申请

US20070180269A1 I/O address translation blocking in a secure system during power-on-reset 审中-公开
标题翻译：上电复位期间安全系统中的I / O地址转换阻塞
公开(公告)号：US20070180269A1
公开(公告)日：2007-08-02
申请号：US11344901
申请日：2006-02-01
申请人： John Irish , Charles Johns , Chad McBride , Ibrahim Ouda , Andrew Wottreng
发明人： John Irish , Charles Johns , Chad McBride , Ibrahim Ouda , Andrew Wottreng
IPC分类号： G06F12/14
CPC分类号： G06F12/1475
摘要： A method and apparatus for the prevention of unwanted access to secure areas of memory during the POR or boot sequence of a CPU. Via control within the CPU, commands that are sent to and received by the CPU prior to the finish of the POR sequence can be denied I/O address translation, thus protecting memory during the POR sequence. Furthermore, an error response can be generated in the CPU and sent back to the I/O device which issued the command.
摘要翻译：一种用于在CPU的POR或引导顺序期间防止对存储器的安全区域的不期望的访问的方法和装置。通过CPU内的控制，在POR序列完成之前发送到CPU并由CPU接收的命令可以被拒绝I / O地址转换，从而在POR序列期间保护存储器。此外，可以在CPU中产生错误响应并发送回发出命令的I / O设备。

4. 发明申请

US20070130372A1 I/O address translation apparatus and method for specifying a relaxed ordering for I/O accesses 失效
标题翻译： I / O地址转换装置和用于指定I / O访问的轻松排序的方法
公开(公告)号：US20070130372A1
公开(公告)日：2007-06-07
申请号：US11274842
申请日：2005-11-15
申请人： John Irish , Charles Johns , Andrew Wottreng
发明人： John Irish , Charles Johns , Andrew Wottreng
IPC分类号： G06F3/00
CPC分类号： G06F13/12 , G06F12/1081
摘要： An I/O address translation apparatus and method for specifying relaxed ordering for I/O accesses are provided. With the apparatus and method, storage ordering (SO) bits are provided in an I/O address translation data structure, such as a page table or segment table. These SO bits define the order in which reads and/or writes initiated by an I/O device may be performed. These SO bits are combined with an ordering bit, e.g., the Relaxed Ordering Attribute bit of PCI Express, on the I/O interface. The weaker ordering indicated either in the I/O address translation data structure or in the I/O interface relaxed ordering bit is used to control the order in which I/O operations may be performed.
摘要翻译：提供了用于指定I / O访问的轻松排序的I / O地址转换装置和方法。利用该装置和方法，在I / O地址转换数据结构（例如页表或段表）中提供存储顺序（SO）位。这些SO位定义可以执行由I / O设备启动的读取和/或写入的顺序。这些SO位与I / O接口上的排序位（例如PCI Express的轻松排序属性位）组合。在I / O地址转换数据结构或I / O接口松弛排序位中指示的较弱排序用于控制可能执行I / O操作的顺序。

5. 发明申请

US20070038797A1 Methods and apparatus for invalidating multiple address cache entries 有权
标题翻译：使多个地址缓存条目无效的方法和装置
公开(公告)号：US20070038797A1
公开(公告)日：2007-02-15
申请号：US11201971
申请日：2005-08-11
申请人： Chad McBride , Andrew Wottreng
发明人： Chad McBride , Andrew Wottreng
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0891
摘要： In a first aspect, a first method is provided for removing entries from an address cache. The first method includes the steps of (1) writing data to a register; and (2) removing a plurality of address cache entries from the address cache based on the data written to the register. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种从地址高速缓存中移除条目的第一方法。第一种方法包括以下步骤：（1）将数据写入寄存器; 和（2）基于写入寄存器的数据从地址高速缓存中移除多个地址高速缓存条目。提供了许多其他方面。

6. 发明申请

US20070186046A1 Pseudo LRU algorithm for hint-locking during software and hardware address translation cache miss handling modes 有权
标题翻译：用于虚拟锁定的伪LRU算法在软件和硬件地址转换缓存未命中处理模式下
公开(公告)号：US20070186046A1
公开(公告)日：2007-08-09
申请号：US11348971
申请日：2006-02-07
申请人： John Irish , Chad McBride , Andrew Wottreng
发明人： John Irish , Chad McBride , Andrew Wottreng
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/123 , G06F2212/6042
摘要： The present invention provides an improved way to calculate a replacement way within a processor cache that is effective with different combinations of hardware address translation cache miss handling, software address translation cache miss handling, and hint lock bits. For some embodiments, LRU bits used to select an entry for replacement are updated only if software address translation cache miss handling is disabled. Further, for some embodiments, LRU bits may be modified to change the way a binary tree structure is traversed to avoid selecting a hint locked entry for replacement
摘要翻译：本发明提供了一种用于计算处理器高速缓存中的替换方式的改进方法，该替换方式对于硬件地址转换高速缓存未命中处理，软件地址转换高速缓存未命中处理和提示锁定位的不同组合是有效的。对于一些实施例，仅当禁用软件地址转换高速缓存未命中处理时，才更新用于选择用于替换的条目的LRU位。此外，对于一些实施例，可以修改LRU比特以改变遍历二叉树结构的方式，以避免选择用于替换的提示锁定条目

7. 发明申请

US20070180195A1 Method and apparatus for allowing uninterrupted address translations while performing address translation cache invalidates and other cache operations 失效
标题翻译：允许不间断地址转换同时执行地址转换高速缓存无效和其它高速缓存操作的方法和装置
公开(公告)号：US20070180195A1
公开(公告)日：2007-08-02
申请号：US11344900
申请日：2006-02-01
申请人： Chad McBride , Andrew Wottreng , John Irish
发明人： Chad McBride , Andrew Wottreng , John Irish
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F12/1027
摘要： A method and apparatus for allowing multiple devices access to an address translation cache while cache maintenance operations are occurring at the same time. By interleaving the commands requiring address translation with maintenance operations that may normally take many cycles, address translation requests may have faster access to the address translation cache than if maintenance operations were allowed to stall commands requiring address translations until the maintenance operation was completed.
摘要翻译：一种用于允许多个设备访问地址转换高速缓存并且同时进行高速缓存维护操作的方法和装置。通过将需要地址转换的命令与可能通常需要许多周期的维护操作交错，与维护操作被允许停止需要地址转换的命令直到维护操作完成之前，地址转换请求可能具有对地址转换缓存的更快访问。

8. 发明申请

US20070260754A1 Hardware Assisted Exception for Software Miss Handling of an I/O Address Translation Cache Miss 审中-公开
标题翻译：软件的硬件辅助异常处理I / O地址转换缓存缺陷
公开(公告)号：US20070260754A1
公开(公告)日：2007-11-08
申请号：US11279614
申请日：2006-04-13
申请人： John Irish , Chad McBride , Andrew Wottreng
发明人： John Irish , Chad McBride , Andrew Wottreng
IPC分类号： G06F3/00
CPC分类号： G06F12/1081 , G06F12/1027
摘要： Embodiments of the present invention generally provide an improved technique to handle I/O address translation cache misses caused by I/O commands within a CPU. For some embodiments, CPU hardware may buffer I/O commands that cause an I/O address translation cache miss in a command queue until the I/O address translation cache is updated with the necessary information. When the I/O address translation cache has been updated, the CPU may reissue the I/O command from the command queue, translate the address of the I/O command at a convenient time, and execute the command as if a cache miss did not occur. This way the I/O device does not need to handle an error response from the CPU, the I/O command is handled by the CPU, and the I/O command is not discarded.
摘要翻译：本发明的实施例通常提供一种改进的技术来处理由CPU内的I / O命令引起的I / O地址转换高速缓存未命中。对于一些实施例，CPU硬件可以缓冲在命令队列中导致I / O地址转换高速缓存未命中的I / O命令，直到I / O地址转换高速缓存用必要信息更新。当I / O地址转换缓存更新时，CPU可能会从命令队列重新发出I / O命令，在方便的时候转换I / O命令的地址，并执行命令，就好像高速缓存未命中一样不发生这样，I / O设备不需要处理来自CPU的错误响应，I / O命令由CPU处理，I / O命令不会被丢弃。

9. 发明申请

US20050055462A1 Method, apparatus and computer program product for implementing conditional packet alterations based on transmit port 失效
标题翻译：用于基于发送端口实现条件分组改变的方法，装置和计算机程序产品
公开(公告)号：US20050055462A1
公开(公告)日：2005-03-10
申请号：US10655054
申请日：2003-09-04
申请人： Kerry Imming , John Irish , Tolga Ozguner , Andrew Wottreng
发明人： Kerry Imming , John Irish , Tolga Ozguner , Andrew Wottreng
IPC分类号： G06F15/16 , H04L12/46 , H04L29/06
CPC分类号： H04L69/22
摘要： A method, apparatus and computer program product are provided for implementing conditional packet alterations based upon a transmit port. A selection mechanism is provided for implementing packet alterations. A sequence of frame alteration instructions and transmit port numbers associated with a packet being transmitted is applied to the selection mechanism. The selection mechanism performs alterations on the packet being transmitted responsive to the applied sequence of frame alteration instructions and port numbers associated with the packet. The selection mechanism includes a multiplexer that sequentially receives frame alteration instructions and port numbers associated with a packet being transmitted, and an indirect data array for providing packet alteration data from the indirect data array.
摘要翻译：提供了一种方法，装置和计算机程序产品，用于基于发送端口实现条件分组改变。提供了一种用于实现数据包更改的选择机制。与所发送的分组相关联的帧改变指令和发送端口号的序列被应用于选择机制。选择机制响应于应用的帧改变指令序列和与分组相关联的端口号，对发送的分组进行改变。选择机制包括：多路复用器，其依次接收与正在发送的分组相关联的帧改变指令和端口号;以及间接数据阵列，用于从间接数据阵列提供分组改变数据。

10. 发明申请

US20070226424A1 Low-cost cache coherency for accelerators 有权
标题翻译：加速器的低成本缓存一致性
公开(公告)号：US20070226424A1
公开(公告)日：2007-09-27
申请号：US11388013
申请日：2006-03-23
申请人： Scott Clark , Andrew Wottreng
发明人： Scott Clark , Andrew Wottreng
IPC分类号： G06F13/28
CPC分类号： G06F12/0817 , G06F2212/1016
摘要： Embodiments of the invention provide methods and systems for reducing the consumption of inter-node bandwidth by communications maintaining coherence between accelerators and CPUs. The CPUs and the accelerators may be clustered on separate nodes in a multiprocessing environment. Each node that contains a shared memory device may maintain a directory to track blocks of shared memory that may have been cached at other nodes. Therefore, commands and addresses may be transmitted to processors and accelerators at other nodes only if a memory location has been cached outside of a node. Additionally, because accelerators generally do not access the same data as CPUs, only initial read, write, and synchronization operations may be transmitted to other nodes. Intermediate accesses to data may be performed non-coherently. As a result, the inter-chip bandwidth consumed for maintaining coherence may be reduced.
摘要翻译：本发明的实施例提供了通过保持加速器和CPU之间的一致性来减少节点间带宽消耗的方法和系统。 CPU和加速器可以聚集在多处理环境中的单独的节点上。包含共享存储器设备的每个节点可以维护目录以跟踪可能在其他节点处被缓存的共享存储器的块。因此，只有当存储器位置已被缓存在节点外部时，命令和地址才可以发送到其他节点上的处理器和加速器。另外，因为加速器通常不能访问与CPU相同的数据，所以只能将初始读，写和同步操作传输到其他节点。对数据的中间访问可以非相干地执行。结果，可以减少用于维持一致性所消耗的芯片间带宽。

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