专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050138621A1 Method of resource allocation using an access control mechanism 失效
标题翻译：使用访问控制机制的资源分配方法
公开(公告)号：US20050138621A1
公开(公告)日：2005-06-23
申请号：US10738720
申请日：2003-12-17
申请人： Scott Clark , Michael Day , Charles Johns , Andrew Wottreng
发明人： Scott Clark , Michael Day , Charles Johns , Andrew Wottreng
IPC分类号： G06F9/46
CPC分类号： G06F9/52 , G06F9/5011
摘要： A method and apparatus are provided for efficiently managing limited resources is a given computer system. The system utilizes a token manager that assigns tokens to groups of associated requestors. The tokens are then utilized by the requesters to occupy the given resource. The allocation of these tokens, thus, prevents such problems as denial of service due to a lack of available resources.
摘要翻译：提供用于有效地管理有限资源的方法和装置是给定的计算机系统。该系统利用令牌管理器，将令牌分配给相关联的请求者的组。然后请求者利用令牌来占用给定的资源。因此，这些令牌的分配可以防止由于缺乏可用资源而导致拒绝服务的问题。

2. 发明申请

US20070226424A1 Low-cost cache coherency for accelerators 有权
标题翻译：加速器的低成本缓存一致性
公开(公告)号：US20070226424A1
公开(公告)日：2007-09-27
申请号：US11388013
申请日：2006-03-23
申请人： Scott Clark , Andrew Wottreng
发明人： Scott Clark , Andrew Wottreng
IPC分类号： G06F13/28
CPC分类号： G06F12/0817 , G06F2212/1016
摘要： Embodiments of the invention provide methods and systems for reducing the consumption of inter-node bandwidth by communications maintaining coherence between accelerators and CPUs. The CPUs and the accelerators may be clustered on separate nodes in a multiprocessing environment. Each node that contains a shared memory device may maintain a directory to track blocks of shared memory that may have been cached at other nodes. Therefore, commands and addresses may be transmitted to processors and accelerators at other nodes only if a memory location has been cached outside of a node. Additionally, because accelerators generally do not access the same data as CPUs, only initial read, write, and synchronization operations may be transmitted to other nodes. Intermediate accesses to data may be performed non-coherently. As a result, the inter-chip bandwidth consumed for maintaining coherence may be reduced.
摘要翻译：本发明的实施例提供了通过保持加速器和CPU之间的一致性来减少节点间带宽消耗的方法和系统。 CPU和加速器可以聚集在多处理环境中的单独的节点上。包含共享存储器设备的每个节点可以维护目录以跟踪可能在其他节点处被缓存的共享存储器的块。因此，只有当存储器位置已被缓存在节点外部时，命令和地址才可以发送到其他节点上的处理器和加速器。另外，因为加速器通常不能访问与CPU相同的数据，所以只能将初始读，写和同步操作传输到其他节点。对数据的中间访问可以非相干地执行。结果，可以减少用于维持一致性所消耗的芯片间带宽。

3. 发明申请

US20080052472A1 METHODS AND APPARATUS FOR REDUCING COMMAND PROCESSING LATENCY WHILE MAINTAINING COHERENCE 失效
标题翻译：在保持协调的同时减少指令处理的方法和装置
公开(公告)号：US20080052472A1
公开(公告)日：2008-02-28
申请号：US11846697
申请日：2007-08-29
申请人： Jeffrey Brown , Scott Clark , Mark Fredrickson , Charles Johns , David Krolak
发明人： Jeffrey Brown , Scott Clark , Mark Fredrickson , Charles Johns , David Krolak
IPC分类号： G06F12/16
CPC分类号： G06F12/0804 , G06F12/0831
摘要： In a first aspect, a first method of reducing command processing latency while maintaining memory coherence is provided. The first method includes the steps of (1) providing a memory map including memory addresses available to a system; and (2) arranging the memory addresses into a plurality of groups. At least one of the groups does not require the system, in response to a command that requires access to a memory address in the group from a bus unit, to get permission from all remaining bus units included in the system to maintain memory coherence. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种在维持存储器一致性的同时降低命令处理等待时间的方法。第一种方法包括以下步骤：（1）提供包括可用于系统的存储器地址的存储器映射; 和（2）将存储器地址排列成多个组。响应于需要访问来自总线单元的组中的存储器地址的命令，组中的至少一个不需要系统以从包括在系统中的所有剩余总线单元获得许可以维持存储器一致性。提供了许多其他方面。

4. 发明申请

US20060179168A1 System and method for flexible multiple protocols 有权
标题翻译：灵活多协议的系统和方法
公开(公告)号：US20060179168A1
公开(公告)日：2006-08-10
申请号：US11050022
申请日：2005-02-03
申请人： Scott Clark , Charles Johns , James Kahle
发明人： Scott Clark , Charles Johns , James Kahle
IPC分类号： G06F3/00
CPC分类号： G06F13/385
摘要： A system and method for flexible multiple protocols are presented. A device's logical layer may be dynamically configured on a per interface basis to communicate with external devices in a coherent or a non-coherent mode. In coherent mode, commands such as coherency protocol, system commands, and snoop response pass from the device's internal system bus to an external device, thereby creating a logical extension of the devices internal system bus. In non-coherent mode, the input-output bus unit receives commands from the internal system bus and generates non-coherent input-output commands, which are eventually received by an external device.
摘要翻译：介绍了灵活多协议的系统和方法。可以在每个接口的基础上动态地配置设备的逻辑层，以以相干或非相干模式与外部设备进行通信。在相干模式下，诸如一致性协议，系统命令和侦听响应的命令从设备的内部系统总线传递到外部设备，从而创建设备内部系统总线的逻辑扩展。在非相干模式下，输入 - 输出总线单元从内部系统总线接收命令，并产生最终由外部设备接收的非相干输入 - 输出命令。

5. 发明申请

US20060059273A1 Envelope packet architecture for broadband engine 有权
标题翻译：宽带引擎的信封包架构
公开(公告)号：US20060059273A1
公开(公告)日：2006-03-16
申请号：US10942422
申请日：2004-09-16
申请人： Michael Carnevale , Scott Clark , David Hill , Charles Johns , Thomas Pokrandt , Jeffrey Ruedinger , Dorothy Thelen
发明人： Michael Carnevale , Scott Clark , David Hill , Charles Johns , Thomas Pokrandt , Jeffrey Ruedinger , Dorothy Thelen
IPC分类号： G06F15/16
CPC分类号： H04L1/188
摘要： The present invention provides for sending an envelope and replying to an envelope. A transmitter is configured to send an envelope. A receiver is coupled to the transmitter, wherein the receiver is configured to receive the envelope and generate a reply envelope. A send buffer is coupled to the transmitter. A receive buffer is coupled to the receiver. A retry timer is coupled to the transmitter, wherein the retry timer is configured to reset upon the receipt of a reply envelope correlated to the transmit envelope. The transmitter is configured to retransmit an envelope if the transmitter does not receive a corresponding reply envelope within a selected time period as determined by the retry timer. This leads to a decrease in the total number of envelopes, transmitted from both the transmitter and the receiver.
摘要翻译：本发明提供发送信封并回复信封。发射机被配置为发送信封。接收机耦合到发射机，其中接收机被配置为接收信封并产生回复信封。发送缓冲器耦合到发送器。接收缓冲器耦合到接收器。重试定时器耦合到发射机，其中重试定时器被配置为在接收到与发射包络相关的应答包络时复位。如果发射机在由重试定时器确定的选定时间段内没有接收到对应的应答包络，则发射机被配置为重发信封。这导致从发射机和接收机两者发送的信封总数的减少。

6. 发明申请

US20050125581A1 Method of resource arbitration 失效
标题翻译：资源仲裁方法
公开(公告)号：US20050125581A1
公开(公告)日：2005-06-09
申请号：US10730952
申请日：2003-12-09
申请人： Jeffrey Brown , Scott Clark , Charles Johns , Takeshi Yamazaki
发明人： Jeffrey Brown , Scott Clark , Charles Johns , Takeshi Yamazaki
IPC分类号： G06F13/14 , G06F13/362
CPC分类号： G06F13/3625
摘要： An improved method and apparatus for resource arbitration. Four priority classes, managed high (MH), managed low (ML), opportunistic high (OH) and opportunistic low (OL), are defined. A priority class is assigned to each resource access request. An access request concentrator (ARC) is created for each resource, through which the resource is accessed. An access request is chosen at each ARC using the priority order MH, ML, OH, and OL, in decreasing order of priority. If OH priority class resource access requests are locked out, the priority order is temporarily changed to OH, OL, MH, and ML, in decreasing order of priority. If OL priority class resource access requests are locked out, the priority order is temporarily changed to MH, OL, OH, and ML, in decreasing order of priority.
摘要翻译：一种改进的资源仲裁方法和装置。定义了四个优先级，管理高（MH），管理低（ML），机会高（OH）和机会主义低（OL）。优先级分配给每个资源访问请求。为每个资源创建访问请求集中器（ARC），通过该资源访问资源。在优先级顺序为MH，ML，OH和OL的每个ARC中选择访问请求。如果OH优先级资源访问请求被锁定，优先级顺序将按照优先级的降序暂时更改为OH，OL，MH和ML。如果OL优先级资源访问请求被锁定，优先级顺序将按照优先级的降序临时更改为MH，OL，OH和ML。

7. 发明申请

US20080005374A1 System and Method for Flexible Multiple Protocols 有权
标题翻译：灵活多协议的系统和方法
公开(公告)号：US20080005374A1
公开(公告)日：2008-01-03
申请号：US11844336
申请日：2007-08-23
申请人： Scott Clark , Charles Johns , James Kahle
发明人： Scott Clark , Charles Johns , James Kahle
IPC分类号： G06F3/00
CPC分类号： G06F13/385
摘要： A system and method for flexible multiple protocols are presented. A device's logical layer may be dynamically configured on a per interface basis to communicate with external devices in a coherent or a non-coherent mode. In coherent mode, commands such as coherency protocol, system commands, and snoop response pass from the device's internal system bus to an external device, thereby creating a logical extension of the devices internal system bus. In non-coherent mode, the input-output bus unit receives commands from the internal system bus and generates non-coherent input-output commands, which are eventually received by an external device.
摘要翻译：介绍了灵活多协议的系统和方法。可以在每个接口的基础上动态地配置设备的逻辑层，以以相干或非相干模式与外部设备进行通信。在相干模式下，诸如一致性协议，系统命令和侦听响应的命令从设备的内部系统总线传递到外部设备，从而创建设备内部系统总线的逻辑扩展。在非相干模式下，输入 - 输出总线单元从内部系统总线接收命令，并产生最终由外部设备接收的非相干输入 - 输出命令。

8. 发明申请

US20070186052A1 Methods and apparatus for reducing command processing latency while maintaining coherence 审中-公开
标题翻译：减少命令处理延迟同时保持一致性的方法和装置
公开(公告)号：US20070186052A1
公开(公告)日：2007-08-09
申请号：US11348969
申请日：2006-02-07
申请人： Jeffrey Brown , Scott Clark , Mark Fredrickson , Charles Johns , David Krolak
发明人： Jeffrey Brown , Scott Clark , Mark Fredrickson , Charles Johns , David Krolak
IPC分类号： G06F13/28
CPC分类号： G06F12/0804 , G06F12/0831
摘要： In a first aspect, a first method of reducing command processing latency while maintaining memory coherence is provided. The first method includes the steps of (1) providing a memory map including memory addresses available to a system; and (2) arranging the memory addresses into a plurality of groups. At least one of the groups does not require the system, in response to a command that requires access to a memory address in the group from a bus unit, to get permission from all remaining bus units included in the system to maintain memory coherence. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种在维持存储器一致性的同时降低命令处理等待时间的方法。第一种方法包括以下步骤：（1）提供包括可用于系统的存储器地址的存储器映射; 和（2）将存储器地址排列成多个组。响应于需要访问来自总线单元的组中的存储器地址的命令，组中的至少一个不需要系统以从包括在系统中的所有剩余总线单元获得许可以维持存储器一致性。提供了许多其他方面。

9. 发明申请

US20060206657A1 Single port/multiple ring implementation of a hybrid crossbar partially non-blocking data switch 审中-公开
标题翻译：单端口/多环实现混合交叉开关部分非阻塞数据交换
公开(公告)号：US20060206657A1
公开(公告)日：2006-09-14
申请号：US11077330
申请日：2005-03-10
申请人： Scott Clark , Charles Johns , David Krolak , Takeshi Yamazaki , Jeffrey Brown
发明人： Scott Clark , Charles Johns , David Krolak , Takeshi Yamazaki , Jeffrey Brown
IPC分类号： G06F13/00
CPC分类号： G06F13/362 , G06F1/3237 , G06F1/3253 , Y02D10/128 , Y02D10/151
摘要： A ring-based crossbar data switch, a method and a computer program are provided for the transfer of data between multiple bus units in a memory system. Each bus unit is connected to a corresponding data ramp. Each data ramp is only directly connected to the adjacent data ramps. This forms at least one data ring that enables the transfer of data from each bus unit to any other bus unit in the memory system. A central arbiter manages the transfer of data between the data ramps and the transfer of data between the data ramp and its corresponding bus unit. A preferred embodiment contains four data rings, wherein two data rings transfer data clockwise and two data rings transfer data counter-clockwise.
摘要翻译：提供了一种基于环的交叉开关数据开关，方法和计算机程序，用于在存储器系统中的多个总线单元之间传送数据。每个总线单元连接到相应的数据斜坡。每个数据斜坡仅直接连接到相邻的数据斜坡。这形成至少一个数据环，其使得能够将数据从每个总线单元传送到存储器系统中的任何其它总线单元。中央仲裁器管理数据斜坡之间的数据传输和数据斜坡与其对应的总线单元之间的数据传输。优选实施例包含四个数据环，其中两个数据环顺时针传送数据，两个数据环逆时针传送数据。

10. 发明申请

US20060251070A1 Methods and apparatus for facilitating coherency management in distributed multi-processor system 有权
标题翻译：用于促进分布式多处理器系统中的一致性管理的方法和装置
公开(公告)号：US20060251070A1
公开(公告)日：2006-11-09
申请号：US11098621
申请日：2005-04-04
申请人： Takeshi Yamazaki , Jeffrey Brown , Scott Clark , Charles Johns
发明人： Takeshi Yamazaki , Jeffrey Brown , Scott Clark , Charles Johns
IPC分类号： H04L12/56
CPC分类号： G06F12/0831 , G06F12/0813 , G06F2212/251 , G06F2212/253
摘要： Methods and apparatus provide for sending a data command from a first of a plurality of devices to a first address concentrator within a first of a plurality of processing systems; selecting one of the other processing systems, the selected processing system having data addressed by the data command stored therein; sending the data command to a first address concentrator of the selected processing system; and broadcasting the data command from the first address concentrator of the selected processing system to a second address concentrator in each of the processing systems.
摘要翻译：方法和装置提供从多个设备中的第一设备向多个处理系统中的第一个内的第一地址集中器发送数据命令; 选择其他处理系统之一，所选择的处理系统具有由其中存储的数据命令寻址的数据; 将所述数据命令发送到所选择的处理系统的第一地址集中器; 以及从所选择的处理系统的第一地址集中器将数据命令广播到每个处理系统中的第二地址集中器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式