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1. 发明申请

US20070180269A1 I/O address translation blocking in a secure system during power-on-reset 审中-公开
标题翻译：上电复位期间安全系统中的I / O地址转换阻塞
公开(公告)号：US20070180269A1
公开(公告)日：2007-08-02
申请号：US11344901
申请日：2006-02-01
申请人： John Irish , Charles Johns , Chad McBride , Ibrahim Ouda , Andrew Wottreng
发明人： John Irish , Charles Johns , Chad McBride , Ibrahim Ouda , Andrew Wottreng
IPC分类号： G06F12/14
CPC分类号： G06F12/1475
摘要： A method and apparatus for the prevention of unwanted access to secure areas of memory during the POR or boot sequence of a CPU. Via control within the CPU, commands that are sent to and received by the CPU prior to the finish of the POR sequence can be denied I/O address translation, thus protecting memory during the POR sequence. Furthermore, an error response can be generated in the CPU and sent back to the I/O device which issued the command.
摘要翻译：一种用于在CPU的POR或引导顺序期间防止对存储器的安全区域的不期望的访问的方法和装置。通过CPU内的控制，在POR序列完成之前发送到CPU并由CPU接收的命令可以被拒绝I / O地址转换，从而在POR序列期间保护存储器。此外，可以在CPU中产生错误响应并发送回发出命令的I / O设备。

2. 发明申请

US20070180157A1 Method for cache hit under miss collision handling 审中-公开
标题翻译：错误碰撞处理下缓存命中的方法
公开(公告)号：US20070180157A1
公开(公告)日：2007-08-02
申请号：US11344909
申请日：2006-02-01
申请人： John Irish , Chad McBride , Ibrahim Ouda
发明人： John Irish , Chad McBride , Ibrahim Ouda
IPC分类号： G06F3/00
CPC分类号： G06F12/1027 , G06F12/0855 , G06F2212/684
摘要： Embodiments of the present invention provide methods and systems for maintaining command order while processing commands in a command queue. Commands may be queued in an input command queue at the CPU. During address translation for a command, subsequent commands may be processed to increase efficiency. Processed commands may be placed in an output queue and sent to the CPU in order. If address translation entries for a command are not found, the translation entries may be retrieved from memory. Address translations for subsequent commands depending from the command getting the miss may be preserved until the address translation entry is retrieved from memory. Therefore, retranslation of addresses for subsequent commands is avoided.
摘要翻译：本发明的实施例提供了在处理命令队列中的命令时维持命令顺序的方法和系统。命令可能在CPU的输入命令队列中排队。在命令的地址转换期间，可以处理后续命令以提高效率。处理的命令可以放置在输出队列中并按顺序发送到CPU。如果没有找到命令的地址转换条目，则可以从存储器检索翻译条目。从命令获取未命中取得的后续命令的地址转换可以被保留，直到从存储器检索到地址转换条目为止。因此，避免了后续命令的地址重新转发。

3. 发明申请

US20070180156A1 Method for completing IO commands after an IO translation miss 审中-公开
标题翻译：在IO翻译错过后完成IO命令的方法
公开(公告)号：US20070180156A1
公开(公告)日：2007-08-02
申请号：US11344908
申请日：2006-02-01
申请人： John Irish , Chad McBride , Ibrahim Ouda
发明人： John Irish , Chad McBride , Ibrahim Ouda
IPC分类号： G06F3/00
CPC分类号： G06F12/1027 , G06F12/1009 , G06F2212/684
摘要： Embodiments of the present invention provide methods and systems for maintaining command order while processing commands in a command queue while handling translation cache misses. Commands may be queued in an input command queue at the CPU. During address translation for a command, subsequent commands may be processed to increase efficiency. Processed commands may be placed in an output queue and sent to the CPU in order. During address translation, if a translation cache miss occurs the relevant translation cache entries may be retrieved from memory. After the relevant entries are retrieved a notification may be sent requesting reissue of the command getting the translation cache miss.
摘要翻译：本发明的实施例提供了在处理转换高速缓存未命中时在命令队列中处理命令时维持命令顺序的方法和系统。命令可能在CPU的输入命令队列中排队。在命令的地址转换期间，可以处理后续命令以提高效率。处理的命令可以放置在输出队列中并按顺序发送到CPU。在地址转换期间，如果翻译高速缓存未命中，则可以从存储器检索相关的转换高速缓存条目。在检索到相关条目之后，可以发送请求重新发出获得翻译高速缓存未命中的命令的通知。

4. 发明申请

US20070180158A1 Method for command list ordering after multiple cache misses 审中-公开
标题翻译：多重缓存未命中后的命令列表排序方法
公开(公告)号：US20070180158A1
公开(公告)日：2007-08-02
申请号：US11344910
申请日：2006-02-01
申请人： John Irish , Chad McBride , Ibrahim Ouda
发明人： John Irish , Chad McBride , Ibrahim Ouda
IPC分类号： G06F3/00
CPC分类号： G06F12/1027 , G06F12/1009 , G06F2212/684
摘要： Embodiments of the present invention provide methods and systems for maintaining command order while processing commands in a command queue while handling multiple translation cache misses. Commands may be queued in an input command queue at the CPU. During address translation for a command, subsequent commands may be processed to increase efficiency. Processed commands may be placed in an output queue and sent to the CPU in order. During address translation, if a translation cache miss occurs while an outstanding miss is being handled, the pipeline may be stalled and the command causing the second miss and all subsequent commands may be processed again after the first miss is handled.
摘要翻译：本发明的实施例提供了在处理多个转换高速缓存未命中时在命令队列中处理命令时维持命令顺序的方法和系统。命令可能在CPU的输入命令队列中排队。在命令的地址转换期间，可以处理后续命令以提高效率。处理的命令可以放置在输出队列中并按顺序发送到CPU。在地址转换期间，如果正在处理未完成的未命中时翻译高速缓存未命中，则流水线可能被停止，并且在处理第一个未命中之后再次处理导致第二未命中的命令和所有后续命令。

5. 发明申请

US20070186046A1 Pseudo LRU algorithm for hint-locking during software and hardware address translation cache miss handling modes 有权
标题翻译：用于虚拟锁定的伪LRU算法在软件和硬件地址转换缓存未命中处理模式下
公开(公告)号：US20070186046A1
公开(公告)日：2007-08-09
申请号：US11348971
申请日：2006-02-07
申请人： John Irish , Chad McBride , Andrew Wottreng
发明人： John Irish , Chad McBride , Andrew Wottreng
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/123 , G06F2212/6042
摘要： The present invention provides an improved way to calculate a replacement way within a processor cache that is effective with different combinations of hardware address translation cache miss handling, software address translation cache miss handling, and hint lock bits. For some embodiments, LRU bits used to select an entry for replacement are updated only if software address translation cache miss handling is disabled. Further, for some embodiments, LRU bits may be modified to change the way a binary tree structure is traversed to avoid selecting a hint locked entry for replacement
摘要翻译：本发明提供了一种用于计算处理器高速缓存中的替换方式的改进方法，该替换方式对于硬件地址转换高速缓存未命中处理，软件地址转换高速缓存未命中处理和提示锁定位的不同组合是有效的。对于一些实施例，仅当禁用软件地址转换高速缓存未命中处理时，才更新用于选择用于替换的条目的LRU位。此外，对于一些实施例，可以修改LRU比特以改变遍历二叉树结构的方式，以避免选择用于替换的提示锁定条目

6. 发明申请

US20070260754A1 Hardware Assisted Exception for Software Miss Handling of an I/O Address Translation Cache Miss 审中-公开
标题翻译：软件的硬件辅助异常处理I / O地址转换缓存缺陷
公开(公告)号：US20070260754A1
公开(公告)日：2007-11-08
申请号：US11279614
申请日：2006-04-13
申请人： John Irish , Chad McBride , Andrew Wottreng
发明人： John Irish , Chad McBride , Andrew Wottreng
IPC分类号： G06F3/00
CPC分类号： G06F12/1081 , G06F12/1027
摘要： Embodiments of the present invention generally provide an improved technique to handle I/O address translation cache misses caused by I/O commands within a CPU. For some embodiments, CPU hardware may buffer I/O commands that cause an I/O address translation cache miss in a command queue until the I/O address translation cache is updated with the necessary information. When the I/O address translation cache has been updated, the CPU may reissue the I/O command from the command queue, translate the address of the I/O command at a convenient time, and execute the command as if a cache miss did not occur. This way the I/O device does not need to handle an error response from the CPU, the I/O command is handled by the CPU, and the I/O command is not discarded.
摘要翻译：本发明的实施例通常提供一种改进的技术来处理由CPU内的I / O命令引起的I / O地址转换高速缓存未命中。对于一些实施例，CPU硬件可以缓冲在命令队列中导致I / O地址转换高速缓存未命中的I / O命令，直到I / O地址转换高速缓存用必要信息更新。当I / O地址转换缓存更新时，CPU可能会从命令队列重新发出I / O命令，在方便的时候转换I / O命令的地址，并执行命令，就好像高速缓存未命中一样不发生这样，I / O设备不需要处理来自CPU的错误响应，I / O命令由CPU处理，I / O命令不会被丢弃。

7. 发明申请

US20070180195A1 Method and apparatus for allowing uninterrupted address translations while performing address translation cache invalidates and other cache operations 失效
标题翻译：允许不间断地址转换同时执行地址转换高速缓存无效和其它高速缓存操作的方法和装置
公开(公告)号：US20070180195A1
公开(公告)日：2007-08-02
申请号：US11344900
申请日：2006-02-01
申请人： Chad McBride , Andrew Wottreng , John Irish
发明人： Chad McBride , Andrew Wottreng , John Irish
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F12/1027
摘要： A method and apparatus for allowing multiple devices access to an address translation cache while cache maintenance operations are occurring at the same time. By interleaving the commands requiring address translation with maintenance operations that may normally take many cycles, address translation requests may have faster access to the address translation cache than if maintenance operations were allowed to stall commands requiring address translations until the maintenance operation was completed.
摘要翻译：一种用于允许多个设备访问地址转换高速缓存并且同时进行高速缓存维护操作的方法和装置。通过将需要地址转换的命令与可能通常需要许多周期的维护操作交错，与维护操作被允许停止需要地址转换的命令直到维护操作完成之前，地址转换请求可能具有对地址转换缓存的更快访问。

8. 发明申请

US20070136532A1 Methods and apparatus for handling a cache miss 失效
标题翻译：用于处理高速缓存未命中的方法和装置
公开(公告)号：US20070136532A1
公开(公告)日：2007-06-14
申请号：US11297312
申请日：2005-12-08
申请人： John Irish , Chad McBride , Andrew Wottreng
发明人： John Irish , Chad McBride , Andrew Wottreng
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/0862 , G06F12/1027 , G06F12/127 , G06F2212/654
摘要： In a first aspect, a first method is provided. The first method includes the steps of (1) providing a cache having a plurality of cache entries, each entry adapted to store data, wherein the cache is adapted to be accessed by hardware and software in a first operational mode; (2) determining an absence of desired data in one of the plurality of cache entries; (3) determining a status based on a current operational mode and a value of hint-lock bits associated with the plurality of cache entries; and (4) determining availability of at least one of the cache entries based on the status, wherein availability of a cache entry indicates that data stored in the cache entry can be replaced. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了第一种方法。第一种方法包括以下步骤：（1）提供具有多个高速缓存条目的高速缓存，每个条目适于存储数据，其中高速缓存适于在第一操作模式中由硬件和软件进行访问; （2）确定在所述多个高速缓存条目之一中不存在期望数据; （3）基于当前操作模式和与所述多个高速缓存条目相关联的提示锁定位的值来确定状态; 以及（4）基于所述状态来确定所述高速缓存条目中的至少一个的可用性，其中高速缓存条目的可用性指示可以替换存储在所述高速缓存条目中的数据。提供了许多其他方面。

9. 发明申请

US20070130372A1 I/O address translation apparatus and method for specifying a relaxed ordering for I/O accesses 失效
标题翻译： I / O地址转换装置和用于指定I / O访问的轻松排序的方法
公开(公告)号：US20070130372A1
公开(公告)日：2007-06-07
申请号：US11274842
申请日：2005-11-15
申请人： John Irish , Charles Johns , Andrew Wottreng
发明人： John Irish , Charles Johns , Andrew Wottreng
IPC分类号： G06F3/00
CPC分类号： G06F13/12 , G06F12/1081
摘要： An I/O address translation apparatus and method for specifying relaxed ordering for I/O accesses are provided. With the apparatus and method, storage ordering (SO) bits are provided in an I/O address translation data structure, such as a page table or segment table. These SO bits define the order in which reads and/or writes initiated by an I/O device may be performed. These SO bits are combined with an ordering bit, e.g., the Relaxed Ordering Attribute bit of PCI Express, on the I/O interface. The weaker ordering indicated either in the I/O address translation data structure or in the I/O interface relaxed ordering bit is used to control the order in which I/O operations may be performed.
摘要翻译：提供了用于指定I / O访问的轻松排序的I / O地址转换装置和方法。利用该装置和方法，在I / O地址转换数据结构（例如页表或段表）中提供存储顺序（SO）位。这些SO位定义可以执行由I / O设备启动的读取和/或写入的顺序。这些SO位与I / O接口上的排序位（例如PCI Express的轻松排序属性位）组合。在I / O地址转换数据结构或I / O接口松弛排序位中指示的较弱排序用于控制可能执行I / O操作的顺序。

10. 发明申请

US20050071595A1 Methods and apparatus for allocating memory 审中-公开
标题翻译：分配内存的方法和设备
公开(公告)号：US20050071595A1
公开(公告)日：2005-03-31
申请号：US10670703
申请日：2003-09-25
申请人： John Irish , Ibrahim Ouda , James Steenburgh , Jason Thompson
发明人： John Irish , Ibrahim Ouda , James Steenburgh , Jason Thompson
IPC分类号： G06F12/00 , G06F12/02 , H04L12/56
CPC分类号： G06F12/023
摘要： In a first aspect, a first method is provided. The first method includes the steps of (1) receiving a set of data; (2) determining whether a free group entry of a size required by a portion of the set of data exists in one of a plurality of sections of a memory; (3) if a free group entry of the size required by the portion of the set of data does not exist in one of the plurality of sections of the memory, determining whether the memory includes one or more sections of an unallocated size; and (4) if the memory includes one or more sections of an unallocated size, allocating one of the sections of an unallocated size to the size required by the portion of the set of data thereby creating a section of a dynamically allocated size. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了第一种方法。第一种方法包括以下步骤：（1）接收一组数据; （2）确定存储器的多个部分之一中是否存在所述数据集合的一部分所需的大小的空闲组条目; （3）如果存储器的多个部分之一中不存在所述数据集的所述部分所需的大小的空闲组条目，则确定所述存储器是否包括未分配大小的一个或多个部分; 和（4）如果存储器包括一个或多个未分配大小的部分，则将未分配大小的部分中的一个分配给该组数据的部分所需的大小，从而创建动态分配大小的部分。提供了许多其他方面。

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