专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06544828B1 Adding a poly-strip on isolation's edge to improve endurance of high voltage NMOS on EEPROM 有权
标题翻译：在隔离边缘添加多芯片，以提高EEPROM上高压NMOS的耐用性
公开(公告)号：US06544828B1
公开(公告)日：2003-04-08
申请号：US10044860
申请日：2001-11-07
申请人： Wen-Ting Chu , Di-Son Kuo , Jack Yeh , Chia-Ta Hsieh , Chrong-Jung Lin , Sheng-Wei Tsaur
发明人： Wen-Ting Chu , Di-Son Kuo , Jack Yeh , Chia-Ta Hsieh , Chrong-Jung Lin , Sheng-Wei Tsaur
IPC分类号： H01L218234
CPC分类号： H01L29/402 , H01L21/28123 , H01L21/823481 , H01L29/4238
摘要： A method for improving the endurance and robustness of high voltage NMOS devices by forming a conductive field plate at the edge of a shallow trench isolation region at the drain side only is described. Active areas are separated by isolation regions in a substrate. A gate oxide layer is grown on the active areas. A conducting layer is deposited overlying the gate oxide layer and patterned to form gate electrodes in the active areas and to form conductive strips overlapping both the active areas and the isolation areas at an isolation's edge on a drain side of the active areas wherein the conductive strips reduce the electric field at the isolation's edge in the fabrication of an integrated circuit device.
摘要翻译：描述了通过在漏极侧的浅沟槽隔离区域的边缘处形成导电场板来提高高电压NMOS器件的耐久性和鲁棒性的方法。活性区域通过衬底中的隔离区域分离。在活性区域上生长栅极氧化物层。导电层沉积在栅极氧化物层上并被图案化以在有源区域中形成栅电极，并且在有源区域的漏极侧上的隔离边缘处形成与有源区域和隔离区域重叠的导电条带，其中导电条在集成电路器件的制造中减小隔离边缘的电场。

2. 发明授权

US06420233B1 Split gate field effect transistor (FET) device employing non-linear polysilicon floating gate electrode dopant profile 有权
标题翻译：采用非线性多晶硅浮栅电极掺杂剂分布的分流栅场效应晶体管（FET）器件
公开(公告)号：US06420233B1
公开(公告)日：2002-07-16
申请号：US09766860
申请日：2001-01-19
申请人： Chia-Ta Hsieh , Di-Son Kuo , Jake Yeh , Chung-Li Chang , Wen-Ting Chu , Chrong-Jung Lin
发明人： Chia-Ta Hsieh , Di-Son Kuo , Jake Yeh , Chung-Li Chang , Wen-Ting Chu , Chrong-Jung Lin
IPC分类号： H01L29336
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324
摘要： Within both a split gate field effect transistor (FET) device and a method for fabricating the split gate field effect transistor (FET) device there is employed a doped polysilicon floating gate electrode having an central annular portion having a higher dopant concentration than a peripheral annular portion of the doped polysilicon floating gate electrode. The higher dopant concentration within the central annular portion of the doped polysilicon floating gate electrode provides enhanced programming speed properties of the split gate field effect transistor (FET) device. The lower dopant concentration within the peripheral annular portion of the doped polysilicon floating gate electrode provides enhanced erasing speed properties within the split gate field effect transistor (FET) device under certain circumstances of fabrication of the split gate field effect transistor (FET) device.
摘要翻译：在分裂栅场效应晶体管（FET）器件和用于制造分离栅场效应晶体管（FET）器件的方法中，采用掺杂多晶硅浮栅，其具有中间环状部分，其掺杂浓度高于周边环形掺杂多晶硅浮栅电极的一部分。掺杂多晶硅浮置栅电极的中心环形部分内的较高掺杂剂浓度提供了分裂栅极场效应晶体管（FET）器件的增强的编程速度特性。在掺杂多晶硅浮置栅电极的外围环形部分内的较低掺杂剂浓度在分裂栅极场效应晶体管（FET）器件的制造的某些情况下在分裂栅极场效应晶体管（FET）器件内提供增强的擦除速度特性。

3. 发明授权

US5970341A Method for forming vertical channels in split-gate flash memory cell 失效
标题翻译：分闸式闪存单元形成垂直通道的方法
公开(公告)号：US5970341A
公开(公告)日：1999-10-19
申请号：US988772
申请日：1997-12-11
申请人： Chrong-Jung Lin , Chia-Ta Hsieh , Jong Chen , Di-Son Kuo
发明人： Chrong-Jung Lin , Chia-Ta Hsieh , Jong Chen , Di-Son Kuo
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L29/42336 , H01L29/66825 , H01L29/7883
摘要： A method of forming a vertical memory split gate flash memory device on a silicon semiconductor substrate is provided by the following steps. Form a floating gate trench hole in the silicon semiconductor substrate, the trench hole having trench surfaces. Form a tunnel oxide layer on the trench surfaces, the tunnel oxide layer having outer surfaces. Form a floating gate electrode layer filling the trench hole on the outer surfaces of the tunnel oxide layer. Form source/drain regions in the substrate self-aligned with the floating gate electrode layer. Pattern the floating gate electrode layer by removing the gate electrode layer from the drain region side of the trench hole. Form a control gate hole therein. Form an interelectrode dielectric layer over the top surface of the floating gate electrode, and over the tunnel oxide layer. Form a control gate electrode over the interelectrode dielectric layer over the top surface of the floating gate electrode and extending down into the control gate hole in the trench hole.
摘要翻译：通过以下步骤提供在硅半导体衬底上形成垂直存储器分离栅极闪存器件的方法。在硅半导体衬底中形成浮栅沟槽，沟槽具有沟槽表面。在沟槽表面上形成隧道氧化物层，隧道氧化物层具有外表面。形成填充隧道氧化物层的外表面上的沟槽的浮栅电极层。衬底中的源极/漏极区域与浮栅电极层自对准。通过从沟槽的漏极区域侧去除栅极电极层来对浮栅电极层进行构图。在其中形成控制门孔。在浮栅电极的顶表面上方，并在隧道氧化物层之上形成电极间电介质层。在浮栅电极的顶表面上方的电极间电介质层上形成控制栅电极，并向下延伸到沟槽孔中的控制栅极孔。

4. 发明授权

US6078076A Vertical channels in split-gate flash memory cell 有权
标题翻译：分闸式闪存单元中的垂直通道
公开(公告)号：US6078076A
公开(公告)日：2000-06-20
申请号：US317645
申请日：1999-05-24
申请人： Chrong-Jung Lin , Chia-Ta Hsieh , Jong Chen , Di-Son Kuo
发明人： Chrong-Jung Lin , Chia-Ta Hsieh , Jong Chen , Di-Son Kuo
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L29/42336 , H01L29/66825 , H01L29/7883
摘要： A method of forming a vertical memory split gate flash memory device on a silicon semiconductor substrate is provided by the following steps. Form a floating gate trench hole in the silicon semiconductor substrate, the trench hole having trench surfaces. Form a tunnel oxide layer on the trench surfaces, the tunnel oxide layer having outer surfaces. Form a floating gate electrode layer filling the trench hole on the outer surfaces of the tunnel oxide layer. Form source/drain regions in the substrate self-aligned with the floating gate electrode layer. Pattern the floating gate electrode layer by removing the gate electrode layer from the drain region side of the trench hole Form a control gate hole therein. Form an interelectrode dielectric layer over the top surface of the floating gate electrode, and over the tunnel oxide layer. Form a control gate electrode over the interelectrode dielectric layer over the top surface of the floating gate electrode and extending down into the control gate hole in the trench hole.
摘要翻译：通过以下步骤提供在硅半导体衬底上形成垂直存储器分离栅极闪存器件的方法。在硅半导体衬底中形成浮栅沟槽，沟槽具有沟槽表面。在沟槽表面上形成隧道氧化物层，隧道氧化物层具有外表面。形成填充隧道氧化物层的外表面上的沟槽的浮栅电极层。衬底中的源极/漏极区域与浮栅电极层自对准。通过从沟槽的漏极区域侧去除栅极电极层来对浮栅电极层进行构图在其中形成控制栅极孔。在浮栅电极的顶表面上方，并在隧道氧化物层之上形成电极间电介质层。在浮栅电极的顶表面上方的电极间电介质层上形成控制栅电极，并向下延伸到沟槽孔中的控制栅极孔。

5. 发明授权

US06933198B2 Method for forming enhanced areal density split gate field effect transistor device array 有权
标题翻译：用于形成增强的面密度分离栅场效应晶体管器件阵列的方法
公开(公告)号：US06933198B2
公开(公告)日：2005-08-23
申请号：US10326501
申请日：2002-12-20
申请人： Wen-Ting Chu , Chia-Ta Hsieh , Chrong-Jung Lin
发明人： Wen-Ting Chu , Chia-Ta Hsieh , Chrong-Jung Lin
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/423
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： A method for forming a floating gate electrode within a split gate field effect transistor device provides for isotropically processing a blanket isotropically processable material layer having a patterned mask layer formed thereover to form a patterned isotropically processed material layer which encroaches beneath the patterned mask layer. The patterned isotropically processed material layer may then be employed as a mask for forming a floating gate electrode from a blanket floating gate electrode material layer. The method provides for forming adjacent floating gate electrodes with less than minimally photolithographically resolvable separation.
摘要翻译：在分裂栅极场效应晶体管器件内形成浮栅电极的方法提供了各向同性地处理具有形成在其上的图案化掩模层的覆盖层各向同性处理的材料层，以形成图案化的各向同性处理的材料层，其侵入图案化掩模层下面。然后可以将图案化的各向同性处理的材料层用作用于从橡皮布浮栅电极材料层形成浮栅电极的掩模。该方法提供了以少于光刻可分辨的最小分离形成相邻浮栅电极。

6. 发明授权

US6001687A Process for forming self-aligned source in flash cell using SiN spacer as hard mask 有权
标题翻译：使用SiN间隔物作为硬掩模在闪存单元中形成自对准源的工艺
公开(公告)号：US6001687A
公开(公告)日：1999-12-14
申请号：US283849
申请日：1999-04-01
申请人： Wen-Ting Chu , Di-Son Kuo , Chrong-Jung Lin , Hung-Der Su , Jong Chen
发明人： Wen-Ting Chu , Di-Son Kuo , Chrong-Jung Lin , Hung-Der Su , Jong Chen
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/8239
CPC分类号： H01L27/11521
摘要： When FLASH cells are made in association with STI (as opposed to LOCOS) it is often the case that stringers of silicon nitride are left behind after the spacers have been formed. This problem has been eliminated by requiring that the oxide in the STI trenches remain in place at the time that the silicon nitride spacers are formed. After that, the oxide is removed in the usual manner, following which a SALICIDE process is used to form a self aligned source line. When this sequence is followed no stringers are left behind on the walls of the trench, guaranteeing the absence of any open circuits or high resistance regions in the source line.
摘要翻译：当与STI（与LOCOS相反）制成FLASH单元时，通常在形成间隔物之后留下氮化硅桁条。通过要求在形成氮化硅间隔物的时刻STI槽中的氧化物保持在适当位置，已经消除了这个问题。之后，以通常的方式去除氧化物，随后使用SALICIDE工艺来形成自对准的源极线。当遵循该顺序时，沟槽的壁上不留下桁条，保证在源极线中不存在任何开路或高电阻区域。

7. 发明授权

US06251744B1 Implant method to improve characteristics of high voltage isolation and high voltage breakdown 有权
标题翻译：植入法提高高压隔离和高压击穿特性
公开(公告)号：US06251744B1
公开(公告)日：2001-06-26
申请号：US09356870
申请日：1999-07-19
申请人： Hung-Der Su , Chrong-Jung Lin , Jong Chen , Wen-Ting Chu , Hung-Cheng Sung , Di-Son Kuo
发明人： Hung-Der Su , Chrong-Jung Lin , Jong Chen , Wen-Ting Chu , Hung-Cheng Sung , Di-Son Kuo
IPC分类号： H01L2176
CPC分类号： H01L21/76213
摘要： A layer of well oxide is grown over the n-well or p-well region of the semiconductor substrate. A deep n-well implant is performed in high voltage device region, followed by a deep n-well drive-in of the deep n-well implant. The well oxide is removed; the field oxide (FOX) region is created in the high voltage device region. A layer of sacrificial oxide is deposited on the surface of the semiconductor substrate. A low voltage cluster n-well implant is performed in the high voltage PMOS region of the semiconductor substrate followed, for the high voltage NMOS region, by a low voltage cluster p-well implant which is followed by a buried p-well cluster implant.
摘要翻译：在半导体衬底的n阱或p阱区域上生长一层良好的氧化物。在高电压器件区域中进行深n阱注入，随后是深n阱注入的深n阱驱动。去除氧化物; 在高电压器件区域中产生场氧化物（FOX）区域。牺牲氧化物层沉积在半导体衬底的表面上。在半导体衬底的高电压PMOS区域中执行低电压簇n阱注入，随后是高压NMOS区，由低电压簇p阱注入，随后是埋置的p阱簇注入。

8. 发明授权

US06130168A Using ONO as hard mask to reduce STI oxide loss on low voltage device in flash or EPROM process 有权
标题翻译：使用ONO作为硬掩模，以减少闪存或EPROM工艺中低电压器件的STI氧化物损耗
公开(公告)号：US06130168A
公开(公告)日：2000-10-10
申请号：US349844
申请日：1999-07-08
申请人： Wen-Ting Chu , Di-Son Kuo , Chrong-Jung Lin , Hung-Der Su , Jong Chen
发明人： Wen-Ting Chu , Di-Son Kuo , Chrong-Jung Lin , Hung-Der Su , Jong Chen
IPC分类号： H01L21/32 , H01L21/8234 , H01L21/8247 , H01L27/105 , H01L21/302
CPC分类号： H01L27/11526 , H01L21/32 , H01L21/823462 , H01L21/823481 , H01L27/105 , H01L27/11546 , Y10S438/954
摘要： A new method of forming differential gate oxide thicknesses for both high and low voltage transistors is described. A semiconductor substrate is provided wherein active areas of the substrate are isolated from other active areas by shallow trench isolation regions. A polysilicon layer is deposited overlying a tunneling oxide layer on the surface of the substrate. The polysilicon and tunneling oxide layers are removed except in the memory cell area. An ONO layer is deposited overlying the polysilicon layer in the memory cell area and on the surface of the substrate in the low voltage and high voltage areas. The ONO layer is removed in the high voltage area. The substrate is oxidized in the high voltage area to form a thick gate oxide layer. Thereafter, the ONO layer is removed in the low voltage area and the substrate is oxidized to form a thin gate oxide layer. A second polysilicon layer is deposited over the ONO layer in the memory area, over the thin gate oxide layer in the low voltage area, and over the thick gate oxide layer in the high voltage area. The second polysilicon layer, ONO layer and first polysilicon layer in the memory cell area are patterned to form a control gate overlying a floating gate separated by the ONO layer. The second polysilicon layer is patterned to form a low voltage transistor in the low voltage area and a high voltage transistor in the high voltage area.
摘要翻译：描述了为高压和低压晶体管形成差分栅极氧化物厚度的新方法。提供半导体衬底，其中衬底的有源区域通过浅沟槽隔离区域与其它有源区域隔离。沉积在衬底表面上的隧道氧化物层上的多晶硅层。去除多晶硅和隧道氧化物层，除了在存储单元区域中。沉积在存储单元区域中的多晶硅层和低电压和高电压区域的衬底表面上的ONO层。在高电压区域中去除ONO层。衬底在高压区域被氧化以形成厚的栅极氧化物层。此后，在低电压区域中去除ONO层，并且衬底被氧化以形成薄的栅极氧化物层。第二多晶硅层沉积在存储区域中的ONO层上，在低电压区域的薄栅极氧化物层上方，以及高电压区域中的厚栅极氧化物层上方。将存储单元区域中的第二多晶硅层，ONO层和第一多晶硅层图案化以形成覆盖由ONO层分离的浮动栅极的控制栅极。将第二多晶硅层图案化以在低电压区域中形成低压晶体管，并在高电压区域形成高压晶体管。

9. 发明授权

US06902978B2 Method of making the selection gate in a split-gate flash EEPROM cell and its structure 失效
标题翻译：在分闸器快闪EEPROM单元中制作选择栅极的方法及其结构
公开(公告)号：US06902978B2
公开(公告)日：2005-06-07
申请号：US10929396
申请日：2004-08-31
申请人： Wen-Ting Chu , Jack Yeh , Chrong-Jung Lin
发明人： Wen-Ting Chu , Jack Yeh , Chrong-Jung Lin
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/66553 , H01L29/7885
摘要： A method of making the selection gate in a split-gate flash EEPROM cell forms a selection gate on a trench sidewall of a semiconductor substrate to minimize the sidewise dimension of the selection gate and to maintain the channel length. The disclosed method includes the steps of: forming a trench on a semiconductor substrate on one side of a suspending gate structure; forming an inter polysilicon dielectric layer on the sidewall of the suspending gate structure and the trench; and forming a polysilicon spacer on the inter polysilicon dielectric layer as the selection gate. Such a split-gate flash EEPROM cell can produce ballistic hot electrons, improving the data writing efficiency and lowering the writing voltage.
摘要翻译：在分裂栅极快闪EEPROM单元中形成选择栅极的方法在半导体衬底的沟槽侧壁上形成选择栅极，以最小化选择栅极的侧向尺寸并保持沟道长度。所公开的方法包括以下步骤：在悬挂栅结构的一侧上的半导体衬底上形成沟槽; 在悬挂栅结构和沟槽的侧壁上形成多晶硅间介质层; 以及在多晶硅间介质层上形成多晶硅间隔物作为选择栅极。这种分裂栅极快速EEPROM电池可以产生弹道热电子，提高数据写入效率并降低写入电压。

10. 发明申请

US20050029575A1 Method of making the selection gate in a split-gate flash EEPROM cell and its structure 失效
公开(公告)号：US20050029575A1
公开(公告)日：2005-02-10
申请号：US10929396
申请日：2004-08-31
申请人： Wen-Ting Chu , Jack Yeh , Chrong-Jung Lin
发明人： Wen-Ting Chu , Jack Yeh , Chrong-Jung Lin
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/76 , H01L31/062 , H01L31/119
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/66553 , H01L29/7885
摘要： A method of making the selection gate in a split-gate flash EEPROM cell forms a selection gate on a trench sidewall of a semiconductor substrate to minimize the sidewise dimension of the selection gate and to maintain the channel length. The disclosed method includes the steps of: forming a trench on a semiconductor substrate on one side of a suspending gate structure; forming an inter polysilicon dielectric layer on the sidewall of the suspending gate structure and the trench; and forming a polysilicon spacer on the inter polysilicon dielectric layer as the selection gate. Such a split-gate flash EEPROM cell can produce ballistic hot electrons, improving the data writing efficiency and lowering the writing voltage.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式