专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070270003A1 POWER SUPPLY APPARATUS HAVING MULTIPLE POWER OUTPUT DEVICES 审中-公开
标题翻译：具有多个电力输出装置的电源装置
公开(公告)号：US20070270003A1
公开(公告)日：2007-11-22
申请号：US11534104
申请日：2006-09-21
申请人： Wen-Hsiang Lin , Szu-Lu Huang , Hung-Chang Hsieh
发明人： Wen-Hsiang Lin , Szu-Lu Huang , Hung-Chang Hsieh
IPC分类号： H01R13/648
CPC分类号： H01R13/6272 , H01R13/639
摘要： A power supply apparatus includes a main body, a power input device, a first power output device and a second power output device. The power input device is coupled to an input terminal of the main body. The first power output device includes a first cable and a first connector. The first cable is interconnected between a first output terminal of the main body and a first surface of the first connector. An extension part is extended from the first surface of the first connector. The second power output device includes a second cable and a second connector. A first surface of the second connector is suppressed by the extension part of the first connector to facilitate securely fixing the first connector and the second connector in a power socket, so that a regulated output voltage is outputted from the first and second output devices to the power socket.
摘要翻译：电源装置包括主体，电源输入装置，第一电力输出装置和第二电力输出装置。电源输入装置耦合到主体的输入端子。第一电力输出装置包括第一电缆和第一连接器。第一电缆在主体的第一输出端子和第一连接器的第一表面之间互连。延伸部分从第一连接器的第一表面延伸。第二电力输出装置包括第二电缆和第二连接器。第二连接器的第一表面被第一连接器的延伸部分抑制，以便将第一连接器和第二连接器牢固地固定在电源插座中，使得稳定的输出电压从第一和第二输出装置输出到电源插座。

2. 发明申请

US20080032539A1 ELECTRICAL CONNECTOR HAVING LATCHING MECHANISM 失效
标题翻译：具有锁紧机构的电气连接器
公开(公告)号：US20080032539A1
公开(公告)日：2008-02-07
申请号：US11534122
申请日：2006-09-21
申请人： Hung-Chuan Chen , Szu-Lu Huang , Hung-Chang Hsieh
发明人： Hung-Chuan Chen , Szu-Lu Huang , Hung-Chang Hsieh
IPC分类号： H01R13/627
CPC分类号： H01R13/6271
摘要： An electrical connector includes a plurality of pins, an isolation body and a latching mechanism. The isolation body has a specified side including a first portion, a second portion and an indentation. The second portion is higher than the first portion. The indentation is formed in the first portion and the second portion. The latching mechanism has an end fixed onto the second portion and extended above a bottom surface of the indentation, wherein the latching mechanism includes at least a fastening part.
摘要翻译：电连接器包括多个销，隔离体和闭锁机构。隔离体具有包括第一部分，第二部分和缩进的特定侧面。第二部分高于第一部分。凹陷形成在第一部分和第二部分中。锁定机构具有固定在第二部分上并在凹槽的底表面上方延伸的端部，其中锁定机构至少包括紧固部分。

3. 发明授权

US07335048B1 Electrical connector having latching mechanism 失效
标题翻译：具有闭锁机构的电连接器
公开(公告)号：US07335048B1
公开(公告)日：2008-02-26
申请号：US11534122
申请日：2006-09-21
申请人： Hung-Chuan Chen , Szu-Lu Huang , Hung-Chang Hsieh
发明人： Hung-Chuan Chen , Szu-Lu Huang , Hung-Chang Hsieh
IPC分类号： H01R13/627
CPC分类号： H01R13/6271
摘要： An electrical connector includes a plurality of pins, an isolation body and a latching mechanism. The isolation body has a specified side including a first portion, a second portion and an indentation. The second portion is higher than the first portion. The indentation is formed in the first portion and the second portion. The latching mechanism has an end fixed onto the second portion and extended above a bottom surface of the indentation, wherein the latching mechanism includes at least a fastening part.
摘要翻译：电连接器包括多个销，隔离体和闭锁机构。隔离体具有包括第一部分，第二部分和缩进的特定侧面。第二部分高于第一部分。凹陷形成在第一部分和第二部分中。锁定机构具有固定在第二部分上并在凹槽的底表面上方延伸的端部，其中锁定机构至少包括紧固部分。

4. 发明申请

US20130181320A1 Manufacturing Techniques for Workpieces with Varying Topographies 有权
标题翻译：具有不同形貌的工件制造技术
公开(公告)号：US20130181320A1
公开(公告)日：2013-07-18
申请号：US13350010
申请日：2012-01-13
申请人： Chun-Chang Chen , Shih-Chi Fu , Wang-Pen Mo , Hung-Chang Hsieh
发明人： Chun-Chang Chen , Shih-Chi Fu , Wang-Pen Mo , Hung-Chang Hsieh
IPC分类号： H01L29/00 , B44C1/22 , H01L21/311
CPC分类号： H01L21/0276 , H01L21/32139 , H01L21/823431 , H01L21/823456
摘要： Some embodiments relate to a method for processing a workpiece. In the method, an anti-reflective coating layer is provided over the workpiece. A first patterned photoresist layer, which has a first photoresist tone, is provided over the anti-reflective coating layer. A second patterned photoresist layer, which has a second photoresist tone opposite the first photoresist tone, is provided over the first patterned photoresist layer. An opening extends through the first and second patterned photoresist layers to allow a treatment to be applied to the workpiece through the opening. Other embodiments are also disclosed.
摘要翻译：一些实施例涉及用于处理工件的方法。在该方法中，在工件上方设有抗反射涂层。具有第一光致抗蚀剂色调的第一图案化光致抗蚀剂层设置在抗反射涂层上。在第一图案化光致抗蚀剂层上提供具有与第一光致抗蚀剂色调相反的第二光致抗蚀剂色调的第二图案化光致抗蚀剂层。开口延伸穿过第一和第二图案化的光致抗蚀剂层，以允许通过开口对工件施加处理。还公开了其他实施例。

5. 发明授权

US07897297B2 Method and system for optimizing intra-field critical dimension uniformity using a sacrificial twin mask 有权
标题翻译：使用牺牲双掩模优化场内临界尺寸均匀性的方法和系统
公开(公告)号：US07897297B2
公开(公告)日：2011-03-01
申请号：US11763269
申请日：2007-06-14
申请人： Chih-Ming Ke , Tsai-Sheng Gau , Shinn-Sheng Yu , Hung-Chang Hsieh
发明人： Chih-Ming Ke , Tsai-Sheng Gau , Shinn-Sheng Yu , Hung-Chang Hsieh
IPC分类号： G03F1/00
CPC分类号： G03F1/44 , G03F1/00
摘要： Disclosed is a method and a system for optimizing intra-field critical dimension of an integrated circuit. A first mask for an integrated circuit is provided comprising at least one device region. A second mask is provided by copying the first mask and a lithography operation is provided to the integrated circuit using the first and second masks, wherein the critical dimension of the integrated circuit is optimized using the second mask. The second mask comprises a plurality of sacrificial patterns, which may be a plurality of flat patterns or a plurality of grating patterns.
摘要翻译：公开了一种用于优化集成电路的场内临界尺寸的方法和系统。提供了集成电路的第一掩模，其包括至少一个器件区域。通过复制第一掩模来提供第二掩模，并且使用第一和第二掩模将光刻操作提供给集成电路，其中使用第二掩模优化集成电路的临界尺寸。第二掩模包括多个牺牲图案，其可以是多个平坦图案或多个光栅图案。

6. 发明授权

US06312876B1 Method for placing identifying mark on semiconductor wafer 有权
标题翻译：在半导体晶片上放置识别标记的方法
公开(公告)号：US06312876B1
公开(公告)日：2001-11-06
申请号：US09349842
申请日：1999-07-08
申请人： Yung-Sheng Huang , Hung-Chang Hsieh
发明人： Yung-Sheng Huang , Hung-Chang Hsieh
IPC分类号： G03F726
CPC分类号： H01L23/544 , H01L2223/54406 , H01L2223/54433 , H01L2223/54493 , H01L2924/0002 , H01L2924/00
摘要： A tool and method for placing an identifying mark on a semiconductor wafer has a bundle of optical fibers that can be illuminated in a pattern representing an identifying character. Light from the fibers is focused on a photoresist layer during wafer manufacture and a pattern of dots is etched into the wafer to represent the character. The dots are too small to be seen with the human eye but the character can be read by a human or by a machine. The character is etched as part of a conventional etch step in manufacturing the wafer and it is easily repeated as a series of manufacturing steps obscure the original mark.
摘要翻译：用于在半导体晶片上放置识别标记的工具和方法具有可以以表示识别字符的图案照亮的一束光纤。来自纤维的光在晶片制造期间聚焦在光致抗蚀剂层上，并且将点阵图案蚀刻到晶片中以表示字符。这些点太小，不能用人眼看到，但人物可以由人或机器读取。作为制造晶片的常规蚀刻步骤的一部分蚀刻该字符，并且由于一系列制造步骤遮蔽原始标记，因此容易重复该字符。

7. 发明授权

US5894350A Method of in line intra-field correction of overlay alignment 失效
标题翻译：在线校正叠加对齐的方法
公开(公告)号：US5894350A
公开(公告)日：1999-04-13
申请号：US097143
申请日：1998-06-12
申请人： Hung-Chang Hsieh , Shinn-Sheng Yu
发明人： Hung-Chang Hsieh , Shinn-Sheng Yu
IPC分类号： G03F7/20 , G03F9/00 , G01B11/00
CPC分类号： G03F7/70633 , G03F9/70
摘要： This invention describes a method of making intra-field corrections to the alignment of a step and repeat projection system used to expose image fields on an integrated circuit wafer. A first pattern having first image fields and first alignment marks is formed on a wafer. A mask having a second image field and second alignment marks is projected on the wafers, having a layer of photoresist formed thereon, using light which will not expose the photoresist. The relative location of the second alignment marks to the second image field is the same as the relative location of the first alignment marks to the first image field. A detectors, comprising an interferometer, determines the displacement vector between the first alignment marks and the corresponding second alignment marks. The displacement vectors are fed to a computer which computes a translation correction, a rotation correction, and a magnification correction for the alignment of the mask to the wafer. After the corrections are made the photoresist is exposed by projecting light which will expose the photoresist.
摘要翻译：本发明描述了对用于在集成电路晶片上曝光图像场的步骤和重复投影系统的对准进行场内校正的方法。具有第一图像场和第一对准标记的第一图案形成在晶片上。具有第二图像场和第二对准标记的掩模使用不会暴露光致抗蚀剂的光而投影在具有形成在其上的光致抗蚀剂层的晶片上。第二对准标记与第二图像场的相对位置与第一对准标记与第一图像场的相对位置相同。包括干涉仪的检测器确定第一对准标记和对应的第二对准标记之间的位移矢量。位移矢量被馈送到计算机，该计算机计算平移校正，旋转校正和用于掩模对晶片对准的倍率校正。在进行校正之后，光致抗蚀剂通过投射将暴露光致抗蚀剂的光曝光。

8. 发明授权

US08916482B2 Method of making a lithography mask 有权
标题翻译：制作光刻掩模的方法
公开(公告)号：US08916482B2
公开(公告)日：2014-12-23
申请号：US13437075
申请日：2012-04-02
申请人： Hsin-Chang Lee , Yun-Yue Lin , Hung-Chang Hsieh , Chia-Jen Chen , Yih-Chen Su , Ta-Cheng Lien , Anthony Yen
发明人： Hsin-Chang Lee , Yun-Yue Lin , Hung-Chang Hsieh , Chia-Jen Chen , Yih-Chen Su , Ta-Cheng Lien , Anthony Yen
IPC分类号： H01L21/31
CPC分类号： G03F1/76
摘要： A method of making a lithography mask with a stress-relief treatment is disclosed. The method includes providing a substrate and depositing an opaque layer on the substrate. The opaque layer is patterned to form a patterned mask. A stress-relief treatment is applied to the patterned mask by using an radiation exposure.
摘要翻译：公开了一种制造具有应力消除处理的光刻掩模的方法。该方法包括提供衬底并在衬底上沉积不透明层。将不透明层图案化以形成图案化掩模。通过使用辐射照射对图案化掩模施加应力消除处理。

9. 发明申请

US20130270667A1 Metal Grid in Backside Illumination Image Sensor Chips and Methods for Forming the Same 有权
标题翻译：金属网格背面照明图像传感器芯片及其形成方法
公开(公告)号：US20130270667A1
公开(公告)日：2013-10-17
申请号：US13449019
申请日：2012-04-17
申请人： Chih-Chien Wang , Chu-Wei Chang , Wang-Pen Mo , Hung-Chang Hsieh
发明人： Chih-Chien Wang , Chu-Wei Chang , Wang-Pen Mo , Hung-Chang Hsieh
IPC分类号： H01L31/0224 , H01L27/146 , H01L31/18
CPC分类号： H01L27/14621 , H01L27/14629 , H01L27/1464
摘要： A method includes forming a plurality of image sensors on a front side of a semiconductor substrate, and forming a dielectric layer on a backside of the semiconductor substrate. The dielectric layer is over the semiconductor substrate. The dielectric layer is patterned into a plurality of grid-filling regions, wherein each of the plurality of grid-filling regions overlaps one of the plurality of image sensors. A metal layer is formed on top surfaces and sidewalls of the plurality of grid-filling regions. The metal layer is etched to remove horizontal portions of the metal layer, wherein vertical portions of the metal layer remain after the step of etching to form a metal grid. A transparent material is filled into grid openings of the metal grid.
摘要翻译：一种方法包括在半导体衬底的正面上形成多个图像传感器，并在半导体衬底的背面形成电介质层。电介质层在半导体衬底之上。电介质层被图案化成多个栅格填充区域，其中多个网格填充区域中的每一个与多个图像传感器之一重叠。金属层形成在多个网格填充区域的顶表面和侧壁上。蚀刻金属层以去除金属层的水平部分，其中金属层的垂直部分在蚀刻步骤之后保留以形成金属网格。将透明材料填充到金属网格的网格开口中。

10. 发明申请

US20130207163A1 Semiconductor Devices and Manufacturing Methods Thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130207163A1
公开(公告)日：2013-08-15
申请号：US13370132
申请日：2012-02-09
申请人： Chun-Chang Chen , Shun-Shing Yang , Shih-Chi Fu , Wang-Pen Mo , Hung-Chang Hsieh
发明人： Chun-Chang Chen , Shun-Shing Yang , Shih-Chi Fu , Wang-Pen Mo , Hung-Chang Hsieh
IPC分类号： H01L27/04 , H01L21/20 , H01L29/02
CPC分类号： H01L21/823437 , H01L21/0274 , H01L21/32139 , H01L27/1052
摘要： Semiconductor devices and manufacturing methods thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece with a first region having a plurality of first features and a second region having a plurality of second features proximate the first region. The first region and the second region share a patterning overlap region disposed between the first region and the second region. The patterning overlap region includes a residue feature with an aspect ratio of about 4 or less.
摘要翻译：公开了半导体器件及其制造方法。在一个实施例中，半导体器件包括具有多个第一特征的第一区域的工件和具有靠近第一区域的多个第二特征的第二区域。第一区域和第二区域共享布置在第一区域和第二区域之间的图案化重叠区域。图案重叠区域包括长宽比为约4或更小的残留特征。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式