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1. 发明授权

US08726208B2 DFM improvement utility with unified interface 有权
标题翻译：具有统一接口的DFM改进实用程序
公开(公告)号：US08726208B2
公开(公告)日：2014-05-13
申请号：US13186241
申请日：2011-07-19
申请人： Wen-Hao Chen , Zhe-Wei Jiang , Chung-Min Fu
发明人： Wen-Hao Chen , Zhe-Wei Jiang , Chung-Min Fu
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A utility includes a design-for-manufacturing (DFM) checker configured to check layout patterns of an integrated circuit, and a layout change instruction generator configured to generate a layout change instruction based on a result generated by the DFM checker. The DFM checker and the layout change instruction generator are embodied on a non-transitory storage media. The layout change instruction specifies an identifier of a layout pattern among the layout patterns, and a respective layout change to be performed on the layout pattern.
摘要翻译：一种实用程序包括：被配置为检查集成电路的布局图案的制造设计（DFM）检查器，以及布局改变指令生成器，其被配置为基于由DFM检验器生成的结果生成布局改变指令。 DFM检查器和布局改变指令生成器体现在非暂时性的存储介质上。布局改变指令指定布局图案之间的布局图案的标识符以及要在布局图案上执行的各自的布局改变。

2. 发明申请

US20130024832A1 DFM Improvement Utility with Unified Interface 有权
标题翻译：带统一接口的DFM改进实用程序
公开(公告)号：US20130024832A1
公开(公告)日：2013-01-24
申请号：US13186241
申请日：2011-07-19
申请人： Wen-Hao Chen , Zhe-Wei Jiang , Chung-Min Fu
发明人： Wen-Hao Chen , Zhe-Wei Jiang , Chung-Min Fu
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A utility includes a design-for-manufacturing (DFM) checker configured to check layout patterns of an integrated circuit, and a layout change instruction generator configured to generate a layout change instruction based on a result generated by the DFM checker. The DFM checker and the layout change instruction generator are embodied on a non-transitory storage media. The layout change instruction specifies an identifier of a layout pattern among the layout patterns, and a respective layout change to be performed on the layout pattern.
摘要翻译：一种实用程序包括：被配置为检查集成电路的布局图案的制造设计（DFM）检查器，以及布局改变指令生成器，其被配置为基于由DFM检验器生成的结果生成布局改变指令。 DFM检查器和布局改变指令生成器体现在非暂时性的存储介质上。布局改变指令指定布局图案之间的布局图案的标识符以及要在布局图案上执行的相应布局改变。

3. 发明申请

US20140001638A1 Semiconductor Devices and Methods of Manufacture Thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140001638A1
公开(公告)日：2014-01-02
申请号：US13540464
申请日：2012-07-02
申请人： Chung-Min Fu , Wen-Hao Chen , Dian-Hau Chen
发明人： Chung-Min Fu , Wen-Hao Chen , Dian-Hau Chen
IPC分类号： H01L23/50 , H01L21/306
CPC分类号： H01L21/768 , H01L21/76816 , H01L23/5283 , H01L23/5286 , H01L23/538 , H01L2924/0002 , H01L2924/01079 , H01L2924/00
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece and a plurality of first conductive lines disposed over the workpiece in a metallization layer. A plurality of second conductive lines is disposed over the workpiece in the metallization layer. The plurality of second conductive lines comprises a greater vertical height in a cross-sectional view of the workpiece than a vertical height of the plurality of first conductive lines.
摘要翻译：公开了半导体器件及其制造方法。在一个实施例中，半导体器件包括工件和在金属化层中设置在工件上的多个第一导电线。多个第二导线设置在金属化层中的工件上方。多个第二导电线在工件的横截面视图中包括比多个第一导电线的垂直高度更大的垂直高度。

4. 发明授权

US08786094B2 Semiconductor devices and methods of manufacture thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08786094B2
公开(公告)日：2014-07-22
申请号：US13540464
申请日：2012-07-02
申请人： Chung-Min Fu , Wen-Hao Chen , Dian-Hau Chen
发明人： Chung-Min Fu , Wen-Hao Chen , Dian-Hau Chen
IPC分类号： H01L23/50 , H01L21/768 , H01L23/538
CPC分类号： H01L21/768 , H01L21/76816 , H01L23/5283 , H01L23/5286 , H01L23/538 , H01L2924/0002 , H01L2924/01079 , H01L2924/00
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece and a plurality of first conductive lines disposed over the workpiece in a metallization layer. A plurality of second conductive lines is disposed over the workpiece in the metallization layer. The plurality of second conductive lines comprises a greater vertical height in a cross-sectional view of the workpiece than a vertical height of the plurality of first conductive lines.
摘要翻译：公开了半导体器件及其制造方法。在一个实施例中，半导体器件包括工件和在金属化层中设置在工件上的多个第一导电线。多个第二导线设置在金属化层中的工件上方。多个第二导电线在工件的横截面视图中包括比多个第一导电线的垂直高度更大的垂直高度。

5. 发明授权

US08601408B2 Method and system for replacing a pattern in a layout 有权
公开(公告)号：US08601408B2
公开(公告)日：2013-12-03
申请号：US13269757
申请日：2011-10-10
申请人： Huang-Yu Chen , Yuan-Te Hou , Chung-Min Fu , Chung-Hsing Wang , Wen-Hao Chen , Yi-Kan Cheng
发明人： Huang-Yu Chen , Yuan-Te Hou , Chung-Min Fu , Chung-Hsing Wang , Wen-Hao Chen , Yi-Kan Cheng
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.

6. 发明授权

US09262568B2 Dummy pattern performance aware analysis and implementation 有权
标题翻译：虚拟模式性能意识分析和实现
公开(公告)号：US09262568B2
公开(公告)日：2016-02-16
申请号：US12763889
申请日：2010-04-20
申请人： Chung-Min Fu , Meng-Fu You
发明人： Chung-Min Fu , Meng-Fu You
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5031 , G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： Embodiments of the present invention are a system, a computer program product, and a method for implementing an integrated circuit design. The method for implementing an integrated circuit design includes accessing an original electronic representation of an integrated circuit layout from a first user file, and accessing a defined sensitivity index that characterizes an impact of the dummy pattern on the functional component. The impact of the dummy pattern on the functional component is analyzed and it is determined whether the impact is within a limit of the sensitivity index. One of a plurality of features of the dummy pattern is adjusted if the impact is not within the limit to form a generated electronic representation of a modified integrated circuit layout, and the generated electronic representation is output to a second user file. The integrated circuit layout includes a dummy pattern and a functional component.
摘要翻译：本发明的实施例是一种用于实现集成电路设计的系统，计算机程序产品和方法。用于实现集成电路设计的方法包括从第一用户文件访问集成电路布局的原始电子表示，以及访问表征虚拟图案对功能组件的影响的定义的灵敏度指标。分析虚拟模式对功能组件的影响，确定影响是否在灵敏度指标的极限之内。如果影响不在限制内以形成经修改的集成电路布局的生成的电子表示，则调整虚拟图案的多个特征之一，并且所生成的电子表示被输出到第二用户文件。集成电路布局包括虚拟图案和功能部件。

7. 发明授权

US08577717B2 Method and system for predicting shrinkable yield for business assessment of integrated circuit design shrink 有权
标题翻译：集成电路设计业务评估收缩收益预测方法与系统收缩
公开(公告)号：US08577717B2
公开(公告)日：2013-11-05
申请号：US11486521
申请日：2006-07-13
申请人： Chung-Min Fu , Yu-Chyi Harn
发明人： Chung-Min Fu , Yu-Chyi Harn
IPC分类号： G06Q99/00 , G06Q30/02 , G06Q10/04
CPC分类号： G06Q30/0283 , G06Q10/04
摘要： A method and a system for predicting shrinkable yield for business assessment of integrated circuit design shrink are provided. An assessment system is provided to determine cost benefits of a design shrink of an integrated circuit chip. A cost benefit analysis across different design shrink technologies is provided early in the process, so that business decisions regarding employment of design shrinks can be made as early as possible.
摘要翻译：提供了一种用于预测集成电路设计收缩业务评估的收缩收益的方法和系统。提供评估系统来确定集成电路芯片设计收缩的成本优势。在早期提供不同设计收缩技术的成本效益分析，以便尽可能早地制定有关就业设计缩减的业务决策。

8. 发明授权

US09311440B2 System and method of electromigration avoidance for automatic place-and-route 有权
标题翻译：自动放置路由的电迁移避免系统和方法
公开(公告)号：US09311440B2
公开(公告)日：2016-04-12
申请号：US13468055
申请日：2012-05-10
申请人： Jerry Kao , King-Ho Tam , Meng-Xiang Lee , Li-Chung Hsu , Chi-Yeh Yu , Chung-Min Fu , Chung-Hsing Wang
发明人： Jerry Kao , King-Ho Tam , Meng-Xiang Lee , Li-Chung Hsu , Chi-Yeh Yu , Chung-Min Fu , Chung-Hsing Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077 , G06F2217/76
摘要： A method includes identifying at least one local power segment of a circuit, estimating at least one performance parameter of the at least one power segment based on a computer-based simulation of the circuit, and changing a design of the circuit based on at least one electromigration avoidance strategy if the at least one parameter is greater than or equal to a threshold value. A data file representing the circuit is stored if the at least one parameter is less than the threshold value.
摘要翻译：一种方法包括识别电路的至少一个局部电力部分，基于电路的基于计算机的仿真来估计所述至少一个电力部分的至少一个性能参数，以及基于至少一个电路来改变所述电路的设计如果至少一个参数大于或等于阈值，则电迁移避免策略。如果至少一个参数小于阈值，则存储表示电路的数据文件。

9. 发明授权

US08677292B2 Cell-context aware integrated circuit design 有权
标题翻译：电池背景感知集成电路设计
公开(公告)号：US08677292B2
公开(公告)日：2014-03-18
申请号：US12708098
申请日：2010-02-18
申请人： Chung-Min Fu , Yen-Pin Chen , Yung-Fong Lu
发明人： Chung-Min Fu , Yen-Pin Chen , Yung-Fong Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of designing an integrated circuit includes providing a standard cell database including a plurality of standard cells; providing an index file having cell-context information indexed to the plurality of standard cells; retrieving the cell-context information of one of the plurality of standard cells from the cell-context file; and applying the index information to a design of the integrated circuit.
摘要翻译：设计集成电路的方法包括提供包括多个标准单元的标准单元数据库; 提供具有索引到所述多个标准单元的单元格上下文信息的索引文件; 从所述小区上下文文件中检索所述多个标准单元之一的小区上下文信息; 以及将所述索引信息应用于所述集成电路的设计。

10. 发明申请

US20060230371A1 Alternative methodology for defect simulation and system 有权
标题翻译：缺陷模拟和系统的替代方法
公开(公告)号：US20060230371A1
公开(公告)日：2006-10-12
申请号：US11099834
申请日：2005-04-06
申请人： Jui-Jung Yan , Chung-Min Fu , Ricky Yang
发明人： Jui-Jung Yan , Chung-Min Fu , Ricky Yang
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5081
摘要： A system for defect simulation is provided. A defect layout generator generates a defect layout comprising a given number of spot defects of a given size. A processor first compares the defect layout and a provided circuit layout comprising a plurality of conductive regions. The processor further determines whether the spot defects are located on the conductive regions, and determines whether short-circuits and/or open circuits are caused by the spot defects in the conductive regions.
摘要翻译：提供了一种用于缺陷模拟的系统。缺陷布局生成器生成包括给定尺寸的给定数量的斑点缺陷的缺陷布局。处理器首先比较缺陷布局和提供的包括多个导电区域的电路布局。处理器还确定斑点缺陷是否位于导电区域上，并且确定短路和/或开路是否由导电区域中的斑点缺陷引起。

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