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1. 发明申请

US20070187845A1 Integrated Stress Relief Pattern and Registration Structure 有权
标题翻译：综合应力消除模式和注册结构
公开(公告)号：US20070187845A1
公开(公告)日：2007-08-16
申请号：US11695665
申请日：2007-04-03
申请人： Chung-min Fu , Huang-Sheng Lin , Yu-Chyi Harn , Hsien-Wei Chen
发明人： Chung-min Fu , Huang-Sheng Lin , Yu-Chyi Harn , Hsien-Wei Chen
IPC分类号： H01L23/544 , H01L21/76
CPC分类号： H01L23/585 , H01L23/544 , H01L23/562 , H01L2223/5442 , H01L2223/5448 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor die having an integrated circuit region formed in a substrate comprises at least one die-corner-circuit-forbidden (DCCF) region disposed in the substrate, proximate to the integrated circuit region; and at least one registration feature formed within the at least one DCCF region. The at least one registration feature comprises a structure selected from the group consisting of a laser fuse mark, an alignment mark, and a monitor mark.
摘要翻译：具有形成在基板中的集成电路区域的半导体管芯包括：靠近集成电路区域设置在基板中的至少一个管芯拐角电路禁止（DCCF）区域; 以及形成在所述至少一个DCCF区域内的至少一个配准特征。所述至少一个配准特征包括从由激光熔丝标记，对准标记和监视标记组成的组中选择的结构。

2. 发明申请

US20070276770A1 Method and system for predicting shrinkable yield for business assessment of integrated circuit design shrink 有权
标题翻译：集成电路设计业务评估收缩收益预测方法与系统收缩
公开(公告)号：US20070276770A1
公开(公告)日：2007-11-29
申请号：US11486521
申请日：2006-07-13
申请人： Chung-Min Fu , Yu-Chyi Harn
发明人： Chung-Min Fu , Yu-Chyi Harn
IPC分类号： G06F17/00
CPC分类号： G06Q30/0283 , G06Q10/04
摘要： Aspects of the present invention provide a method and a system for predicting shrinkable yield for business assessment of integrated circuit design shrink. An assessment system is provided to determine cost benefits of a design shrink of an integrated circuit chip. A cost benefit analysis across different design shrink technologies is provided early in the process, so that business decisions regarding employment of design shrinks can be made as early as possible.
摘要翻译：本发明的方面提供了一种用于预测集成电路设计业务评估收缩收益的方法和系统。提供评估系统来确定集成电路芯片设计收缩的成本优势。在早期提供不同设计收缩技术的成本效益分析，以便尽可能早地制定有关就业设计缩减的业务决策。

3. 发明授权

US08577717B2 Method and system for predicting shrinkable yield for business assessment of integrated circuit design shrink 有权
标题翻译：集成电路设计业务评估收缩收益预测方法与系统收缩
公开(公告)号：US08577717B2
公开(公告)日：2013-11-05
申请号：US11486521
申请日：2006-07-13
申请人： Chung-Min Fu , Yu-Chyi Harn
发明人： Chung-Min Fu , Yu-Chyi Harn
IPC分类号： G06Q99/00 , G06Q30/02 , G06Q10/04
CPC分类号： G06Q30/0283 , G06Q10/04
摘要： A method and a system for predicting shrinkable yield for business assessment of integrated circuit design shrink are provided. An assessment system is provided to determine cost benefits of a design shrink of an integrated circuit chip. A cost benefit analysis across different design shrink technologies is provided early in the process, so that business decisions regarding employment of design shrinks can be made as early as possible.
摘要翻译：提供了一种用于预测集成电路设计收缩业务评估的收缩收益的方法和系统。提供评估系统来确定集成电路芯片设计收缩的成本优势。在早期提供不同设计收缩技术的成本效益分析，以便尽可能早地制定有关就业设计缩减的业务决策。

4. 发明授权

US07378720B2 Integrated stress relief pattern and registration structure 有权
标题翻译：综合应力消除模式和注册结构
公开(公告)号：US07378720B2
公开(公告)日：2008-05-27
申请号：US11695665
申请日：2007-04-03
申请人： Chung-min Fu , Huang-Sheng Lin , Yu-Chyi Harn , Hsien-Wei Chen
发明人： Chung-min Fu , Huang-Sheng Lin , Yu-Chyi Harn , Hsien-Wei Chen
IPC分类号： H01L23/544 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/585 , H01L23/544 , H01L23/562 , H01L2223/5442 , H01L2223/5448 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor die having an integrated circuit region formed in a substrate comprises at least one die-corner-circuit-forbidden (DCCF) region disposed in the substrate, proximate to the integrated circuit region; and at least one registration feature formed within the at least one DCCF region. The at least one registration feature comprises a structure selected from the group consisting of a laser fuse mark, an alignment mark, and a monitor mark.
摘要翻译：具有形成在基板中的集成电路区域的半导体管芯包括：靠近集成电路区域设置在基板中的至少一个管芯拐角电路禁止（DCCF）区域; 以及形成在所述至少一个DCCF区域内的至少一个配准特征。所述至少一个配准特征包括从由激光熔丝标记，对准标记和监视标记组成的组中选择的结构。

5. 发明授权

US07202550B2 Integrated stress relief pattern and registration structure 有权
标题翻译：综合应力消除模式和注册结构
公开(公告)号：US07202550B2
公开(公告)日：2007-04-10
申请号：US10983425
申请日：2004-11-08
申请人： Chung-min Fu , Huang-Sheng Lin , Yu-Chyi Harn , Hsien-Wei Chen
发明人： Chung-min Fu , Huang-Sheng Lin , Yu-Chyi Harn , Hsien-Wei Chen
IPC分类号： H01L23/544 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/585 , H01L23/544 , H01L23/562 , H01L2223/5442 , H01L2223/5448 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor die having an integrated circuit region formed in a substrate comprises at least one die-corner-circuit-forbidden (DCCF) region disposed in the substrate, proximate to the integrated circuit region; and at least one registration feature formed within the at least one DCCF region. The at least one registration feature comprises a structure selected from the group consisting of a laser fuse mark, an alignment mark, and a monitor mark.
摘要翻译：具有形成在基板中的集成电路区域的半导体管芯包括：靠近集成电路区域设置在基板中的至少一个管芯拐角电路禁止（DCCF）区域; 以及形成在所述至少一个DCCF区域内的至少一个配准特征。所述至少一个配准特征包括从由激光熔丝标记，对准标记和监视标记组成的组中选择的结构。

6. 发明申请

US20050263855A1 Integrated stress relief pattern and registration structure 有权
标题翻译：综合应力消除模式和注册结构
公开(公告)号：US20050263855A1
公开(公告)日：2005-12-01
申请号：US10983425
申请日：2004-11-08
申请人： Chung-min Fu , Huang-Sheng Lin , Yu-Chyi Harn , Hsien-Wei Chen
发明人： Chung-min Fu , Huang-Sheng Lin , Yu-Chyi Harn , Hsien-Wei Chen
IPC分类号： H01L23/00 , H01L23/544 , H01L23/58 , H01R13/627
CPC分类号： H01L23/585 , H01L23/544 , H01L23/562 , H01L2223/5442 , H01L2223/5448 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor die having an integrated circuit region formed in a substrate comprises at least one die-corner-circuit-forbidden (DCCF) region disposed in the substrate, proximate to the integrated circuit region; and at least one registration feature formed within the at least one DCCF region. The at least one registration feature comprises a structure selected from the group consisting of a laser fuse mark, an alignment mark, and a monitor mark.
摘要翻译：具有形成在基板中的集成电路区域的半导体管芯包括：靠近集成电路区域设置在基板中的至少一个管芯拐角电路禁止（DCCF）区域; 以及形成在所述至少一个DCCF区域内的至少一个配准特征。所述至少一个配准特征包括从由激光熔丝标记，对准标记和监视标记组成的组中选择的结构。

7. 发明授权

US08786054B2 Structure for integrated circuit alignment 有权
标题翻译：集成电路对准的结构
公开(公告)号：US08786054B2
公开(公告)日：2014-07-22
申请号：US12619460
申请日：2009-11-16
申请人： Yu-Chyi Harn , Sophia Wang , Chun-Hung Lin , Hsien-Wei Chen , Ming-Yen Chiu
发明人： Yu-Chyi Harn , Sophia Wang , Chun-Hung Lin , Hsien-Wei Chen , Ming-Yen Chiu
IPC分类号： H01L23/48
CPC分类号： G03F9/7084 , H01L2924/0002 , H01L2924/00
摘要： A method and device for pattern alignment are disclosed. The device can include an exposure field; a die within the exposure field, wherein the die comprises an integrated circuit region, a seal ring region, and a corner stress relief region; and a die alignment mark disposed between the seal ring region and the corner stress relief region.
摘要翻译：公开了一种用于图案对准的方法和装置。该装置可以包括曝光场; 在所述曝光场内的管芯，其中所述管芯包括集成电路区域，密封环区域和拐角应力释放区域; 以及设置在密封环区域和角部应力消除区域之间的模具对准标记。

8. 发明申请

US20110115057A1 DESIGN STRUCTURE FOR INTEGRATED CIRCUIT ALIGNMENT 有权
标题翻译：集成电路对准的设计结构
公开(公告)号：US20110115057A1
公开(公告)日：2011-05-19
申请号：US12619460
申请日：2009-11-16
申请人： Yu-Chyi Harn , Sophia Wang , Chun-Hung Lin , Hsien-Wei Chen , Ming-Yen Chiu
发明人： Yu-Chyi Harn , Sophia Wang , Chun-Hung Lin , Hsien-Wei Chen , Ming-Yen Chiu
IPC分类号： H01L23/544 , H01L21/71 , H01L21/26
CPC分类号： G03F9/7084 , H01L2924/0002 , H01L2924/00
摘要： A method and device for pattern alignment are disclosed. The device can include an exposure field; a die within the exposure field, wherein the die comprises an integrated circuit region, a seal ring region, and a corner stress relief region; and a die alignment mark disposed between the seal ring region and the corner stress relief region.
摘要翻译：公开了一种用于图案对准的方法和装置。该装置可以包括曝光场; 在所述曝光场内的管芯，其中所述管芯包括集成电路区域，密封环区域和拐角应力释放区域; 以及设置在密封环区域和角部应力消除区域之间的模具对准标记。

9. 发明授权

US06517637B1 Method for cleaning wafers with ionized water 失效
标题翻译：用离子水清洗晶片的方法
公开(公告)号：US06517637B1
公开(公告)日：2003-02-11
申请号：US08899176
申请日：1997-07-23
申请人： Chiang Fu , Yu-Chyi Harn
发明人： Chiang Fu , Yu-Chyi Harn
IPC分类号： B08B704
CPC分类号： H01L21/02052 , C11D7/08 , C11D7/265 , C11D11/0047
摘要： The present invention provides a method for cleaning wafer surfaces in a scrubber by ion doped deionized water without the electrostatic discharge problem. The method can be carried out by first doping a quantity of deionized water with at least one species of ions from the group consisting of OH−, F−, Cl−, NH4+ and H+ any other suitable ions. The added ions significantly reduce the resistivity of the DI water such that DI water is no longer a perfect insulator and therefore, when sprayed onto wafer surfaces covered by an insulating material, the generation of electrostatic charges is significantly reduced. As a result, the undesirable effect of electrostatic discharge can be significantly reduced or eliminated and the yield of the wafer fabrication process can be improved.
摘要翻译：本发明提供了一种用于通过离子掺杂的去离子水清洁洗涤器中的晶片表面而没有静电放电问题的方法。该方法可以通过首先用至少一种离子从OH-，F-，Cl-，NH4 +和H +任意其它合适的离子掺杂一定量的去离子水进行。添加的离子显着降低去离子水的电阻率，使得去离子水不再是完美的绝缘体，因此当喷涂在被绝缘材料覆盖的晶片表面上时，静电电荷的产生显着降低。结果，可以显着地减少或消除静电放电的不良影响，并且可以提高晶片制造工艺的产量。

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