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1. 发明授权

US06459428B1 Programmable sample filtering for image rendering 有权
标题翻译：用于图像渲染的可编程样本滤波
公开(公告)号：US06459428B1
公开(公告)日：2002-10-01
申请号：US09970077
申请日：2001-10-03
申请人： Wayne Eric Burk , Yan Y. Tang , Michael G. Lavelle , Philip C. Leung , Michael F. Deering , Ranjit S. Oberoi
发明人： Wayne Eric Burk , Yan Y. Tang , Michael G. Lavelle , Philip C. Leung , Michael F. Deering , Ranjit S. Oberoi
IPC分类号： G06T1500
CPC分类号： G06T11/001 , G06T5/20 , G06T15/503
摘要： A graphics system configured to perform programmable filtering of samples to generate pixel values. The graphics system comprises a frame buffer, an accelerator unit and a video output processor. The accelerator unit receives graphics primitives, renders samples for the graphics primitives, and stores the rendered samples into a sample area of the frame buffer. The accelerator unit subsequently reads the samples from the sample area of the frame buffer, and filters the samples with a programmable filter having a programmable support region. The resulting pixel values are stored in a pixel area of the frame buffer. The video output processor reads the pixel values from the pixel area and converts the pixel values into a video signal which is provided to a video output port.
摘要翻译：被配置为对样本执行可编程滤波以生成像素值的图形系统。图形系统包括帧缓冲器，加速器单元和视频输出处理器。加速器单元接收图形基元，呈现图形基元的样本，并将渲染的样本存储在帧缓冲器的采样区域中。加速器单元随后从帧缓冲器的采样区域读取样本，并且用具有可编程支持区域的可编程滤波器对样本进行滤波。所得到的像素值被存储在帧缓冲器的像素区域中。视频输出处理器从像素区域读取像素值，并将像素值转换为提供给视频输出端口的视频信号。

2. 发明授权

US06795081B2 Sample cache for supersample filtering 有权
标题翻译：超示例过滤示例缓存
公开(公告)号：US06795081B2
公开(公告)日：2004-09-21
申请号：US09861479
申请日：2001-05-18
申请人： Michael G. Lavelle , Philip C. Leung , Yan Y. Tang
发明人： Michael G. Lavelle , Philip C. Leung , Yan Y. Tang
IPC分类号： G09G536
CPC分类号： G06T1/60
摘要： A system and method capable of super-sampling and performing super-sample convolution are disclosed. In one embodiment, the system may comprise a graphics processor, a frame buffer, a sample cache, and a sample-to-pixel calculation unit. The graphics processor may be configured to generate a plurality of samples. The frame buffer, which is coupled to the graphics processor, may be configured to store the samples in a sample buffer. The samples may be positioned according to a regular grid, a perturbed regular grid, or a stochastic grid. The sample-to-pixel calculation unit is programmable to select a variable number of stored samples from the frame buffer, copy the selected samples to a sample cache, and filter a set of the selected samples into an output pixel. The sample-to-pixel calculation unit retains those samples in the sample cache that will be reused in a subsequent pixel calculation and replaces those samples no longer required with new samples for another filter calculation.
摘要翻译：公开了能够超采样和执行超采样卷积的系统和方法。在一个实施例中，系统可以包括图形处理器，帧缓冲器，采样高速缓存和采样到像素计算单元。图形处理器可以被配置为生成多个采样。耦合到图形处理器的帧缓冲器可以被配置为将样本存储在采样缓冲器中。样本可以根据规则网格，扰动的规则网格或随机网格来定位。样本到像素计算单元是可编程的，以从帧缓冲器中选择可变数量的存储样本，将所选样本复制到样本高速缓存，并将所选择的样本集合过滤到输出像素中。样本到像素计算单元将样本缓存中保留的样本保留在随后的像素计算中重新使用，并将不再需要的样本替换为另一个滤波器计算的新采样。

3. 发明授权

US06795078B2 Parallel read with source-clear operation 有权
标题翻译：并行读取与源清除操作
公开(公告)号：US06795078B2
公开(公告)日：2004-09-21
申请号：US10066397
申请日：2002-01-31
申请人： Michael G. Lavelle , Ewa M. Kubalska , Yan Y. Tang
发明人： Michael G. Lavelle , Ewa M. Kubalska , Yan Y. Tang
IPC分类号： G06G1318
CPC分类号： G09G5/363 , G06F12/0875 , G06F12/0891 , G06F12/0897 , G09G5/393 , G09G5/395 , G09G2360/121 , G09G2360/126 , G09G2360/127
摘要： A memory interface controls read and write accesses to a memory device. The memory device includes a level-one cache, level-two cache and storage cell array. The memory interface includes a data request processor (DRP), a memory control processor (MCP) and a block cleansing unit (BCU). The MCP controls transfers between the storage cell array, the level-two cache and the level-one cache. In response to a read request with associated read clear indication, the DRP controls a read from a level-one cache block, updates bits in a corresponding dirty tag, and sets a mode indicator of the dirty tag to a the read clear mode. The modified dirty tag bits and mode indicator are signals to the BCU that the level-one cache block requires a source clear operation. The BCU commands the transfer of data from a color fill block in the level-one cache to the level-two cache.
摘要翻译：存储器接口控制对存储器件的读写访问。存储器件包括一级缓存，二级缓存和存储单元阵列。存储器接口包括数据请求处理器（DRP），存储器控制处理器（MCP）和块清理单元（BCU）。 MCP控制存储单元阵列，二级缓存和一级缓存之间的传输。响应于具有关联的读取清除指示的读取请求，DRP控制从一级缓存块的读取，更新相应脏标签中的比特，并将脏标签的模式指示符设置为读取清除模式。修改的脏标签位和模式指示符是到BCU的信号，一级缓存块需要源清除操作。 BCU命令将数据从一级缓存中的颜色填充块传送到二级缓存。

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