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1. 发明申请

US20110221742A1 Scalable High Performance 3D Graphics 有权
标题翻译：可扩展的高性能3D图形
公开(公告)号：US20110221742A1
公开(公告)日：2011-09-15
申请号：US12898249
申请日：2010-10-05
申请人： Michael F. Deering , Michael G. Lavelle
发明人： Michael F. Deering , Michael G. Lavelle
IPC分类号： G06T15/00
CPC分类号： G06T1/20 , G06T1/60 , G06T5/002 , G06T15/005
摘要： A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).
摘要翻译：高速环形拓扑。在一个实施例中，需要两种基本芯片类型：“绘图”芯片，LoopDraw和“接口”芯片，LoopInterface。每个芯片都有一组引脚，支持相同的高速点对点输入和输出环互连接口：LoopLink。 LoopDraw芯片使用额外的引脚连接到形成高带宽本地存储器子系统的多个标准存储器。 LoopInterface芯片使用额外的引脚来支持高速主机主机接口，至少一个视频输出接口，以及可能与其他LoopInterface芯片的附加非本地互连。

2. 发明授权

US07502470B2 Method and apparatus for content protection within an open architecture system 有权
标题翻译：开放式架构系统内容保护的方法和装置
公开(公告)号：US07502470B2
公开(公告)日：2009-03-10
申请号：US10679055
申请日：2003-10-03
申请人： James G. Hanko , Michael G. Lavelle , James D. Lyle , J. Duane Northcutt
发明人： James G. Hanko , Michael G. Lavelle , James D. Lyle , J. Duane Northcutt
IPC分类号： H04N7/16
CPC分类号： H04N5/913 , G06F21/10 , G06F21/85 , G11B20/00086 , G11B20/0021 , H04L63/0464 , H04L63/0823 , H04L63/0869 , H04L2463/101 , H04N7/088 , H04N7/1675 , H04N21/2541 , H04N21/4334 , H04N21/4367 , H04N21/4405 , H04N21/4408 , H04N21/4627 , H04N21/835
摘要： In a class of embodiments, the invention is an open computing system (e.g., a PC) in which a protected, closed subsystem is embedded. The closed subsystem typically includes multiple parts that ensure that content protection keys and protected content are never revealed outside the closed subsystem. Content (e.g., high-definition digital video) that enters the closed subsystem (and is typically decrypted and re-encrypted within the closed subsystem) is afforded a similar level of protection within the open system as can be obtained in standalone closed systems. Other aspects of the invention are methods for protecting content within an open computing system, a closed system (or disk drive thereof) configured to be embedded in an open computing system, and circuitry configured to be embedded in an open computing system for combining the output of a closed subsystem with other output (e.g., graphics and/or audio output) of the open computing system.
摘要翻译：在一类实施例中，本发明是其中嵌入了受保护的封闭子系统的开放式计算系统（例如，PC）。封闭的子系统通常包括多个部分，确保内容保护密钥和受保护内容永远不会在封闭子系统外部显示。进入封闭子系统（并且通常在封闭子系统内被解密并重新加密）的内容（例如，高清数字视频）在独立的封闭系统中可获得与开放系统相似的保护水平。本发明的其他方面是用于保护开放式计算系统内的内容的方法，被配置为嵌入在开放式计算系统中的封闭系统（或其盘驱动器）以及被配置为嵌入开放式计算系统中的组合的输出的方法，具有开放式计算系统的其他输出（例如，图形和/或音频输出）的封闭子系统。

3. 发明授权

US07379067B2 Scalable high performance 3D graphics 有权
标题翻译：可扩展的高性能3D图形
公开(公告)号：US07379067B2
公开(公告)日：2008-05-27
申请号：US11305474
申请日：2005-12-15
申请人： Michael F. Deering , Michael G. Lavelle
发明人： Michael F. Deering , Michael G. Lavelle
IPC分类号： G06T1/20 , G06T1/60 , G06F15/16
CPC分类号： G06T1/20 , G06T1/60 , G06T5/002 , G06T15/005
摘要： A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).
摘要翻译：高速环形拓扑。在一个实施例中，需要两种基本芯片类型：“绘图”芯片，LoopDraw和“接口”芯片，LoopInterface。每个芯片都有一组引脚，支持相同的高速点对点输入和输出环互连接口：LoopLink。 LoopDraw芯片使用额外的引脚连接到形成高带宽本地存储器子系统的多个标准存储器。 LoopInterface芯片使用额外的引脚来支持高速主机主机接口，至少一个视频输出接口，以及可能与其他LoopInterface芯片的附加非本地互连。

4. 发明授权

US07145570B2 Magnified texture-mapped pixel performance in a single-pixel pipeline 有权
公开(公告)号：US07145570B2
公开(公告)日：2006-12-05
申请号：US10317599
申请日：2002-12-12
申请人： Brian D. Emberling , Michael G. Lavelle
发明人： Brian D. Emberling , Michael G. Lavelle
IPC分类号： G09G5/00
CPC分类号： G06T15/005 , G06T15/04
摘要： A system and a method for improving magnified texture-mapped pixel performance in a single-pixel pipeline. A plurality of textured pixel addresses corresponding to a plurality of pixels may be generated. A FIFO or other memory unit may be used to linearly order the plurality of textured pixel addresses. Two consecutive textured pixel addresses out of the plurality of textured pixel addresses may be examined if they map to a common set of texels in texture space. The two consecutive textured pixel addresses may be merged together and propagated down the pipeline if they map to the common set of texels. However, only a first of the two consecutive textured pixel addresses may be propagated down the pipeline if the two consecutive textured pixel addresses do not map to a common set of texels. Texel data may be generated in response to receiving either the combined texel structure or the first of the two textured pixel addresses. The texel data may be filtered using one or more texture filters in order to generate texture values. The next two textured pixel addresses that may be examined by the merge unit include the subsequent two consecutive textured pixel addresses, or a second of the two consecutive textured pixel addresses and a subsequent consecutive textured pixel address.

5. 发明授权

US07023444B2 Multi-texturing by walking an appropriately-sized supertile over a primitive 有权
标题翻译：通过在原始图像上行走适当尺寸的超重物进行多纹理化
公开(公告)号：US07023444B2
公开(公告)日：2006-04-04
申请号：US10393528
申请日：2003-03-20
申请人： Brian D. Emberling , Michael G. Lavelle , Assana M. Fard , Nandini Ramani , David C. Kehlet , Michael A. Wasserman , Ewa M. Kubalska , Mark E Pascual
发明人： Brian D. Emberling , Michael G. Lavelle , Assana M. Fard , Nandini Ramani , David C. Kehlet , Michael A. Wasserman , Ewa M. Kubalska , Mark E Pascual
IPC分类号： G06T11/40
CPC分类号： G06T15/04
摘要： A rendering unit positions a supertile so that it intersects a primitive. The rendering unit repeatedly walks over bins of the supertile, applying a layer of texture to the bins of the supertile in each iteration of said repeated walking. The rendering unit advances to the next texture layer after having applied the current texture layer to each candidate bin of the supertile. The results of each texture layer application to the bins may be stored in a texture accumulation buffer. The size of the supertile corresponds to the size of the texture accumulation buffer. After applying a last layer of texture to the bins of the supertile, the supertile may be advanced to a new position. The rendering unit traverses the primitive with the supertile so that the union of areas visited by the supertile covers the primitive.
摘要翻译：渲染单元定位一个supertile，以便它与一个原语相交。渲染单元重复地移动超重物料箱，在所述重复步行的每次迭代中将一层纹理施加到上层的仓上。渲染单元在将当前纹理层应用于上层的每个候选块之后前进到下一个纹理层。每个纹理层应用于存储区的结果可以存储在纹理累积缓冲器中。 supertile的大小对应于纹理累积缓冲区的大小。将最后一层纹理应用于上层的仓后，超级可以提前到一个新的位置。渲染单元用优先级遍历原始图像，使得由supertile访问的区域的联合覆盖原始图像。

6. 发明授权

US06963342B2 Arbitration scheme for efficient parallel processing 有权
标题翻译：有效的并行处理仲裁方案
公开(公告)号：US06963342B2
公开(公告)日：2005-11-08
申请号：US10085432
申请日：2002-02-28
申请人： Mark E. Pascual , Michael G. Lavelle , Nandini Ramani , Patrick Shehane
发明人： Mark E. Pascual , Michael G. Lavelle , Nandini Ramani , Patrick Shehane
IPC分类号： G06F9/38 , G06F15/78 , G06T1/20
CPC分类号： G06F15/8053 , G06F9/3836 , G06F9/3885 , G06T1/20
摘要： A system and method for assigning operations to multiple pipelines in a graphics system is disclosed. The graphics system may include an arbitration unit coupled to a plurality of calculation pipelines. The arbitration unit is operable to provide graphics operations to selected ones of the calculation pipelines. Each of the calculation pipelines is operable to perform a graphics operation. Each of the calculation pipelines may include digital logic and/or a processing element for performing the graphics operations. An operation may be assigned to a pipeline if the pipeline is performing a low latency operation. A low latency operation may comprise an operation that is performed by one of the calculation pipelines in less time than a pre-determined number of clock cycles.
摘要翻译：公开了一种用于向图形系统中的多个管道分配操作的系统和方法。图形系统可以包括耦合到多个计算管线的仲裁单元。仲裁单元可操作以向所选择的计算流水线提供图形操作。每个计算流水线都可操作以执行图形操作。每个计算流水线可以包括用于执行图形操作的数字逻辑和/或处理元件。如果管道正在执行低延迟操作，则可以将操作分配给流水线。低延迟操作可以包括在比预定数量的时钟周期更短的时间内由计算流水线之一执行的操作。

7. 发明授权

US06943791B2 Z-slope test to optimize sample throughput 有权
标题翻译： Z斜率测试以优化样品通量
公开(公告)号：US06943791B2
公开(公告)日：2005-09-13
申请号：US10094947
申请日：2002-03-11
申请人： Mark E. Pascual , Michael G. Lavelle , Michael F. Deering , Nandini Ramani
发明人： Mark E. Pascual , Michael G. Lavelle , Michael F. Deering , Nandini Ramani
IPC分类号： G06T15/00 , G06T15/40
CPC分类号： G06T15/005 , G06T2200/28
摘要： A system and method are disclosed for utilizing a Z slope test to select polygons that may be candidates for multiple storage methods. The method may calculate the absolute Z slope from vertex data and compare the calculated value with a specified threshold value. In some embodiments, for polygons that have an absolute Z slope less than the threshold value, parameter values may be rendered for only one sample position of multiple neighboring sample positions. The parameter values rendered for the one sample position may then be stored in multiple memory locations that correspond to the multiple neighboring sample positions. In some embodiments, storing parameter values in multiple memory locations may be achieved in a single write transaction. In some embodiments, utilization of the Z slope test method may be subject to user input and in other embodiments may be a dynamic decision controlled by the graphics system.
摘要翻译：公开了一种利用Z斜率测试来选择可能是多种存储方法候选的多边形的系统和方法。该方法可以从顶点数据计算绝对Z斜率，并将计算值与指定的阈值进行比较。在一些实施例中，对于具有小于阈值的绝对Z斜率的多边形，可以仅为多个相邻采样位置的一个采样位置呈现参数值。然后可以将针对一个采样位置渲染的参数值存储在对应于多个相邻采样位置的多个存储器位置中。在一些实施例中，在多个存储器位置中存储参数值可以在单个写入事务中实现。在一些实施例中，Z斜率测试方法的利用可能受用户输入的限制，在其他实施例中可以是由图形系统控制的动态决策。

8. 发明授权

US06906720B2 Multipurpose memory system for use in a graphics system 有权
标题翻译：用于图形系统的多功能内存系统
公开(公告)号：US06906720B2
公开(公告)日：2005-06-14
申请号：US10096065
申请日：2002-03-12
申请人： Brian D. Emberling , Michael G. Lavelle
发明人： Brian D. Emberling , Michael G. Lavelle
IPC分类号： G06T1/60 , G09G5/36 , G09G5/39 , G06F12/02
CPC分类号： G06T1/60 , G06T11/40 , G09G5/363 , G09G5/39 , G09G2360/12
摘要： A graphics system may include a frame buffer, a processing device coupled to output data, a multipurpose memory device that includes a plurality of storage locations and is coupled to store data output from the processing device, and a multipurpose memory controller coupled to the multipurpose memory device. The multipurpose memory controller may be configured to allocate a first plurality of the storage locations to a first image buffer configured to store image data, a second plurality of the storage locations to a first texture buffer configured to store texture data, and a third plurality of the storage locations to a first accumulation buffer configured to store accumulation buffer data. The multipurpose memory device may be configured to include a first image buffer, a first texture buffer, and a first accumulation buffer at the same time.
摘要翻译：图形系统可以包括帧缓冲器，耦合到输出数据的处理设备，包括多个存储位置并被耦合以存储从处理设备输出的数据的多用途存储器设备，以及耦合到多用途存储器的多用途存储器控制器设备。多用途存储器控制器可以被配置为将第一多个存储位置分配给被配置为存储图像数据的第一图像缓冲器，第二多个存储位置分配给被配置为存储纹理数据的第一纹理缓冲器，以及第三多个存储位置到被配置为存储累积缓冲器数据的第一累积缓冲器。多用途存储器装置可以被配置为同时包括第一图像缓冲器，第一纹理缓冲器和第一累积缓冲器。

9. 发明授权

US06819320B2 Reading or writing a non-super sampled image into a super sampled buffer 有权
标题翻译：将非超级采样图像读入或写入超采样缓冲器
公开(公告)号：US06819320B2
公开(公告)日：2004-11-16
申请号：US10090479
申请日：2002-03-04
申请人： Michael G. Lavelle , Elena M. Ing
发明人： Michael G. Lavelle , Elena M. Ing
IPC分类号： G06F1500
CPC分类号： G06T5/002 , G06T5/20 , G06T2200/12 , G06T2207/10016
摘要： A graphics system and method for storing pixel values into or reading pixel values from a sample buffer, wherein the sample buffer is configured to store a plurality of samples for each of a plurality of pixels. The graphics system comprises a sample buffer, a programmable register, and a graphics processor. The programmable register stores a value indicating a method for pixel to sample conversion, and is preferably software programmable (e.g., user programmable). The graphics processor accesses the memory to determine a method for pixel to sample conversion and stores the pixel values in the sample buffer according to the determined method. A first method for pixel to sample conversion may specify a pixel write to all of the pixel's supporting samples. A second method for pixel to sample conversion may specify a pixel write to a selected one of the pixel's supporting samples.
摘要翻译：一种用于将像素值存储到样本缓冲器中或从其中读取像素值的图形系统和方法，其中所述采样缓冲器被配置为存储多个像素中的每一个的多个采样。图形系统包括采样缓冲器，可编程寄存器和图形处理器。可编程寄存器存储指示用于像素到样本转换的方法的值，并且优选地是软件可编程的（例如，用户可编程的）。图形处理器访问存储器以确定用于像素进行采样转换的方法，并根据确定的方法将像素值存储在采样缓冲器中。用于像素进行采样转换的第一种方法可以指定对所有像素的支持样本的像素写入。用于像素到采样转换的第二种方法可以指定对所选像素的支持样本中的所选择的像素的像素写入。

10. 发明授权

US06795081B2 Sample cache for supersample filtering 有权
标题翻译：超示例过滤示例缓存
公开(公告)号：US06795081B2
公开(公告)日：2004-09-21
申请号：US09861479
申请日：2001-05-18
申请人： Michael G. Lavelle , Philip C. Leung , Yan Y. Tang
发明人： Michael G. Lavelle , Philip C. Leung , Yan Y. Tang
IPC分类号： G09G536
CPC分类号： G06T1/60
摘要： A system and method capable of super-sampling and performing super-sample convolution are disclosed. In one embodiment, the system may comprise a graphics processor, a frame buffer, a sample cache, and a sample-to-pixel calculation unit. The graphics processor may be configured to generate a plurality of samples. The frame buffer, which is coupled to the graphics processor, may be configured to store the samples in a sample buffer. The samples may be positioned according to a regular grid, a perturbed regular grid, or a stochastic grid. The sample-to-pixel calculation unit is programmable to select a variable number of stored samples from the frame buffer, copy the selected samples to a sample cache, and filter a set of the selected samples into an output pixel. The sample-to-pixel calculation unit retains those samples in the sample cache that will be reused in a subsequent pixel calculation and replaces those samples no longer required with new samples for another filter calculation.
摘要翻译：公开了能够超采样和执行超采样卷积的系统和方法。在一个实施例中，系统可以包括图形处理器，帧缓冲器，采样高速缓存和采样到像素计算单元。图形处理器可以被配置为生成多个采样。耦合到图形处理器的帧缓冲器可以被配置为将样本存储在采样缓冲器中。样本可以根据规则网格，扰动的规则网格或随机网格来定位。样本到像素计算单元是可编程的，以从帧缓冲器中选择可变数量的存储样本，将所选样本复制到样本高速缓存，并将所选择的样本集合过滤到输出像素中。样本到像素计算单元将样本缓存中保留的样本保留在随后的像素计算中重新使用，并将不再需要的样本替换为另一个滤波器计算的新采样。

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