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1. 发明授权

US07018933B2 Method of forming a metal-insulator-metal capacitor 有权
公开(公告)号：US07018933B2
公开(公告)日：2006-03-28
申请号：US10426743
申请日：2003-04-30
申请人： Wan-don Kim , Jin-won Kim , Seok-jun Won , Cha-young Yoo
发明人： Wan-don Kim , Jin-won Kim , Seok-jun Won , Cha-young Yoo
IPC分类号： H01L21/302 , H01L21/8242
CPC分类号： H01L21/02183 , H01L21/0228 , H01L21/02337 , H01L21/02348 , H01L21/31604 , H01L28/91
摘要： A metal-insulator-metal (MIM) capacitor of a semiconductor device, and a manufacturing method thereof, includes a lower electrode formed of a refractory metal or a conductive compound including the refractory metal, a dielectric film formed of a high dielectric material, and an upper electrode formed of a platinum-family metal or a platinum-family metal oxide. Accordingly, the MIM capacitor satisfies the criteria of step coverage, electrical characteristics and manufacturing costs, as compared to a conventional MIM capacitor in which the upper and lower electrodes are formed of the same material such as a platinum-family metal, a refractory metal or a conductive compound including the refractory metal. The capacitor is especially suitable for mass production in semiconductor fabrication processes.

2. 发明授权

US06580111B2 Metal-insulator-metal capacitor 有权
标题翻译：金属绝缘体金属电容器
公开(公告)号：US06580111B2
公开(公告)日：2003-06-17
申请号：US09863679
申请日：2001-05-23
申请人： Wan-don Kim , Jin-won Kim , Seok-jun Won , Cha-young Yoo
发明人： Wan-don Kim , Jin-won Kim , Seok-jun Won , Cha-young Yoo
IPC分类号： H01L27108
CPC分类号： H01L21/02183 , H01L21/0228 , H01L21/02337 , H01L21/02348 , H01L21/31604 , H01L28/91
摘要： A metal-insulator-metal (MIM) capacitor of a semiconductor device, and a manufacturing method thereof, includes a lower electrode formed of a refractory metal or a conductive compound including the refractory metal, a dielectric film formed of a high dielectric material, and an upper electrode formed of a platinum-family metal or a platinum-family metal oxide. Accordingly, the MIM capacitor satisfies the criteria of step coverage, electrical characteristics and manufacturing costs, as compared to a conventional MIM capacitor in which the upper and lower electrodes are formed of the same material such as a platinum-family metal, a refractory metal or a conductive compound including the refractory metal. The capacitor is especially suitable for mass production in semiconductor fabrication processes.
摘要翻译：半导体器件的金属 - 绝缘体 - 金属（MIM）电容器及其制造方法包括由难熔金属形成的下电极或包含难熔金属的导电化合物，由高电介质材料形成的电介质膜，以及由铂族金属或铂族金属氧化物形成的上电极。因此，与常规的MIM电容器相比，MIM电容器满足阶梯覆盖，电特性和制造成本的标准，其中上电极和下电极由相同的材料形成，例如铂族金属，难熔金属或包括难熔金属的导电化合物。电容器特别适用于半导体制造工艺中的批量生产。

3. 发明授权

US06472319B2 Method for manufacturing capacitor of semiconductor memory device by two-step thermal treatment 失效
标题翻译：通过两步热处理制造半导体存储器件电容器的方法
公开(公告)号：US06472319B2
公开(公告)日：2002-10-29
申请号：US09851910
申请日：2001-05-09
申请人： Seok-jun Won , Yun-jung Lee , Soon-yeon Park , Cha-young Yoo , Doo-sup Hwang , Eun-ae Chung , Wan-don Kim
发明人： Seok-jun Won , Yun-jung Lee , Soon-yeon Park , Cha-young Yoo , Doo-sup Hwang , Eun-ae Chung , Wan-don Kim
IPC分类号： H01L2144
CPC分类号： H01L28/55 , H01L28/65
摘要： A method for manufacturing a capacitor of a semiconductor memory device by a two-step thermal treatment is provided. A lower electrode is formed on a semiconductor substrate. A dielectric layer is formed over the lower electrode. An upper electrode formed of a noble metal is formed over the dielectric layer. The resultant having the upper electrode undergoes a first thermal treatment under a first atmosphere including oxygen at a first temperature which is selected to be within a range of 200-600° C., which is lower than the oxidation temperature of the upper electrode. The first thermally treated resultant undergoes a second thermal treatment under a second atmosphere without oxygen at a second temperature which is selected to be within a range of 300-900° C., which is higher than the first temperature.
摘要翻译：提供了通过两步热处理制造半导体存储器件的电容器的方法。在半导体衬底上形成下电极。在下电极上形成电介质层。在电介质层上形成由贵金属形成的上电极。具有上电极的所得物在包含氧的第一气氛下进行第一热处理，所述第一气氛在第一温度下被选择在低于上电极的氧化温度的200-600℃的范围内。第一热处理产物在第二温度下在没有氧的第二气氛下进行第二热处理，第二温度选择在比第一温度高的300-900℃的范围内。

4. 发明授权

US06613629B2 Methods for manufacturing storage nodes of stacked capacitors 有权
公开(公告)号：US06613629B2
公开(公告)日：2003-09-02
申请号：US10213856
申请日：2002-08-07
申请人： Wan-don Kim , Cha-young Yoo , Jae-hyun Joo , Seok-jun Won
发明人： Wan-don Kim , Cha-young Yoo , Jae-hyun Joo , Seok-jun Won
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L27/10852 , H01L28/55
摘要： Methods for manufacturing a node of a stacked capacitor are provided. A first dielectric layer having a contact plug therein is formed on an integrated circuit substrate. A second dielectric layer including a storage node hole adjacent the contact plug is formed on the first dielectric layer. A conductive layer is deposited into the storage node hole and on the second dielectric layer. The conductive layer on the second dielectric layer is removed to provide a conductive storage node in the storage node hole. After the conductive layer on the second dielectric layer is removed, the conductive storage node is heat treated to reflow the conductive storage node before additional layers are formed on the conductive storage node.

5. 发明授权

US06649502B2 Methods of forming multilayer dielectric regions using varied deposition parameters 失效
公开(公告)号：US06649502B2
公开(公告)日：2003-11-18
申请号：US09859168
申请日：2001-05-16
申请人： Cha-young Yoo , Han-jin Lim , Wan-don Kim , Se-jin Lee , Soon-yeon Park , Yong-kuk Jeong , Han-mei Choi , Gyung-hoon Hong , Seok-jun Won
发明人： Cha-young Yoo , Han-jin Lim , Wan-don Kim , Se-jin Lee , Soon-yeon Park , Yong-kuk Jeong , Han-mei Choi , Gyung-hoon Hong , Seok-jun Won
IPC分类号： H01L213205
CPC分类号： H01L21/02183 , C23C16/405 , C23C16/45557 , H01L21/02337 , H01L21/02348 , H01L21/31604 , H01L28/40 , H01L28/56
摘要： A dielectric region for a device such as a memory cell capacitor is formed by depositing a metal oxide, such as tantalum oxide, on a substrate at a first deposition rate in a first atmosphere maintained within a first temperature range and a first pressure range that produce a first tantalum oxide layer with a desirable step coverage. Metal oxide is subsequently deposited on the first metal oxide layer in a second atmosphere maintained within a second temperature range and a second pressure range that produce a second deposition rate greater than the first deposition rate to form a second tantalum oxide layer on the first tantalum oxide layer. For example, the first atmosphere may be maintained at a temperature in a range from about 350° C. to about 460° C. and a pressure in a range from about 0.01 Torr to about 2.0 Torr during formation of a first tantalum oxide layer, and the second atmosphere may be maintained at a temperature in a range from about 400° C. to about 500° C. and a pressure in a range from about 0.1 Torr to about 10.0 Torr during formation of a second tantalum oxide layer.

6. 发明授权

US07034350B2 Capacitors including a cavity containing a buried layer 有权
标题翻译：电容器包括一个包含掩埋层的空腔
公开(公告)号：US07034350B2
公开(公告)日：2006-04-25
申请号：US10795020
申请日：2004-03-05
申请人： Suk-jin Chung , Wan-don Kim , Cha-young Yoo , Kwang-hee Lee , Han-jin Lim , Jin-il Lee
发明人： Suk-jin Chung , Wan-don Kim , Cha-young Yoo , Kwang-hee Lee , Han-jin Lim , Jin-il Lee
IPC分类号： H01L27/108
CPC分类号： H01L28/65 , H01L27/10852 , H01L28/91
摘要： Capacitors include an integrated circuit (semiconductor) substrate and an interlayer dielectric disposed on the integrated circuit substrate and including a metal plug therein. A lower electrode is disposed on the interlayer dielectric and contacting the metal plug. The lower electrode includes a cavity therein and a buried layer in the cavity. The buried layer is an oxygen absorbing material. A dielectric layer disposed on the lower electrode and an upper electrode is disposed on the dielectric layer. The lower electrode may be a noble metal layer. The buried layer may fill in the cavity and may not contain oxygen (O2) when initially formed.
摘要翻译：电容器包括集成电路（半导体）基板和布置在集成电路基板上并且在其中包括金属插塞的层间电介质。下部电极设置在层间电介质上并接触金属插塞。下电极在其中包括空腔，并且在腔中包括掩埋层。掩埋层是吸氧材料。设置在下电极上的电介质层和上电极设置在电介质层上。下电极可以是贵金属层。当初始形成时，掩埋层可以填充空腔并且可以不含有氧（O 2 2 N）。

7. 发明申请

US20060148193A1 Methods for forming ruthenium films with beta-diketone containing ruthenium complexes and method for manufacturing metal-insulator-metal capacitor using the same 审中-公开
标题翻译：用含有钌络合物的β-二酮形成钌膜的方法及使用其制造金属 - 绝缘体 - 金属电容器的方法
公开(公告)号：US20060148193A1
公开(公告)日：2006-07-06
申请号：US11374349
申请日：2006-03-13
申请人： Kwang-hee Lee , Cha-young Yoo , Han-Jin Lim , Sung-tae Kim , Suk-jin Chung , Wan-don Kim , Jung-hee Chung , Jin-il Lee
发明人： Kwang-hee Lee , Cha-young Yoo , Han-Jin Lim , Sung-tae Kim , Suk-jin Chung , Wan-don Kim , Jung-hee Chung , Jin-il Lee
IPC分类号： H01L21/44
CPC分类号： C23C16/18 , H01L21/28556 , H01L27/10852 , H01L27/11502 , H01L27/11507 , H01L28/65
摘要： Provided are 1) a method for forming a ruthenium film under a single process condition, whereby high adhesion of the ruthenium film to a lower layer is maintained, and 2) a method for manufacturing an metal-insulator-metal (MIM) capacitor using the ruthenium film forming method. The method for forming a ruthenium film includes supplying bis(isoheptane-2,4-dionato)norbornadiene ruthenium at a flow rate of 0.2-1 ccm and oxygen at a flow rate of 20-60 sccm, and depositing the ruthenium film at a temperature of 330-430° C. under a pressure of 0.5-5 Torr using chemical vapor deposition (CVD).
摘要翻译：提供1）一种在单一工艺条件下形成钌膜的方法，由此保持钌膜对下层的高附着性，以及2）使用这种方法制造金属 - 绝缘体 - 金属（MIM）电容器的方法钌膜成型方法。形成钌膜的方法包括以0.2-1ccm的流速和20-60sccm的流量的氧供给双（异庚烷-2,4-二酮）降冰片二烯钌，并将钌膜以在0.5-5乇的压力下使用化学气相沉积（CVD）来制备330-430℃。

8. 发明申请

US20050161727A1 Integrated circuit devices having a metal-insulator-metal (MIM) capacitor 审中-公开
标题翻译：具有金属 - 绝缘体 - 金属（MIM）电容器的集成电路器件
公开(公告)号：US20050161727A1
公开(公告)日：2005-07-28
申请号：US11083874
申请日：2005-03-18
申请人： Jae-hyun Joo , Cha-young Yoo , Wan-don Kim , Yong-kuk Jeong
发明人： Jae-hyun Joo , Cha-young Yoo , Wan-don Kim , Yong-kuk Jeong
IPC分类号： H01L27/108 , H01L21/02 , H01L21/8242 , H01L29/76 , H01L21/20
CPC分类号： H01L28/60 , H01L27/10855 , H01L28/91
摘要： In some embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A unitary lower electrode of a capacitor is disposed on the substrate and has a contact plug portion thereof that is disposed in the hole. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer. In other embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A barrier layer is disposed on the exposed portion of the substrate and on sidewalls of the interlevel-insulating layer. A contact plug is disposed in the hole on the barrier layer. A lower electrode of a capacitor is disposed on the contact plug and engages the contact plug at a boundary therebetween. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer.
摘要翻译：在一些实施例中，集成电路器件包括衬底和衬底上的层间绝缘层，其中具有暴露衬底的孔。电容器的整体下电极设置在基板上，并且具有设置在孔中的接触插塞部分。电介质层位于下电极上，电容器的上电极位于电介质层上。在其他实施例中，集成电路器件包括衬底和衬底上的层间绝缘层，其中具有暴露衬底的孔。阻挡层设置在衬底的暴露部分和层间绝缘层的侧壁上。接触塞设置在阻挡层上的孔中。电容器的下电极设置在接触插头上，并在接触插塞之间的边界处接合。电介质层位于下电极上，电容器的上电极位于电介质层上。

9. 发明授权

US06884673B2 Methods of forming integrated circuit devices having metal-insulator-metal (MIM) capacitor 有权
标题翻译：形成具有金属 - 绝缘体 - 金属（MIM）电容器的集成电路器件的方法
公开(公告)号：US06884673B2
公开(公告)日：2005-04-26
申请号：US10160646
申请日：2002-05-31
申请人： Jae-hyun Joo , Cha-young Yoo , Wan-don Kim , Yong-kuk Jeong
发明人： Jae-hyun Joo , Cha-young Yoo , Wan-don Kim , Yong-kuk Jeong
IPC分类号： H01L27/108 , H01L21/02 , H01L21/8242
CPC分类号： H01L28/60 , H01L27/10855 , H01L28/91
摘要： In some embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A unitary lower electrode of a capacitor is disposed on the substrate and has a contact plug portion thereof that is disposed in the hole. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer. In other embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A barrier layer is disposed on the exposed portion of the substrate and on sidewalls of the interlevel-insulating layer. A contact plug is disposed in the hole on the barrier layer. A lower electrode of a capacitor is disposed on the contact plug and engages the contact plug at a boundary therebetween. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer.
摘要翻译：在一些实施例中，集成电路器件包括衬底和衬底上的层间绝缘层，其中具有暴露衬底的孔。电容器的整体下电极设置在基板上，并且具有设置在孔中的接触插塞部分。电介质层位于下电极上，电容器的上电极位于电介质层上。在其他实施例中，集成电路器件包括衬底和衬底上的层间绝缘层，其中具有暴露衬底的孔。阻挡层设置在衬底的暴露部分和层间绝缘层的侧壁上。接触塞设置在阻挡层上的孔中。电容器的下电极设置在接触插头上，并在接触插塞之间的边界处接合。电介质层位于下电极上，电容器的上电极位于电介质层上。

10. 发明申请

US20070099419A1 Methods for forming semiconductor devices including thermal processing 有权
公开(公告)号：US20070099419A1
公开(公告)日：2007-05-03
申请号：US11641138
申请日：2006-12-19
申请人： Jae-hyoung Choi , Wan-don Kim , Cha-young Yoo , Suk-jin Chung
发明人： Jae-hyoung Choi , Wan-don Kim , Cha-young Yoo , Suk-jin Chung
IPC分类号： H01L21/44
CPC分类号： H01L28/65 , H01L28/40
摘要： Methods for fabricating semiconductor memory devices may include forming a first conductive layer for a first electrode on a semiconductor substrate, forming a dielectric layer on the first conductive layer, and forming a second conductive layer for a second electrode on the dielectric layer. Portions of the second conductive layer and the dielectric layer can be removed, and a thermal process can be performed on the second conductive layer and the dielectric layer. The thermal process can reduce interface stress between the second conductive layer and the dielectric layer and/or cure the dielectric layer. In addition, the dielectric layer may be maintained in an amorphous state during and after the thermal process.

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