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1. 发明授权

US06472319B2 Method for manufacturing capacitor of semiconductor memory device by two-step thermal treatment 失效
标题翻译：通过两步热处理制造半导体存储器件电容器的方法
公开(公告)号：US06472319B2
公开(公告)日：2002-10-29
申请号：US09851910
申请日：2001-05-09
申请人： Seok-jun Won , Yun-jung Lee , Soon-yeon Park , Cha-young Yoo , Doo-sup Hwang , Eun-ae Chung , Wan-don Kim
发明人： Seok-jun Won , Yun-jung Lee , Soon-yeon Park , Cha-young Yoo , Doo-sup Hwang , Eun-ae Chung , Wan-don Kim
IPC分类号： H01L2144
CPC分类号： H01L28/55 , H01L28/65
摘要： A method for manufacturing a capacitor of a semiconductor memory device by a two-step thermal treatment is provided. A lower electrode is formed on a semiconductor substrate. A dielectric layer is formed over the lower electrode. An upper electrode formed of a noble metal is formed over the dielectric layer. The resultant having the upper electrode undergoes a first thermal treatment under a first atmosphere including oxygen at a first temperature which is selected to be within a range of 200-600° C., which is lower than the oxidation temperature of the upper electrode. The first thermally treated resultant undergoes a second thermal treatment under a second atmosphere without oxygen at a second temperature which is selected to be within a range of 300-900° C., which is higher than the first temperature.
摘要翻译：提供了通过两步热处理制造半导体存储器件的电容器的方法。在半导体衬底上形成下电极。在下电极上形成电介质层。在电介质层上形成由贵金属形成的上电极。具有上电极的所得物在包含氧的第一气氛下进行第一热处理，所述第一气氛在第一温度下被选择在低于上电极的氧化温度的200-600℃的范围内。第一热处理产物在第二温度下在没有氧的第二气氛下进行第二热处理，第二温度选择在比第一温度高的300-900℃的范围内。

2. 发明授权

US06815221B2 Method for manufacturing capacitor of semiconductor memory device controlling thermal budget 有权
标题翻译：制造控制热预算的半导体存储器件电容器的方法
公开(公告)号：US06815221B2
公开(公告)日：2004-11-09
申请号：US10105181
申请日：2002-03-25
申请人： Wan-don Kim , Cha-young Yoo , Doo-sup Hwang , Jae-hyun Joo , Eun-ae Chung , Yong-kuk Jeong
发明人： Wan-don Kim , Cha-young Yoo , Doo-sup Hwang , Jae-hyun Joo , Eun-ae Chung , Yong-kuk Jeong
IPC分类号： H01G706
CPC分类号： H01L28/55 , H01L28/60 , H01L28/91
摘要： A method for manufacturing a capacitor of a semiconductor memory device by controlling thermal budgets is provided. In the method for manufacturing a capacitor of a semiconductor memory device, a lower electrode is formed on a semiconductor substrate. The lower electrode is heat-treated with a first thermal budget. A dielectric layer is formed on the heat-treated lower electrode. The dielectric layer is crystallized by heat-treating the dielectric layer with a second thermal budget which is smaller than the first thermal budget.
摘要翻译：提供了一种通过控制热预算来制造半导体存储器件的电容器的方法。在制造半导体存储器件的电容器的方法中，在半导体衬底上形成下电极。下电极用第一热预算进行热处理。在热处理的下电极上形成电介质层。通过用小于第一热预算的第二热预算对介电层进行热处理来使介质层结晶。

3. 发明授权

US06683001B2 Method for manufacturing a semiconductor device whereby degradation of surface morphology of a metal layer from thermal oxidation is suppressed 有权
标题翻译：制造半导体器件的方法，其中抑制了金属层从热氧化的表面形态的退化
公开(公告)号：US06683001B2
公开(公告)日：2004-01-27
申请号：US10101353
申请日：2002-03-19
申请人： Eun-ae Chung , Doo-sup Hwang , Cha-young Yoo
发明人： Eun-ae Chung , Doo-sup Hwang , Cha-young Yoo
IPC分类号： H01L2100
CPC分类号： H01L21/02315 , H01L21/02183 , H01L21/02197 , H01L21/31683 , H01L28/55 , H01L28/60 , H01L28/75
摘要： A method of manufacturing a semiconductor device having a metal layer is provided in which variation of surface morphology resulting from thermal oxidation is suppressed. The metal layer is pretreated at a first temperature so that an upper surface of the metal layer is changed into a mixed phase of metal and oxygen and becomes substantially resistant to further oxidation during a subsequent heating at a higher temperature in an oxygen atmosphere.
摘要翻译：提供一种制造具有金属层的半导体器件的方法，其中抑制了由热氧化引起的表面形态的变化。金属层在第一温度下预处理，使得金属层的上表面变为金属和氧的混合相，并且在氧气氛中在较高温度下的后续加热中变得显着抵抗进一步氧化。

4. 发明授权

US06927166B2 Method for manufacturing semiconductor devices and integrated circuit capacitors whereby degradation of surface morphology of a metal layer from thermal oxidation is suppressed 有权
标题翻译：制造半导体器件和集成电路电容器的方法，由此抑制金属层的热氧化的表面形态的退化
公开(公告)号：US06927166B2
公开(公告)日：2005-08-09
申请号：US10690763
申请日：2003-10-22
申请人： Eun-ae Chung , Doo-sup Hwang , Cha-young Yoo
发明人： Eun-ae Chung , Doo-sup Hwang , Cha-young Yoo
IPC分类号： H01L21/30 , H01L21/02 , H01L21/316 , H01L21/00 , H01L21/44
CPC分类号： H01L21/02315 , H01L21/02183 , H01L21/02197 , H01L21/31683 , H01L28/55 , H01L28/60 , H01L28/75
摘要： A method of manufacturing a semiconductor device having a metal layer is provided in which variation of surface morphology resulting from thermal oxidation is suppressed. The metal layer is pretreated at a first temperature so that an upper surface of the metal layer is changed into a mixed phase of metal and oxygen and becomes substantially resistant to further oxidation during a subsequent heating at a higher temperature in an oxygen atmosphere.
摘要翻译：提供一种制造具有金属层的半导体器件的方法，其中抑制了由热氧化引起的表面形态的变化。金属层在第一温度下预处理，使得金属层的上表面变为金属和氧的混合相，并且在氧气氛中在较高温度下的后续加热中变得显着抵抗进一步氧化。

5. 发明授权

US06806183B2 Methods for forming capacitors on semiconductor substrates 有权
标题翻译：在半导体衬底上形成电容器的方法
公开(公告)号：US06806183B2
公开(公告)日：2004-10-19
申请号：US10295348
申请日：2002-11-15
申请人： Chang-seok Kang , Doo-sup Hwang , Cha-young Yoo , Young-wook Park , Hong-bae Park
发明人： Chang-seok Kang , Doo-sup Hwang , Cha-young Yoo , Young-wook Park , Hong-bae Park
IPC分类号： H01L214763
CPC分类号： H01L28/60 , H01L21/321 , H01L28/55
摘要： Methods and apparatus for plasma annealing layers of a microelectronic capacitor on a substrate are provided to improve the leakage current characteristics of a capacitor and/or to reduce the number of impurities in an electrode.
摘要翻译：提供了用于提高电容器的漏电流特性和/或减少电极中杂质数量的基板上的微电子电容器等离子体退火层的方法和装置。

6. 发明授权

US06596186B2 Mask for the selective growth of a solid, a manufacturing method for the mask, and a method for selectively growing a solid using the mask 有权
公开(公告)号：US06596186B2
公开(公告)日：2003-07-22
申请号：US09917711
申请日：2001-07-31
申请人： Tetsuji Yasuda , Kazuyuki Ikuta , Satoshi Yamasaki , Kazunobu Tanaka , Doo-sup Hwang
发明人： Tetsuji Yasuda , Kazuyuki Ikuta , Satoshi Yamasaki , Kazunobu Tanaka , Doo-sup Hwang
IPC分类号： B44C122
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L31/18 , Y10T428/24926
摘要： A mask for a selective growth of a solid, is provided in which the solid is selectively grown in a predetermined region of a substrate and growth on other regions is suppressed. A method is also provided for selectively growing a solid on only the predetermined region of a substrate using the mask. In the mask, a surface layer and an underlayer are provided, each having different chemical compositions. Thus, even if the mask is formed on a substrate in an ultra thin film, the generation of mask defects can be suppressed and stability provided to heat and electron beams.

7. 发明授权

US06287699B1 Mask for the selective growth of a solid 有权
标题翻译：用于固体选择性生长的面膜
公开(公告)号：US06287699B1
公开(公告)日：2001-09-11
申请号：US09263223
申请日：1999-03-05
申请人： Tetsuji Yasuda , Kazuyuki Ikuta , Satoshi Yamasaki , Kazunobu Tanaka , Doo-sup Hwang
发明人： Tetsuji Yasuda , Kazuyuki Ikuta , Satoshi Yamasaki , Kazunobu Tanaka , Doo-sup Hwang
IPC分类号： H01L2132
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L31/18 , Y10T428/24926
摘要： A mask for a selective growth of a solid, is provided in which the solid is selectively grown in a predetermined region of a substrate and growth on other regions is suppressed. A method is also provided for selectively growing a solid on only the predetermined region of a substrate using the mask. In the mask, a surface layer and an underlayer are provided, each having different chemical compositions. Thus, even if the mask is formed on a substrate in an ultra thin film, the generation of mask defects can be suppressed and stability provided to heat and electron beams.
摘要翻译：提供了用于选择性生长固体的掩模，其中固体选择性地生长在基板的预定区域中，并抑制其它区域上的生长。还提供了一种方法，用于使用掩模仅在基板的预定区域上选择性地生长固体。在掩模中，提供表面层和底层，每层具有不同的化学组成。因此，即使在超薄膜中的基板上形成掩模，也可以抑制掩模缺陷的产生，并且对热和电子束提供稳定性。

8. 发明授权

US6001660A Methods of forming integrated circuit capacitors using metal reflow techniques 失效
标题翻译：使用金属回流技术形成集成电路电容器的方法
公开(公告)号：US6001660A
公开(公告)日：1999-12-14
申请号：US969672
申请日：1997-11-13
申请人： Young-soh Park , Sang-in Lee , Cheol-seong Hwang , Doo-sup Hwang , Hag-Ju Cho
发明人： Young-soh Park , Sang-in Lee , Cheol-seong Hwang , Doo-sup Hwang , Hag-Ju Cho
IPC分类号： C23C14/14 , C23C14/58 , H01L21/02 , H01L21/28 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108 , H01G7/06
CPC分类号： H01L28/60 , H01L21/76882
摘要： Methods of forming integrated circuit capacitors include the steps of forming an electrically insulating layer on a face of a semiconductor substrate and then patterning the electrically insulating layer to define a contact hole therein. A barrier metal layer is then formed in at least a portion of the contact hole. A lower electrode metal layer is then formed on the barrier metal layer and then planarized by reflowing the lower electrode metal layer at a temperature greater than about 650.degree. C. in a nitrogen gas ambient, to define a lower capacitor electrode. A layer of material having a high dielectric constant is then formed on the lower capacitor electrode. An upper capacitor electrode is then formed on the dielectric layer, opposite the lower capacitor electrode. The dielectric layer may comprise Ba(Sr, Ti)O.sub.3, Pb(Zr, Ti)O.sub.3, Ta.sub.2 O.sub.5, SiO.sub.2, SiN.sub.3, SrTiO.sub.3, PZT, SrBi.sub.2 Ta.sub.2 O.sub.9, (Pb, La)(Zr, Ti)O.sub.3 and Bi.sub.4 Ti.sub.3 O.sub.12. According to one embodiment of the present invention, the step of patterning the electrically insulating layer comprises patterning the electrically insulating layer to define a contact hole therein that exposes the face of the semiconductor substrate. The step of forming a barrier metal layer also preferably comprises depositing a conformal barrier metal layer on sidewalls of the contact hole and on the exposed face of the substrate. The barrier metal layer may be selected from the group consisting of TiN, CoSi, TaSiN, TiSiN, TaSi, TiSi, Ta and TaN.
摘要翻译：形成集成电路电容器的方法包括以下步骤：在半导体衬底的表面上形成电绝缘层，然后对电绝缘层进行构图以在其中限定接触孔。然后在接触孔的至少一部分中形成阻挡金属层。然后在阻挡金属层上形成下电极金属层，然后通过在氮气环境中在大于约650℃的温度下回流下电极金属层来平坦化，以限定较低的电容器电极。然后在下部电容器电极上形成具有高介电常数的材料层。然后在电介质层上形成上电容器电极，与下电容器电极相对。介电层可以包括Ba（Sr，Ti）O3，Pb（Zr，Ti）O3，Ta2O5，SiO2，SiN3，SrTiO3，PZT，SrBi2Ta2O9，（Pb，La）（Zr，Ti）O3和Bi4Ti3O12。根据本发明的一个实施例，图案化电绝缘层的步骤包括图案化电绝缘层以限定其中露出半导体衬底的表面的接触孔。形成阻挡金属层的步骤还优选包括在接触孔的侧壁上和基底的暴露面上沉积保形阻挡金属层。阻挡金属层可以选自TiN，CoSi，TaSiN，TiSiN，TaSi，TiSi，Ta和TaN。

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