专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06949459B2 Method of patterning damascene structure in integrated circuit design 失效
公开(公告)号：US06949459B2
公开(公告)日：2005-09-27
申请号：US10704022
申请日：2003-11-07
申请人： Wai-Kin Li , Chih-Chao Yang , Yi-hsiung Lin
发明人： Wai-Kin Li , Chih-Chao Yang , Yi-hsiung Lin
IPC分类号： H01L21/302 , H01L21/311 , H01L21/461 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/76808 , H01L21/31144 , H01L21/76831
摘要： Disclosed is a method that deposits an aqueous material having a pH between approximately 10 and 11 in a first opening and on an oxide hard mask, deposits an organic material on the aqueous material, and patterns a photoresist over the organic material. The invention then etches the organic material and the aqueous material through the photoresist to form a second opening above the first opening and forms a polymer along sidewalls of the second opening. The invention can then perform a wet cleaning process using an alkali solution having a pH between approximately 10 and 11 to remove the aqueous material from the first opening. By utilizing an alkali aqueous (water-based) material having a pH of approximately 10-11, the invention can use a fairly low pH wet etch (pH of approximately 10-11) to completely remove the aqueous solution from the via, thereby eliminating the conventional problem of having residual organic material left within the via.

2. 发明授权

US06750129B2 Process for forming fusible links 有权
标题翻译：形成易熔连接的工艺
公开(公告)号：US06750129B2
公开(公告)日：2004-06-15
申请号：US10292399
申请日：2002-11-12
申请人： Gwo-Shii Yang , Jen Kon Chen , Hsueh-Chung Chen , Hans-Joachim Barth , Chiung-Sheng Hsiung , Chih-Chien Liu , Tong-Yu Chen , Yi-hsiung Lin , Chih-Chao Yang
发明人： Gwo-Shii Yang , Jen Kon Chen , Hsueh-Chung Chen , Hans-Joachim Barth , Chiung-Sheng Hsiung , Chih-Chien Liu , Tong-Yu Chen , Yi-hsiung Lin , Chih-Chao Yang
IPC分类号： H01L213205
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A process for forming fusible links in an integrated circuit in which the fusible links are formed in the final metallization layer simultaneously with bonding pads. The process can be applied in the fabrication of integrated circuits that employ copper metallization and low k dielectric materials. After patterning the final metal (aluminum) layer to form the fusible links and the bonding pads, a dielectric etch stop layer is formed over the final metal layer before a passivation layer is deposited. The passivation layer is removed in areas over the fusible links and the bonding pads. The dielectric etch stop layer is removed either from above the bonding pads only, or from above both the bonding pads and the fusible links.
摘要翻译：一种用于在集成电路中形成可熔链节的方法，其中可熔链在最终金属化层中与焊盘同时形成。该方法可以应用于采用铜金属化和低k电介质材料的集成电路的制造中。在对最终的金属（铝）层进行构图以形成可熔连接件和接合焊盘之后，在沉积钝化层之前，在最终的金属层上形成介电蚀刻停止层。钝化层在可熔接头和接合焊盘上的区域中被去除。电介质蚀刻停止层仅从接合焊盘上方或者从焊盘和可熔连接部上方移除。

3. 发明授权

US07553758B2 Method of fabricating interconnections of microelectronic device using dual damascene process 有权
标题翻译：使用双镶嵌工艺制造微电子器件互连的方法
公开(公告)号：US07553758B2
公开(公告)日：2009-06-30
申请号：US11532719
申请日：2006-09-18
申请人： Wan-jae Park , Hyung-yoon Choi , Yi-hsiung Lin , Tong Qing Chen
发明人： Wan-jae Park , Hyung-yoon Choi , Yi-hsiung Lin , Tong Qing Chen
IPC分类号： H01L21/4763
CPC分类号： H01L21/3146 , H01L21/02115 , H01L21/0212 , H01L21/02167 , H01L21/02271 , H01L21/31116 , H01L21/31144 , H01L21/31155 , H01L21/76807 , H01L21/76825 , H01L21/76829 , H01L2221/1063 , Y10S438/924
摘要： Method of Fabricating Interconnections of a Microelectronic Device Using a Dual Damascene Process. A method of fabricating interconnections of a microelectronic device includes preparing a semiconductor substrate comprising a lower dielectric layer and a lower interconnection, forming an etch stopper layer and an interlayer dielectric layer on the semiconductor substrate, forming a via hole in the interlayer dielectric layer so that the etch stopper layer is exposed through the via hole, performing carbon doping on the etch stopper layer, performing trench etching to form a trench in the interlayer dielectric layer so that the trench overlaps part of the via hole, removing the carbon-doped etch stopper layer, and filling the via hole and the trench with a conductive material to form an upper interconnection.
摘要翻译：使用双镶嵌工艺制造微电子器件互连的方法。制造微电子器件的互连的方法包括制备包括下电介质层和下互连的半导体衬底，在半导体衬底上形成蚀刻停止层和层间电介质层，在层间电介质层中形成通孔，使得蚀刻阻挡层通过通孔露出，在蚀刻停止层上进行碳掺杂，进行沟槽蚀刻以在层间电介质层中形成沟槽，使得沟槽与通孔的一部分重叠，去除碳掺杂的蚀刻阻挡层层，并且用导电材料填充通孔和沟槽以形成上互连。

4. 发明申请

US20080064199A1 Methods of Forming Electrical Interconnect Structures Using Polymer Residues to Increase Etching Selectivity Through Dielectric Layers 有权
标题翻译：使用聚合物残余物形成电互连结构以通过介电层增加蚀刻选择性的方法
公开(公告)号：US20080064199A1
公开(公告)日：2008-03-13
申请号：US11530952
申请日：2006-09-12
申请人： Wan Jae Park , Jae Hak Kim , Tong Qing Chen , Yi-hsiung Lin
发明人： Wan Jae Park , Jae Hak Kim , Tong Qing Chen , Yi-hsiung Lin
IPC分类号： H01L21/44
CPC分类号： H01L21/76802 , H01L21/02063 , H01L21/31116 , H01L21/31144
摘要： Methods of forming electrical interconnect structures include forming a dielectric layer on a semiconductor substrate and forming a hard mask layer on the dielectric layer. A photoresist layer is patterned on an upper surface of the hard mask layer. This patterned photoresist layer is used as an etching mask during a step to selectively etch the hard mask layer and define an opening therein. This opening exposes the first dielectric layer. The patterned photoresist layer is then stripped from the hard mask layer using an ashing process that exposes the upper surface of the hard mask layer. Following this ashing process, a portion of the first dielectric layer extending opposite the opening is selectively etched using the hard mask layer as an etching mask. During this selective etching step, polymer residues are accumulated directly on the upper surface of the hard mask layer. These polymer residues may operate to increase a degree of selectively and inhibit recession of the hard mask layer during the step of selectively etching the first dielectric layer.
摘要翻译：形成电互连结构的方法包括在半导体衬底上形成电介质层并在电介质层上形成硬掩模层。在硬掩模层的上表面上形成光刻胶层。该图案化的光致抗蚀剂层在步骤期间用作蚀刻掩模，以选择性地蚀刻硬掩模层并在其中限定开口。该开口露出第一电介质层。然后使用暴露硬掩模层的上表面的灰化处理从硬掩模层剥离图案化的光致抗蚀剂层。在该灰化处理之后，使用硬掩模层作为蚀刻掩模来选择性地蚀刻与开口相对延伸的第一电介质层的一部分。在该选择蚀刻步骤期间，聚合物残留物直接堆积在硬掩模层的上表面上。在选择性蚀刻第一介电层的步骤期间，这些聚合物残余物可以操作以增加选择性的程度并抑制硬掩模层的凹陷。

5. 发明授权

US07352064B2 Multiple layer resist scheme implementing etch recipe particular to each layer 有权
标题翻译：多层抗蚀剂方案实现每层特有的蚀刻配方
公开(公告)号：US07352064B2
公开(公告)日：2008-04-01
申请号：US10904323
申请日：2004-11-04
申请人： Nicholas C. M. Fuller , Timothy J. Dalton , Raymond Joy , Yi-hsiung Lin , Chun Hui Low
发明人： Nicholas C. M. Fuller , Timothy J. Dalton , Raymond Joy , Yi-hsiung Lin , Chun Hui Low
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L21/4763
CPC分类号： H01L21/76802 , H01L21/0332 , H01L21/31138 , H01L21/31144
摘要： Methods of forming a metal line and/or via critical dimension (CD) in a single or dual damascene process on a semiconductor substrate, and the resist scheme implemented, are disclosed. The method includes forming a multiple layer resist scheme including a first planarizing layer of a first type material over the substrate, a second dielectric layer of a second type material over the planarizing layer, and a third photoresist layer of a third type material over the dielectric layer. The types of material alternate between organic and inorganic material. The third layer is patterned for the metal line and/or via CD. Sequential etching to form the metal line and/or via critical dimension using a tailored etch recipe particular to each of the first photoresist layer, the second dielectric layer and the third planarizing layer as each layer is exposed is then used. Accurate CD formation and adequate resist budget are provided.
摘要翻译：公开了在半导体衬底上的单镶嵌或双镶嵌工艺中形成金属线和/或通过临界尺寸（CD）的方法和实现的抗蚀剂方案。该方法包括形成多层抗蚀剂方案，该多层抗蚀剂方案包括在该衬底上的第一类型材料的第一平坦化层，平坦化层上的第二类型材料的第二电介质层，以及在电介质上的第三类型材料的第三光致抗蚀剂层层。有机材料和无机材料之间的材料类型是交替的。第三层被图案化为金属线和/或经由CD。然后使用对每一个被暴露的第一光致抗蚀剂层，第二介电层和第三平坦化层中的每一个特定的定制蚀刻配方进行顺序蚀刻以形成金属线和/或通过临界尺寸。提供准确的CD形成和足够的抗蚀剂预算。

6. 发明申请

US20080070409A1 Method of Fabricating Interconnections of Microelectronic Device Using Dual Damascene Process 有权
标题翻译：使用双镶嵌工艺制造微电子器件互连的方法
公开(公告)号：US20080070409A1
公开(公告)日：2008-03-20
申请号：US11532719
申请日：2006-09-18
申请人： Wan-jae Park , Hyung-yoon Choi , Yi-hsiung Lin , Tong Qing Chen
发明人： Wan-jae Park , Hyung-yoon Choi , Yi-hsiung Lin , Tong Qing Chen
IPC分类号： H01L21/44
CPC分类号： H01L21/3146 , H01L21/02115 , H01L21/0212 , H01L21/02167 , H01L21/02271 , H01L21/31116 , H01L21/31144 , H01L21/31155 , H01L21/76807 , H01L21/76825 , H01L21/76829 , H01L2221/1063 , Y10S438/924
摘要： Method of Fabricating Interconnections of a Microelectronic Device Using a Dual Damascene Process. A method of fabricating interconnections of a microelectronic device includes preparing a semiconductor substrate comprising a lower dielectric layer and a lower interconnection, forming an etch stopper layer and an interlayer dielectric layer on the semiconductor substrate, forming a via hole in the interlayer dielectric layer so that the etch stopper layer is exposed through the via hole, performing carbon doping on the etch stopper layer, performing trench etching to form a trench in the interlayer dielectric layer so that the trench overlaps part of the via hole, removing the carbon-doped etch stopper layer, and filling the via hole and the trench with a conductive material to form an upper interconnection.
摘要翻译：使用双镶嵌工艺制造微电子器件互连的方法。制造微电子器件的互连的方法包括制备包括下电介质层和下互连的半导体衬底，在半导体衬底上形成蚀刻停止层和层间电介质层，在层间电介质层中形成通孔，使得蚀刻阻挡层通过通孔露出，在蚀刻停止层上进行碳掺杂，进行沟槽蚀刻以在层间电介质层中形成沟槽，使得沟槽与通孔的一部分重叠，去除碳掺杂的蚀刻阻挡层层，并且用导电材料填充通孔和沟槽以形成上互连。

7. 发明授权

US07488687B2 Methods of forming electrical interconnect structures using polymer residues to increase etching selectivity through dielectric layers 有权
标题翻译：使用聚合物残余物形成电互连结构以通过介电层增加蚀刻选择性的方法
公开(公告)号：US07488687B2
公开(公告)日：2009-02-10
申请号：US11530952
申请日：2006-09-12
申请人： Wan Jae Park , Jae Hak Kim , Tong Qing Chen , Yi-hsiung Lin
发明人： Wan Jae Park , Jae Hak Kim , Tong Qing Chen , Yi-hsiung Lin
IPC分类号： H01L21/00
CPC分类号： H01L21/76802 , H01L21/02063 , H01L21/31116 , H01L21/31144
摘要： Methods of forming electrical interconnect structures include forming a dielectric layer on a semiconductor substrate and forming a hard mask layer on the dielectric layer. A photoresist layer is patterned on an upper surface of the hard mask layer. This patterned photoresist layer is used as an etching mask during a step to selectively etch the hard mask layer and define an opening therein. This opening exposes the first dielectric layer. The patterned photoresist layer is then stripped from the hard mask layer using an ashing process that exposes the upper surface of the hard mask layer. Following this ashing process, a portion of the first dielectric layer extending opposite the opening is selectively etched using the hard mask layer as an etching mask. During this selective etching step, polymer residues are accumulated directly on the upper surface of the hard mask layer. These polymer residues may operate to increase a degree of selectively and inhibit recession of the hard mask layer during the step of selectively etching the first dielectric layer.
摘要翻译：形成电互连结构的方法包括在半导体衬底上形成电介质层并在电介质层上形成硬掩模层。在硬掩模层的上表面上形成光刻胶层。该图案化的光致抗蚀剂层在步骤期间用作蚀刻掩模，以选择性地蚀刻硬掩模层并在其中限定开口。该开口露出第一电介质层。然后使用暴露硬掩模层的上表面的灰化处理从硬掩模层剥离图案化的光致抗蚀剂层。在该灰化处理之后，使用硬掩模层作为蚀刻掩模来选择性地蚀刻与开口相对延伸的第一电介质层的一部分。在该选择蚀刻步骤期间，聚合物残留物直接堆积在硬掩模层的上表面上。在选择性蚀刻第一介电层的步骤期间，这些聚合物残余物可以操作以增加选择性的程度并抑制硬掩模层的凹陷。

8. 发明申请

US20060094230A1 Multiple Layer Resist Scheme Implementing Etch Recipe Particular to Each Layer 有权
标题翻译：多层抗扰性方案实现每层专用的蚀刻配方
公开(公告)号：US20060094230A1
公开(公告)日：2006-05-04
申请号：US10904323
申请日：2004-11-04
申请人： Nicholas Fuller , Timothy Dalton , Raymond Joy , Yi-hsiung Lin , Chun Low
发明人： Nicholas Fuller , Timothy Dalton , Raymond Joy , Yi-hsiung Lin , Chun Low
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/0332 , H01L21/31138 , H01L21/31144
摘要： Methods of forming a metal line and/or via critical dimension (CD) in a single or dual damascene process on a semiconductor substrate, and the resist scheme implemented, are disclosed. The method includes forming a multiple layer resist scheme including a first planarizing layer of a first type material over the substrate, a second dielectric layer of a second type material over the planarizing layer, and a third photoresist layer of a third type material over the dielectric layer. The types of material alternate between organic and inorganic material. The third layer is patterned for the metal line and/or via CD. Sequential etching to form the metal line and/or via critical dimension using a tailored etch recipe particular to each of the first photoresist layer, the second dielectric layer and the third planarizing layer as each layer is exposed is then used. Accurate CD formation and adequate resist budget are provided.
摘要翻译：公开了在半导体衬底上的单镶嵌或双镶嵌工艺中形成金属线和/或通过临界尺寸（CD）的方法和实现的抗蚀剂方案。该方法包括形成多层抗蚀剂方案，该多层抗蚀剂方案包括在该衬底上的第一类型材料的第一平坦化层，平坦化层上的第二类型材料的第二电介质层，以及在电介质上的第三类型材料的第三光致抗蚀剂层层。有机材料和无机材料之间的材料类型是交替的。第三层被图案化为金属线和/或经由CD。然后使用对每一个被暴露的第一光致抗蚀剂层，第二介电层和第三平坦化层中的每一个特定的定制蚀刻配方进行顺序蚀刻以形成金属线和/或通过临界尺寸。提供准确的CD形成和足够的抗蚀剂预算。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式