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1. 发明授权

US07553758B2 Method of fabricating interconnections of microelectronic device using dual damascene process 有权
标题翻译：使用双镶嵌工艺制造微电子器件互连的方法
公开(公告)号：US07553758B2
公开(公告)日：2009-06-30
申请号：US11532719
申请日：2006-09-18
申请人： Wan-jae Park , Hyung-yoon Choi , Yi-hsiung Lin , Tong Qing Chen
发明人： Wan-jae Park , Hyung-yoon Choi , Yi-hsiung Lin , Tong Qing Chen
IPC分类号： H01L21/4763
CPC分类号： H01L21/3146 , H01L21/02115 , H01L21/0212 , H01L21/02167 , H01L21/02271 , H01L21/31116 , H01L21/31144 , H01L21/31155 , H01L21/76807 , H01L21/76825 , H01L21/76829 , H01L2221/1063 , Y10S438/924
摘要： Method of Fabricating Interconnections of a Microelectronic Device Using a Dual Damascene Process. A method of fabricating interconnections of a microelectronic device includes preparing a semiconductor substrate comprising a lower dielectric layer and a lower interconnection, forming an etch stopper layer and an interlayer dielectric layer on the semiconductor substrate, forming a via hole in the interlayer dielectric layer so that the etch stopper layer is exposed through the via hole, performing carbon doping on the etch stopper layer, performing trench etching to form a trench in the interlayer dielectric layer so that the trench overlaps part of the via hole, removing the carbon-doped etch stopper layer, and filling the via hole and the trench with a conductive material to form an upper interconnection.
摘要翻译：使用双镶嵌工艺制造微电子器件互连的方法。制造微电子器件的互连的方法包括制备包括下电介质层和下互连的半导体衬底，在半导体衬底上形成蚀刻停止层和层间电介质层，在层间电介质层中形成通孔，使得蚀刻阻挡层通过通孔露出，在蚀刻停止层上进行碳掺杂，进行沟槽蚀刻以在层间电介质层中形成沟槽，使得沟槽与通孔的一部分重叠，去除碳掺杂的蚀刻阻挡层层，并且用导电材料填充通孔和沟槽以形成上互连。

2. 发明申请

US20080070409A1 Method of Fabricating Interconnections of Microelectronic Device Using Dual Damascene Process 有权
标题翻译：使用双镶嵌工艺制造微电子器件互连的方法
公开(公告)号：US20080070409A1
公开(公告)日：2008-03-20
申请号：US11532719
申请日：2006-09-18
申请人： Wan-jae Park , Hyung-yoon Choi , Yi-hsiung Lin , Tong Qing Chen
发明人： Wan-jae Park , Hyung-yoon Choi , Yi-hsiung Lin , Tong Qing Chen
IPC分类号： H01L21/44
CPC分类号： H01L21/3146 , H01L21/02115 , H01L21/0212 , H01L21/02167 , H01L21/02271 , H01L21/31116 , H01L21/31144 , H01L21/31155 , H01L21/76807 , H01L21/76825 , H01L21/76829 , H01L2221/1063 , Y10S438/924
摘要： Method of Fabricating Interconnections of a Microelectronic Device Using a Dual Damascene Process. A method of fabricating interconnections of a microelectronic device includes preparing a semiconductor substrate comprising a lower dielectric layer and a lower interconnection, forming an etch stopper layer and an interlayer dielectric layer on the semiconductor substrate, forming a via hole in the interlayer dielectric layer so that the etch stopper layer is exposed through the via hole, performing carbon doping on the etch stopper layer, performing trench etching to form a trench in the interlayer dielectric layer so that the trench overlaps part of the via hole, removing the carbon-doped etch stopper layer, and filling the via hole and the trench with a conductive material to form an upper interconnection.
摘要翻译：使用双镶嵌工艺制造微电子器件互连的方法。制造微电子器件的互连的方法包括制备包括下电介质层和下互连的半导体衬底，在半导体衬底上形成蚀刻停止层和层间电介质层，在层间电介质层中形成通孔，使得蚀刻阻挡层通过通孔露出，在蚀刻停止层上进行碳掺杂，进行沟槽蚀刻以在层间电介质层中形成沟槽，使得沟槽与通孔的一部分重叠，去除碳掺杂的蚀刻阻挡层层，并且用导电材料填充通孔和沟槽以形成上互连。

3. 发明授权

US07488687B2 Methods of forming electrical interconnect structures using polymer residues to increase etching selectivity through dielectric layers 有权
标题翻译：使用聚合物残余物形成电互连结构以通过介电层增加蚀刻选择性的方法
公开(公告)号：US07488687B2
公开(公告)日：2009-02-10
申请号：US11530952
申请日：2006-09-12
申请人： Wan Jae Park , Jae Hak Kim , Tong Qing Chen , Yi-hsiung Lin
发明人： Wan Jae Park , Jae Hak Kim , Tong Qing Chen , Yi-hsiung Lin
IPC分类号： H01L21/00
CPC分类号： H01L21/76802 , H01L21/02063 , H01L21/31116 , H01L21/31144
摘要： Methods of forming electrical interconnect structures include forming a dielectric layer on a semiconductor substrate and forming a hard mask layer on the dielectric layer. A photoresist layer is patterned on an upper surface of the hard mask layer. This patterned photoresist layer is used as an etching mask during a step to selectively etch the hard mask layer and define an opening therein. This opening exposes the first dielectric layer. The patterned photoresist layer is then stripped from the hard mask layer using an ashing process that exposes the upper surface of the hard mask layer. Following this ashing process, a portion of the first dielectric layer extending opposite the opening is selectively etched using the hard mask layer as an etching mask. During this selective etching step, polymer residues are accumulated directly on the upper surface of the hard mask layer. These polymer residues may operate to increase a degree of selectively and inhibit recession of the hard mask layer during the step of selectively etching the first dielectric layer.
摘要翻译：形成电互连结构的方法包括在半导体衬底上形成电介质层并在电介质层上形成硬掩模层。在硬掩模层的上表面上形成光刻胶层。该图案化的光致抗蚀剂层在步骤期间用作蚀刻掩模，以选择性地蚀刻硬掩模层并在其中限定开口。该开口露出第一电介质层。然后使用暴露硬掩模层的上表面的灰化处理从硬掩模层剥离图案化的光致抗蚀剂层。在该灰化处理之后，使用硬掩模层作为蚀刻掩模来选择性地蚀刻与开口相对延伸的第一电介质层的一部分。在该选择蚀刻步骤期间，聚合物残留物直接堆积在硬掩模层的上表面上。在选择性蚀刻第一介电层的步骤期间，这些聚合物残余物可以操作以增加选择性的程度并抑制硬掩模层的凹陷。

4. 发明申请

US20080064199A1 Methods of Forming Electrical Interconnect Structures Using Polymer Residues to Increase Etching Selectivity Through Dielectric Layers 有权
标题翻译：使用聚合物残余物形成电互连结构以通过介电层增加蚀刻选择性的方法
公开(公告)号：US20080064199A1
公开(公告)日：2008-03-13
申请号：US11530952
申请日：2006-09-12
申请人： Wan Jae Park , Jae Hak Kim , Tong Qing Chen , Yi-hsiung Lin
发明人： Wan Jae Park , Jae Hak Kim , Tong Qing Chen , Yi-hsiung Lin
IPC分类号： H01L21/44
CPC分类号： H01L21/76802 , H01L21/02063 , H01L21/31116 , H01L21/31144
摘要： Methods of forming electrical interconnect structures include forming a dielectric layer on a semiconductor substrate and forming a hard mask layer on the dielectric layer. A photoresist layer is patterned on an upper surface of the hard mask layer. This patterned photoresist layer is used as an etching mask during a step to selectively etch the hard mask layer and define an opening therein. This opening exposes the first dielectric layer. The patterned photoresist layer is then stripped from the hard mask layer using an ashing process that exposes the upper surface of the hard mask layer. Following this ashing process, a portion of the first dielectric layer extending opposite the opening is selectively etched using the hard mask layer as an etching mask. During this selective etching step, polymer residues are accumulated directly on the upper surface of the hard mask layer. These polymer residues may operate to increase a degree of selectively and inhibit recession of the hard mask layer during the step of selectively etching the first dielectric layer.
摘要翻译：形成电互连结构的方法包括在半导体衬底上形成电介质层并在电介质层上形成硬掩模层。在硬掩模层的上表面上形成光刻胶层。该图案化的光致抗蚀剂层在步骤期间用作蚀刻掩模，以选择性地蚀刻硬掩模层并在其中限定开口。该开口露出第一电介质层。然后使用暴露硬掩模层的上表面的灰化处理从硬掩模层剥离图案化的光致抗蚀剂层。在该灰化处理之后，使用硬掩模层作为蚀刻掩模来选择性地蚀刻与开口相对延伸的第一电介质层的一部分。在该选择蚀刻步骤期间，聚合物残留物直接堆积在硬掩模层的上表面上。在选择性蚀刻第一介电层的步骤期间，这些聚合物残余物可以操作以增加选择性的程度并抑制硬掩模层的凹陷。

5. 发明申请

US20130207108A1 Critical Dimension and Pattern Recognition Structures for Devices Manufactured Using Double Patterning Techniques 有权
标题翻译：使用双重图案化技术制造的器件的关键尺寸和图案识别结构
公开(公告)号：US20130207108A1
公开(公告)日：2013-08-15
申请号：US13371585
申请日：2012-02-13
申请人： Sohan Mehta , Tong Qing Chen , Vikrant Chauhan , Ravi Srivastava , Catherine Labelle , Mark Kelling
发明人： Sohan Mehta , Tong Qing Chen , Vikrant Chauhan , Ravi Srivastava , Catherine Labelle , Mark Kelling
IPC分类号： H01L23/544 , H01L21/311 , H01L21/306
CPC分类号： H01L21/311 , H01L21/31144 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： An illustrative test structure is disclosed herein that includes a plurality of first line features and a plurality of second line features. In this embodiment, each of the second line features have first and second opposing ends and the first and second line features are arranged in a grating pattern such that the first ends of the first line features are aligned to define a first side of the grating structure and the second ends of the first features are aligned to define a second side of the grating structure that is opposite the first side of the grating structure. The first end of the second line features has a first end that extends beyond the first side of the grating structure while the second end of the second line features has a first end that extends beyond the second side of the grating structure.
摘要翻译：本文公开了包括多个第一线特征和多个第二线特征的说明性测试结构。在该实施例中，每个第二线特征具有第一和第二相对端，并且第一和第二线特征被布置成光栅图案，使得第一线特征的第一端对准以限定光栅结构的第一侧并且第一特征的第二端对齐以限定与光栅结构的第一侧相对的光栅结构的第二侧。第二线特征的第一端具有延伸超过光栅结构的第一侧的第一端，而第二线特征的第二端具有延伸超过光栅结构的第二侧的第一端。

6. 发明授权

US06884712B2 Method of manufacturing semiconductor local interconnect and contact 有权
标题翻译：制造半导体局部互连和接触的方法
公开(公告)号：US06884712B2
公开(公告)日：2005-04-26
申请号：US10359975
申请日：2003-02-07
申请人： Pradeep Yelehanka , Tong Qing Chen , Zhi Yong Han , Zhen Jia Zheng , Kelvin Ong , Tian Hao Gu , Syn Kean Cheah
发明人： Pradeep Yelehanka , Tong Qing Chen , Zhi Yong Han , Zhen Jia Zheng , Kelvin Ong , Tian Hao Gu , Syn Kean Cheah
IPC分类号： H01L21/336 , H01L21/60 , H01L21/768 , H01L21/8234 , H01L21/4763
CPC分类号： H01L21/76897 , H01L21/76895 , H01L21/823468 , H01L21/823475 , H01L29/6656
摘要： An integrated circuit, and manufacturing method therefor, is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.
摘要翻译：提供了一种集成电路及其制造方法。分别在半导体衬底上和上方提供栅极电介质和栅极。在栅极电介质附近形成接合部，并且在栅极周围形成成形间隔物。间隔件形成在成形间隔件下方，衬垫形成在间隔件下方。第一电介质层形成在半导体衬底，成形间隔物，间隔物，衬垫和栅极上。在第一电介质层上形成第二电介质层。局部互连开口形成在第二电介质层中，直到第一电介质层。打开第一介电层中的局部互连开口以暴露半导体衬底和第一栅极中的结。第一和第二介电层中的局部互连开口用导电材料填充。

7. 发明授权

US07803704B2 Reliable interconnects 有权
标题翻译：可靠的互连
公开(公告)号：US07803704B2
公开(公告)日：2010-09-28
申请号：US12196291
申请日：2008-08-22
申请人： Bei Chao Zhang , Chim Seng Seet , Juan Boon Tan , Fan Zhang , Yong Chiang Ee , Bo Tao , Tong Qing Chen , Liang Choo Hsia
发明人： Bei Chao Zhang , Chim Seng Seet , Juan Boon Tan , Fan Zhang , Yong Chiang Ee , Bo Tao , Tong Qing Chen , Liang Choo Hsia
IPC分类号： H01L21/4763
CPC分类号： H01L23/5329 , H01L21/76804 , H01L21/76805 , H01L21/76829 , H01L21/76834 , H01L21/76849 , H01L21/76883 , H01L21/76885 , H01L23/5226 , H01L23/5283 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with a dielectric layer formed thereon. The dielectric layer having a conductive line disposed in an upper portion of the dielectric layer. The substrate is processed to produce a top surface of the dielectric layer that is not coplanar with a top surface of the conductive line to form a stepped topography.
摘要翻译：提出了一种形成半导体器件的方法。该方法包括提供用其上形成的电介质层制备的衬底。电介质层具有布置在电介质层上部的导线。处理衬底以产生与导电线的顶表面不共面的电介质层的顶表面，以形成阶梯形状。

8. 发明授权

US07119005B2 Semiconductor local interconnect and contact 有权
标题翻译：半导体局部互连和接触
公开(公告)号：US07119005B2
公开(公告)日：2006-10-10
申请号：US11045202
申请日：2005-01-27
申请人： Pradeep Ramachandramurthy Yelehanka , Tong Qing Chen , Zhi Yong Han , Jia Zhen Zheng , Kelvin Ong , Tian Hao Gu , Syn Kean Cheah
发明人： Pradeep Ramachandramurthy Yelehanka , Tong Qing Chen , Zhi Yong Han , Jia Zhen Zheng , Kelvin Ong , Tian Hao Gu , Syn Kean Cheah
IPC分类号： H01L21/4763 , H01L21/336
CPC分类号： H01L21/76897 , H01L21/76895 , H01L21/823468 , H01L21/823475 , H01L29/6656
摘要： An integrated circuit is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.
摘要翻译：提供集成电路。分别在半导体衬底上和上方提供栅极电介质和栅极。在栅极电介质附近形成接合部，并且在栅极周围形成成形间隔物。间隔件形成在成形间隔件下方，衬垫形成在间隔件下方。第一电介质层形成在半导体衬底，成形间隔物，间隔物，衬垫和栅极上。在第一电介质层上形成第二电介质层。局部互连开口形成在第二电介质层中，直到第一电介质层。打开第一介电层中的局部互连开口以暴露半导体衬底和第一栅极中的结。第一和第二介电层中的局部互连开口用导电材料填充。

9. 发明授权

US08304834B2 Semiconductor local interconnect and contact 有权
标题翻译：半导体局部互连和接触
公开(公告)号：US08304834B2
公开(公告)日：2012-11-06
申请号：US11466350
申请日：2006-08-22
申请人： Pradeep Ramachandramurthy Yelehanka , Tong Qing Chen , Zhi Yong Han , Jia Zhen Zheng , Kelvin Ong , Tian Hao Gu , Syn Kean Cheah
发明人： Pradeep Ramachandramurthy Yelehanka , Tong Qing Chen , Zhi Yong Han , Jia Zhen Zheng , Kelvin Ong , Tian Hao Gu , Syn Kean Cheah
IPC分类号： H01L27/12
CPC分类号： H01L21/76895 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： An integrated circuit is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.
摘要翻译：提供集成电路。分别在半导体衬底上和上方提供栅极电介质和栅极。在栅极电介质附近形成接合部，并且在栅极周围形成成形间隔物。间隔件形成在成形间隔件下方，衬垫形成在间隔件下方。第一电介质层形成在半导体衬底，成形间隔物，间隔物，衬垫和栅极上。在第一电介质层上形成第二电介质层。局部互连开口形成在第二电介质层中，直到第一电介质层。打开第一介电层中的局部互连开口以暴露半导体衬底和第一栅极中的结。第一和第二介电层中的局部互连开口用导电材料填充。

10. 发明申请

US20060281253A1 SEMICONDUCTOR LOCAL INTERCONNECT AND CONTACT 有权
公开(公告)号：US20060281253A1
公开(公告)日：2006-12-14
申请号：US11466350
申请日：2006-08-22
申请人： Pradeep Yelehanka , Tong Qing Chen , Zhi Yong Han , Jia Zheng , Kelvin Ong , Tian Hao Gu , Syn Kean Cheah
发明人： Pradeep Yelehanka , Tong Qing Chen , Zhi Yong Han , Jia Zheng , Kelvin Ong , Tian Hao Gu , Syn Kean Cheah
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L21/76895 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： An integrated circuit is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.
摘要翻译：提供集成电路。分别在半导体衬底上和上方提供栅极电介质和栅极。在栅极电介质附近形成接合部，并且在栅极周围形成成形间隔物。间隔件形成在成形间隔件下方，衬垫形成在间隔件下方。第一电介质层形成在半导体衬底，成形间隔物，间隔物，衬垫和栅极上。在第一电介质层上形成第二电介质层。局部互连开口形成在第二电介质层中，直到第一电介质层。打开第一介电层中的局部互连开口以暴露半导体衬底和第一栅极中的结。第一和第二介电层中的局部互连开口用导电材料填充。

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