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    • 1. 发明申请
    • INSULATED GATE BIPOLAR TRANSISTOR
    • 绝缘栅双极晶体管
    • WO2010116886A9
    • 2011-04-07
    • PCT/JP2010054950
    • 2010-03-23
    • SUMITOMO ELECTRIC INDUSTRIESHARADA SHINWADA KEIJIHIYOSHI TORU
    • HARADA SHINWADA KEIJIHIYOSHI TORU
    • H01L29/12H01L21/336H01L29/739H01L29/78
    • H01L29/7395H01L29/045H01L29/1608H01L29/66068H01L29/78
    • Disclosed is an IGBT (insulated gate bipolar transistor) (1) which is capable of reducing the on-resistance by decreasing the channel mobility. The IGBT (1) comprises: an n-type substrate (11) that is composed of SiC and has a main surface (11A) having an off angle with respect to the {0001} plane direction of not less than 50° but not more than 65°; a p-type withstand voltage maintaining layer (13) that is composed of SiC and formed on the main surface (11A) of the substrate (11); an n-type well region (14) that is so formed as to contain a second main surface (13B) of the withstand voltage maintaining layer (13); an emitter region (15) that is so formed within the well region (14) as to contain the second main surface (13B) and contains a p-type impurity at a higher concentration than the withstand voltage maintaining layer (13); a gate oxide film (17) that is formed on the withstand voltage maintaining layer (13); and a gate electrode (19) that is formed on the gate oxide film (17). In the IGBT (1), a high nitrogen concentration region (22) having a higher nitrogen concentration than the well region (14) and the gate oxide film (17) is formed in a region that contains the interface between the well region (14) and the gate oxide film (17).
    • 公开了一种能够通过降低沟道迁移率来降低导通电阻的IGBT(绝缘栅双极晶体管)(1)。 IGBT(1)包括:n型衬底(11),由SiC构成,并且具有相对于{0001}面方向偏离角不小于50°但不超过50°的主表面(11A) 超过65°; 形成在基板(11)的主面(11A)上的由SiC构成的p型耐压保持层(13)。 形成为包含耐压保持层(13)的第二主表面(13B)的n型阱区(14); 在所述阱区域(14)中形成为包含所述第二主表面(13B)并且包含比所述耐电压保持层(13)更高浓度的p型杂质的发射极区域(15)。 形成在耐压保持层(13)上的栅极氧化膜(17); 以及形成在栅极氧化膜(17)上的栅电极(19)。 在IGBT(1)中,在包含阱区域(14)的界面的区域形成有具有比阱区域(14)和栅极氧化膜(17)高的氮浓度的高氮浓度区域(22) )和栅氧化膜(17)。
    • 5. 发明申请
    • INSULATED GATE FIELD EFFECT TRANSISTOR
    • 绝缘栅场效应晶体管
    • WO2010116887A9
    • 2011-04-07
    • PCT/JP2010054951
    • 2010-03-23
    • SUMITOMO ELECTRIC INDUSTRIESHARADA SHINWADA KEIJIHIYOSHI TORU
    • HARADA SHINWADA KEIJIHIYOSHI TORU
    • H01L29/78H01L29/12
    • H01L29/7828H01L21/049H01L29/045H01L29/1608H01L29/518H01L29/66068H01L29/7838H01L2924/0002H01L2924/00
    • Disclosed is a MOSFET (metal oxide semiconductor field effect transistor) (1) which is capable of reducing the on-resistance by decreasing the channel mobility even when the gate voltage is high. The MOSFET (1) comprises: an n-type substrate (11) that is composed of SiC and has a main surface having an off angle with respect to the {0001} plane of 50-65°; an n-type withstand voltage maintaining layer (13) that is composed of SiC and formed on the main surface (11A) of the substrate (11); a p-type well region (14) that is formed in the withstand voltage maintaining layer (13) at a distance from a first main surface (13A); a gate oxide film (18) that is formed on the well region (14); an n-type contact region (15) that is arranged between the well region (14) and the gate oxide film (18); a channel region (17) that connects the n-type contact region (15) with the withstand voltage maintaining layer (13); and a gate electrode (20) that is arranged on the gate oxide film (18). In the MOSFET (1), a high nitrogen concentration region (23) is formed in a region that contains the interface between the channel region (17) and the gate oxide film (18).
    • 公开了一种MOSFET(金属氧化物半导体场效应晶体管)(1),其即使在栅极电压高时也能够通过降低沟道迁移率来降低导通电阻。 MOSFET(1)包括:n型衬底(11),其由SiC构成,并且具有相对于{0001}面为50-65°的偏角的主表面; 形成在基板(11)的主表面(11A)上的由SiC构成的n型耐压保持层(13); 形成在所述耐电压保持层(13)中距离第一主表面(13A)一定距离的p型阱区(14); 形成在所述阱区域(14)上的栅极氧化膜(18); 布置在阱区(14)和栅氧化膜(18)之间的n型接触区(15); 将所述n型接触区域(15)与所述耐压保持层(13)连接的沟道区域(17)。 和设置在栅氧化膜(18)上的栅电极(20)。 在MOSFET(1)中,在包含沟道区域(17)和栅氧化膜(18)之间的界面的区域中形成高氮浓度区域(23)。