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1. 发明申请

WO2012017796A1 SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCTION THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：WO2012017796A1
公开(公告)日：2012-02-09
申请号：PCT/JP2011066063
申请日：2011-07-14
申请人： SUMITOMO ELECTRIC INDUSTRIES , MASUDA TAKEYOSHI , HARADA SHIN , HONAGA MISAKO , WADA KEIJI , HIYOSHI TORU
发明人： MASUDA TAKEYOSHI , HARADA SHIN , HONAGA MISAKO , WADA KEIJI , HIYOSHI TORU
IPC分类号： H01L29/12 , H01L21/336 , H01L29/06 , H01L29/78 , H01L29/861
CPC分类号： H01L29/66068 , H01L21/046 , H01L21/0475 , H01L21/3065 , H01L29/045 , H01L29/0615 , H01L29/0619 , H01L29/0623 , H01L29/0657 , H01L29/0661 , H01L29/0696 , H01L29/1608 , H01L29/4236 , H01L29/6606 , H01L29/7397 , H01L29/7813 , H01L29/8613 , H01L29/868
摘要： Provided are a semiconductor device which can exhibit properties thereof steadily and has high quality and a process for producing the semiconductor device. The semiconductor device comprises a substrate (1) which has the main surface and silicon carbide layers (2-5) which are formed on the main surface of the substrate (1) and each of which has a side surface that is inclined against the main surface. The side surface substantially contains face [03-3-8]. The side surface contains a channel region.
摘要翻译：提供一种稳定地显示其性能并且具有高质量的半导体器件以及用于制造半导体器件的工艺。半导体器件包括：具有主表面的基板（1）和形成在基板（1）的主表面上的碳化硅层（2-5），并且每个基板具有与主体相反的侧表面表面。侧面基本上包含面[03-3-8]。侧面包含通道区域。

2. 发明申请

WO2010116887A9 INSULATED GATE FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：绝缘栅场效应晶体管
公开(公告)号：WO2010116887A9
公开(公告)日：2011-04-07
申请号：PCT/JP2010054951
申请日：2010-03-23
申请人： SUMITOMO ELECTRIC INDUSTRIES , HARADA SHIN , WADA KEIJI , HIYOSHI TORU
发明人： HARADA SHIN , WADA KEIJI , HIYOSHI TORU
IPC分类号： H01L29/78 , H01L29/12
CPC分类号： H01L29/7828 , H01L21/049 , H01L29/045 , H01L29/1608 , H01L29/518 , H01L29/66068 , H01L29/7838 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a MOSFET (metal oxide semiconductor field effect transistor) (1) which is capable of reducing the on-resistance by decreasing the channel mobility even when the gate voltage is high. The MOSFET (1) comprises: an n-type substrate (11) that is composed of SiC and has a main surface having an off angle with respect to the {0001} plane of 50-65°; an n-type withstand voltage maintaining layer (13) that is composed of SiC and formed on the main surface (11A) of the substrate (11); a p-type well region (14) that is formed in the withstand voltage maintaining layer (13) at a distance from a first main surface (13A); a gate oxide film (18) that is formed on the well region (14); an n-type contact region (15) that is arranged between the well region (14) and the gate oxide film (18); a channel region (17) that connects the n-type contact region (15) with the withstand voltage maintaining layer (13); and a gate electrode (20) that is arranged on the gate oxide film (18). In the MOSFET (1), a high nitrogen concentration region (23) is formed in a region that contains the interface between the channel region (17) and the gate oxide film (18).
摘要翻译：公开了一种MOSFET（金属氧化物半导体场效应晶体管）（1），其即使在栅极电压高时也能够通过降低沟道迁移率来降低导通电阻。 MOSFET（1）包括：n型衬底（11），其由SiC构成，并且具有相对于{0001}面为50-65°的偏角的主表面; 形成在基板（11）的主表面（11A）上的由SiC构成的n型耐压保持层（13）; 形成在所述耐电压保持层（13）中距离第一主表面（13A）一定距离的p型阱区（14）; 形成在所述阱区域（14）上的栅极氧化膜（18）; 布置在阱区（14）和栅氧化膜（18）之间的n型接触区（15）; 将所述n型接触区域（15）与所述耐压保持层（13）连接的沟道区域（17）。和设置在栅氧化膜（18）上的栅电极（20）。在MOSFET（1）中，在包含沟道区域（17）和栅氧化膜（18）之间的界面的区域中形成高氮浓度区域（23）。

3. 发明申请

WO2010116886A9 INSULATED GATE BIPOLAR TRANSISTOR 审中-公开
标题翻译：绝缘栅双极晶体管
公开(公告)号：WO2010116886A9
公开(公告)日：2011-04-07
申请号：PCT/JP2010054950
申请日：2010-03-23
申请人： SUMITOMO ELECTRIC INDUSTRIES , HARADA SHIN , WADA KEIJI , HIYOSHI TORU
发明人： HARADA SHIN , WADA KEIJI , HIYOSHI TORU
IPC分类号： H01L29/12 , H01L21/336 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7395 , H01L29/045 , H01L29/1608 , H01L29/66068 , H01L29/78
摘要： Disclosed is an IGBT (insulated gate bipolar transistor) (1) which is capable of reducing the on-resistance by decreasing the channel mobility. The IGBT (1) comprises: an n-type substrate (11) that is composed of SiC and has a main surface (11A) having an off angle with respect to the {0001} plane direction of not less than 50° but not more than 65°; a p-type withstand voltage maintaining layer (13) that is composed of SiC and formed on the main surface (11A) of the substrate (11); an n-type well region (14) that is so formed as to contain a second main surface (13B) of the withstand voltage maintaining layer (13); an emitter region (15) that is so formed within the well region (14) as to contain the second main surface (13B) and contains a p-type impurity at a higher concentration than the withstand voltage maintaining layer (13); a gate oxide film (17) that is formed on the withstand voltage maintaining layer (13); and a gate electrode (19) that is formed on the gate oxide film (17). In the IGBT (1), a high nitrogen concentration region (22) having a higher nitrogen concentration than the well region (14) and the gate oxide film (17) is formed in a region that contains the interface between the well region (14) and the gate oxide film (17).
摘要翻译：公开了一种能够通过降低沟道迁移率来降低导通电阻的IGBT（绝缘栅双极晶体管）（1）。 IGBT（1）包括：n型衬底（11），由SiC构成，并且具有相对于{0001}面方向偏离角不小于50°但不超过50°的主表面（11A）超过65°; 形成在基板（11）的主面（11A）上的由SiC构成的p型耐压保持层（13）。形成为包含耐压保持层（13）的第二主表面（13B）的n型阱区（14）; 在所述阱区域（14）中形成为包含所述第二主表面（13B）并且包含比所述耐电压保持层（13）更高浓度的p型杂质的发射极区域（15）。形成在耐压保持层（13）上的栅极氧化膜（17）; 以及形成在栅极氧化膜（17）上的栅电极（19）。在IGBT（1）中，在包含阱区域（14）的界面的区域形成有具有比阱区域（14）和栅极氧化膜（17）高的氮浓度的高氮浓度区域（22））和栅氧化膜（17）。

4. 发明申请

WO2011108137A9 METHOD FOR PRODUCING SILICON CARBIDE SUBSTRATE 审中-公开
标题翻译：生产碳化硅衬底的方法
公开(公告)号：WO2011108137A9
公开(公告)日：2011-10-27
申请号：PCT/JP2010066829
申请日：2010-09-28
申请人： SUMITOMO ELECTRIC INDUSTRIES , NISHIGUCHI TARO , SASAKI MAKOTO , HARADA SHIN , OKITA KYOKO , INOUE HIROKI , NAMIKAWA YASUO
发明人： NISHIGUCHI TARO , SASAKI MAKOTO , HARADA SHIN , OKITA KYOKO , INOUE HIROKI , NAMIKAWA YASUO
IPC分类号： C30B29/36 , C30B33/06 , H01L21/203
CPC分类号： C30B29/36 , C30B23/025 , C30B33/06 , H01L21/02002 , H01L21/02378 , H01L21/02529 , H01L21/02631 , H01L29/1608
摘要： A support section (30c) made from silicon carbide has undulations on at least a portion of the primary surface (F0) thereof. The support section (30c) and at least one monocrystalline substrate (11) are stacked in a manner so that the back surface (B1) of each of the at least one monocrystalline substrate (11) formed from silicon carbide makes contact with the primary surface (F0) of the support section (30c) that has undulations formed. In order to join the back surface (B1) of each of the at least one monocrystalline substrate (11) to the support section (30c), the support section (30c) and the at least one monocrystalline substrate (11) are heated in a manner such that the temperature of the support section (30c) exceeds the sublimation temperature of silicon carbide, and the temperature of each of the at least one monocrystalline substrate (11) is less than the temperature of the aforementioned support section (30c).
摘要翻译：由碳化硅制成的支撑部分（30c）在其主表面（F0）的至少一部分上具有起伏。支撑部分（30c）和至少一个单晶衬底（11）以这样的方式堆叠，使得由碳化硅形成的至少一个单晶衬底（11）中的每一个的背表面（B1）与主表面（30c）的形成有起伏的部分（F0）。为了将至少一个单晶衬底（11）中的每一个的背表面（B1）接合到支撑部分（30c），将支撑部分（30c）和至少一个单晶衬底（11）在（30c）的温度超过碳化硅的升华温度，并且至少一个单晶衬底（11）中的每一个的温度小于上述支撑部分（30c）的温度。

5. 发明申请

WO2010119792A1 SUBSTRATE, SUBSTRATE PROVIDED WITH THIN FILM, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：衬底，具有薄膜的衬底，半导体器件和制造半导体器件的方法
公开(公告)号：WO2010119792A1
公开(公告)日：2010-10-21
申请号：PCT/JP2010056206
申请日：2010-04-06
申请人： SUMITOMO ELECTRIC INDUSTRIES , HARADA SHIN , SASAKI MAKOTO , MASUDA TAKEYOSHI
发明人： HARADA SHIN , SASAKI MAKOTO , MASUDA TAKEYOSHI
IPC分类号： C30B29/36 , C23C16/32 , C23C16/42 , C30B25/20 , H01L21/02 , H01L21/205 , H01L21/329 , H01L21/336 , H01L21/337 , H01L21/338 , H01L29/12 , H01L29/47 , H01L29/78 , H01L29/80 , H01L29/808 , H01L29/812 , H01L29/861 , H01L29/872
CPC分类号： H01L29/808 , B24B7/17 , B24B7/228 , B24B37/08 , B24B37/10 , C30B25/20 , C30B29/36 , H01L21/02378 , H01L21/0243 , H01L21/02529 , H01L21/0465 , H01L29/02 , H01L29/045 , H01L29/063 , H01L29/0657 , H01L29/1608 , H01L29/66068 , H01L29/78 , H01L29/7802 , H01L29/7813 , H01L29/8083 , H01L29/812 , H01L29/8122 , H01L29/8128 , H01L29/8611 , H01L29/872
摘要： Provided are a substrate which suppresses deterioration of processing accuracy of a semiconductor device due to the warping of the substrate, a substrate provided with a thin film, a semiconductor device formed using the abovementioned substrate, and a method for manufacturing said semiconductor device. In the substrate (1), the diameter of the main surface (1a) is 2 inches or more, the bow value of the main surface (1a) is -40 µm to -5 µm, and the warp value of the main surface (1a) is 5 µm to 40 µm. The value of the surface roughness (Ra) of the main surface (1a) of the substrate (1) is preferably 1 nm or less and the value of the surface roughness (Ra) of the main surface (1b) is preferably 100 nm or less.
摘要翻译：提供了抑制由于基板的翘曲，设置有薄膜的基板，使用上述基板形成的半导体装置引起的半导体装置的加工精度劣化的基板及其制造方法。在基板（1）中，主表面（1a）的直径为2英寸以上，主面（1a）的弓形值为-40〜-5μm，主表面的翘曲值 1a）为5μm〜40μm。基板（1）的主表面（1a）的表面粗糙度（Ra）的值优选为1nm以下，主面（1b）的表面粗糙度（Ra）的值优选为100nm，减。

6. 发明申请

WO2011065239A9 METHOD FOR PRODUCING MONOCRYSTAL 审中-公开
标题翻译：生产单晶的方法
公开(公告)号：WO2011065239A9
公开(公告)日：2011-09-29
申请号：PCT/JP2010070175
申请日：2010-11-12
申请人： SUMITOMO ELECTRIC INDUSTRIES , NISHIGUCHI TARO , SASAKI MAKOTO , HARADA SHIN
发明人： NISHIGUCHI TARO , SASAKI MAKOTO , HARADA SHIN
IPC分类号： C30B23/08 , C30B29/36
CPC分类号： C30B29/36 , C30B23/025
摘要： In the disclosed method, a seed crystal (11) having a front surface and a rear surface is prepared. The surface roughness of the rear surface of the seed crystal (11) is increased. A coating film containing carbon is formed on the rear surface of the seed crystal. The coating film and a seat (41) are put in contact with each other, sandwiching an adhesive. The adhesive is cured in order to affix the seed crystal (11) to the seat (41). A monocrystal (52) is grown on the seed crystal (11). Before performing the abovementioned growth, a carbon film (22) is formed by means of carbonizing the abovementioned coating film.
摘要翻译：在所公开的方法中，制备具有前表面和后表面的晶种（11）。晶种（11）的后表面的表面粗糙度增加。在籽晶的背面形成含有碳的涂膜。涂膜和座（41）彼此接触，夹着粘合剂。固化粘合剂以将晶种（11）固定到座（41）上。在晶种（11）上生长单晶（52）。在进行上述生长之前，通过碳化上述涂膜形成碳膜（22）。

7. 发明申请

WO2011058830A9 METHOD FOR MANUFACTURING A SEMICONDUCTOR SUBSTRATE 审中-公开
标题翻译：制造半导体衬底的方法
公开(公告)号：WO2011058830A9
公开(公告)日：2011-08-25
申请号：PCT/JP2010066831
申请日：2010-09-28
申请人： SUMITOMO ELECTRIC INDUSTRIES , SASAKI MAKOTO , HARADA SHIN , NISHIGUCHI TARO , OKITA KYOKO , NAMIKAWA YASUO
发明人： SASAKI MAKOTO , HARADA SHIN , NISHIGUCHI TARO , OKITA KYOKO , NAMIKAWA YASUO
IPC分类号： H01L21/02 , H01L21/20 , H01L21/205 , H01L21/265 , H01L21/336 , H01L29/78
CPC分类号： H01L21/02667 , H01L21/02378 , H01L21/0243 , H01L21/02529 , H01L21/02612 , H01L21/02614 , H01L21/02656 , H01L21/047 , H01L21/0475 , H01L29/045 , H01L29/66068 , H01L29/7802
摘要： In the provided method for manufacturing a semiconductor substrate, a composite substrate (80P) that has a support section (30) and first and second silicon carbide substrates (11, 12) is prepared. There is a gap (GP) with an opening (CR) between the first and second silicon carbide substrates (11, 12). A plug layer for the gap (GP) is formed above the opening (CR). The plug layer includes at a silicon layer, at least. The silicon layer is carbonized to form a lid (70) comprising silicon carbide that plugs the gap (GP) above the opening (CR). Depositing a sublimate from respective first and second lateral surfaces (S1, S2) of the first and second silicon carbide substrates (11, 12) onto the lid (70) forms a joining part that plugs up the opening (CR). The lid (70) is then removed.
摘要翻译：在所提供的用于制造半导体衬底的方法中，制备具有支撑部分（30）和第一和第二碳化硅衬底（11,12）的复合衬底（80P）。在第一和第二碳化硅衬底（11,12）之间存在具有开口（CR）的间隙（GP）。用于间隙（GP）的塞层形成在开口（CR）上方。插塞层至少包括硅层。硅层被碳化以形成包含碳化硅的盖子（70），其封闭开口（CR）上方的间隙（GP）。将来自第一和第二碳化硅衬底（11,12）的相应第一和第二侧表面（S1，S2）的升华物沉积到盖子（70）上形成堵塞开口（CR）的接合部分。然后移除盖（70）。

8. 发明专利

CA2774314A1 COMPOSITE SUBSTRATGE HAVING SINGLE-CRYSTAL SILICON CARBIDE SUBSTRATE 未知
公开(公告)号：CA2774314A1
公开(公告)日：2012-04-19
申请号：CA2774314
申请日：2011-06-17
申请人： SUMITOMO ELECTRIC INDUSTRIES
发明人： HORI TSUTOMU , HARADA SHIN , INOUE HIROKI , SASAKI MAKOTO , ITOH SATOMI , NAMIKAWA YASUO
IPC分类号： B32B3/14 , B32B18/00 , C30B19/12 , C30B29/36
摘要： A first vertex (P1) of a first single-crystal silicon carbide substrate (11) and a second vertex (P2) of a second single-crystal silicon carbide substrate (12) abut each other such that a first side (S1) of the first single-crystal silicon carbide substrate (11) and a second side (S2) of the second single-crystal silicon carbide substrate (12) are aligned. In addition, at least a part of the first side (S1) and at least a part of the second side (S2) abut on a third side (S3) of a third single-crystal silicon carbide substrate (13). Thus, in manufacturing a semiconductor device including a composite substrate, process fluctuations caused by a gap between the single-crystal silicon carbide substrates can be suppressed.

9. 发明专利

CA2783310A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 未知
公开(公告)号：CA2783310A1
公开(公告)日：2012-02-09
申请号：CA2783310
申请日：2011-07-14
申请人： SUMITOMO ELECTRIC INDUSTRIES
发明人： MASUDA TAKEYOSHI , HARADA SHIN , HONAGA MISAKO , WADA KEIJI , HIYOSHI TORU
IPC分类号： H01L29/12 , H01L21/336 , H01L29/06 , H01L29/78 , H01L29/861
摘要： Provided are a semiconductor device which can exhibit properties thereof steadily and has high quality and a process for producing the semiconductor device. The semiconductor device comprises a substrate (1) which has the main surface and silicon carbide layers (2-5) which are formed on the main surface of the substrate (1) and each of which has a side surface that is inclined against the main surface. The side surface substantially contains face [03-3-8]. The side surface contains a channel region.

10. 发明专利

CA2760162A1 SILICON CARBIDE SUBSTRATE, EPITAXIAL LAYER PROVIDED SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE 未知
公开(公告)号：CA2760162A1
公开(公告)日：2011-12-09
申请号：CA2760162
申请日：2011-02-21
申请人： SUMITOMO ELECTRIC INDUSTRIES
发明人： SHIOMI HIROMU , TAMASO HIDETO , HARADA SHIN , TSUNO TAKASHI , NAMIKAWA YASUO
IPC分类号： H01L29/24 , H01L21/20 , H01L21/302 , H01L29/04
摘要： The present invention provides a silicon carbide substrate, an epitaxial layer provided substrate. a semiconductor device, and a method for manufacturing the silicon carbide substrate, each of which achieves reduced on-resistance. The silicon carbide substrate (10) is a silicon carbide substrate (10) having a main surface, and includes: a SiC single-crystal substrate (1) formed in at least a portion of the main surface; and a base member (20) disposed to surround the SiC single-crystal substrate (1). The base member (20) includes a boundary region (11) and a base region (12). The boundary region (11) is adjacent to the SiC single-crystal substrate (1) in a direction along the main surface, and has a crystal grain boundary therein. The base region (12) is adjacent to the SiC single-crystal substrate (1) in a direction perpendicular to the main surface, and has an impurity concentration higher than that of the SiC single-crystal substrate (1).

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