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1. 发明申请

WO2010134415A9 SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：WO2010134415A9
公开(公告)日：2011-08-25
申请号：PCT/JP2010057112
申请日：2010-04-22
申请人： SUMITOMO ELECTRIC INDUSTRIES , WADA KEIJI , TAMASO HIDETO , MASUDA TAKEYOSHI , HONAGA MISAKO
发明人： WADA KEIJI , TAMASO HIDETO , MASUDA TAKEYOSHI , HONAGA MISAKO
IPC分类号： H01L21/28 , H01L21/336 , H01L21/337 , H01L21/768 , H01L29/12 , H01L29/417 , H01L29/78 , H01L29/808
CPC分类号： H01L21/0485 , H01L21/0455 , H01L29/1608 , H01L29/401 , H01L29/45 , H01L29/66068 , H01L29/7802 , H01L29/808
摘要： Disclosed is a silicon carbide semiconductor device which, when the electrode material is different from the material of the internal interconnects, eliminates the possibility of trouble at the contact interface of these different metals, and has high reliability even after long periods of use. The semiconductor device is provided with contact electrodes (16) which contact silicon carbide (14, 18), and interconnects (19) which connect with the contact electrodes. The contact electrodes (16) are formed from an alloy containing titanium, aluminum, and silicon. The interconnects (19) are formed either from aluminum or aluminum alloy and are connected with the contact electrodes by contacting the contact electrodes.
摘要翻译：公开了一种碳化硅半导体器件，当电极材料与内部互连的材料不同时，消除了在这些不同金属的接触界面处的麻烦的可能性，并且即使在长时间使用后也具有高可靠性。半导体器件具有接触碳化硅（14,18）的接触电极（16）和与接触电极连接的互连（19）。接触电极（16）由含有钛，铝和硅的合金形成。互连（19）由铝或铝合金形成，并通过接触电极与接触电极连接。

2. 发明申请

WO2012017796A1 SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCTION THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：WO2012017796A1
公开(公告)日：2012-02-09
申请号：PCT/JP2011066063
申请日：2011-07-14
申请人： SUMITOMO ELECTRIC INDUSTRIES , MASUDA TAKEYOSHI , HARADA SHIN , HONAGA MISAKO , WADA KEIJI , HIYOSHI TORU
发明人： MASUDA TAKEYOSHI , HARADA SHIN , HONAGA MISAKO , WADA KEIJI , HIYOSHI TORU
IPC分类号： H01L29/12 , H01L21/336 , H01L29/06 , H01L29/78 , H01L29/861
CPC分类号： H01L29/66068 , H01L21/046 , H01L21/0475 , H01L21/3065 , H01L29/045 , H01L29/0615 , H01L29/0619 , H01L29/0623 , H01L29/0657 , H01L29/0661 , H01L29/0696 , H01L29/1608 , H01L29/4236 , H01L29/6606 , H01L29/7397 , H01L29/7813 , H01L29/8613 , H01L29/868
摘要： Provided are a semiconductor device which can exhibit properties thereof steadily and has high quality and a process for producing the semiconductor device. The semiconductor device comprises a substrate (1) which has the main surface and silicon carbide layers (2-5) which are formed on the main surface of the substrate (1) and each of which has a side surface that is inclined against the main surface. The side surface substantially contains face [03-3-8]. The side surface contains a channel region.
摘要翻译：提供一种稳定地显示其性能并且具有高质量的半导体器件以及用于制造半导体器件的工艺。半导体器件包括：具有主表面的基板（1）和形成在基板（1）的主表面上的碳化硅层（2-5），并且每个基板具有与主体相反的侧表面表面。侧面基本上包含面[03-3-8]。侧面包含通道区域。

3. 发明申请

WO2012077443A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：WO2012077443A1
公开(公告)日：2012-06-14
申请号：PCT/JP2011075590
申请日：2011-11-07
申请人： SUMITOMO ELECTRIC INDUSTRIES , KUBOTA RYOSUKE , WADA KEIJI , MASUDA TAKEYOSHI , SHIOMI HIROMU
发明人： KUBOTA RYOSUKE , WADA KEIJI , MASUDA TAKEYOSHI , SHIOMI HIROMU
IPC分类号： H01L21/265 , H01L21/336 , H01L29/12 , H01L29/78
CPC分类号： H01L29/7802 , H01L21/046 , H01L21/268 , H01L29/1608 , H01L29/66068
摘要： A silicon carbide substrate having a surface is prepared. Impurity regions (123-125) are formed by carrying out ion implantation into the silicon carbide substrate through the surface. Annealing is carried out for the purpose of activating the impurity regions. The annealing comprises: a step for irradiating the surface of the silicon carbide substrate with first laser light that has a first wavelength; and a step for irradiating the surface of the silicon carbide substrate with second laser light that has a second wavelength. The silicon carbide substrate has first and second extinction coefficients respectively at the first and second wavelengths. The ratio of the first extinction coefficient to the first wavelength is larger than 5 × 105/m. The ratio of the second extinction coefficient to the second wavelength is smaller than 5 × 105/m. Consequently, damage to the surface of the silicon carbide substrate during the laser annealing can be reduced.
摘要翻译：制备具有表面的碳化硅衬底。杂质区域（123-125）通过经由表面对碳化硅基板进行离子注入而形成。退火是为了激活杂质区而进行的。退火包括：用具有第一波长的第一激光照射碳化硅衬底的表面的步骤; 以及用具有第二波长的第二激光照射碳化硅衬底的表面的步骤。碳化硅衬底分别在第一和第二波长处具有第一和第二消光系数。第一消光系数与第一波长的比率大于5×105 / m。第二消光系数与第二波长的比率小于5×105 / m。因此，可以减少激光退火过程中碳化硅衬底表面的损坏。

4. 发明申请

WO2010116886A9 INSULATED GATE BIPOLAR TRANSISTOR 审中-公开
标题翻译：绝缘栅双极晶体管
公开(公告)号：WO2010116886A9
公开(公告)日：2011-04-07
申请号：PCT/JP2010054950
申请日：2010-03-23
申请人： SUMITOMO ELECTRIC INDUSTRIES , HARADA SHIN , WADA KEIJI , HIYOSHI TORU
发明人： HARADA SHIN , WADA KEIJI , HIYOSHI TORU
IPC分类号： H01L29/12 , H01L21/336 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7395 , H01L29/045 , H01L29/1608 , H01L29/66068 , H01L29/78
摘要： Disclosed is an IGBT (insulated gate bipolar transistor) (1) which is capable of reducing the on-resistance by decreasing the channel mobility. The IGBT (1) comprises: an n-type substrate (11) that is composed of SiC and has a main surface (11A) having an off angle with respect to the {0001} plane direction of not less than 50° but not more than 65°; a p-type withstand voltage maintaining layer (13) that is composed of SiC and formed on the main surface (11A) of the substrate (11); an n-type well region (14) that is so formed as to contain a second main surface (13B) of the withstand voltage maintaining layer (13); an emitter region (15) that is so formed within the well region (14) as to contain the second main surface (13B) and contains a p-type impurity at a higher concentration than the withstand voltage maintaining layer (13); a gate oxide film (17) that is formed on the withstand voltage maintaining layer (13); and a gate electrode (19) that is formed on the gate oxide film (17). In the IGBT (1), a high nitrogen concentration region (22) having a higher nitrogen concentration than the well region (14) and the gate oxide film (17) is formed in a region that contains the interface between the well region (14) and the gate oxide film (17).
摘要翻译：公开了一种能够通过降低沟道迁移率来降低导通电阻的IGBT（绝缘栅双极晶体管）（1）。 IGBT（1）包括：n型衬底（11），由SiC构成，并且具有相对于{0001}面方向偏离角不小于50°但不超过50°的主表面（11A）超过65°; 形成在基板（11）的主面（11A）上的由SiC构成的p型耐压保持层（13）。形成为包含耐压保持层（13）的第二主表面（13B）的n型阱区（14）; 在所述阱区域（14）中形成为包含所述第二主表面（13B）并且包含比所述耐电压保持层（13）更高浓度的p型杂质的发射极区域（15）。形成在耐压保持层（13）上的栅极氧化膜（17）; 以及形成在栅极氧化膜（17）上的栅电极（19）。在IGBT（1）中，在包含阱区域（14）的界面的区域形成有具有比阱区域（14）和栅极氧化膜（17）高的氮浓度的高氮浓度区域（22））和栅氧化膜（17）。

5. 发明申请

WO2010116887A9 INSULATED GATE FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：绝缘栅场效应晶体管
公开(公告)号：WO2010116887A9
公开(公告)日：2011-04-07
申请号：PCT/JP2010054951
申请日：2010-03-23
申请人： SUMITOMO ELECTRIC INDUSTRIES , HARADA SHIN , WADA KEIJI , HIYOSHI TORU
发明人： HARADA SHIN , WADA KEIJI , HIYOSHI TORU
IPC分类号： H01L29/78 , H01L29/12
CPC分类号： H01L29/7828 , H01L21/049 , H01L29/045 , H01L29/1608 , H01L29/518 , H01L29/66068 , H01L29/7838 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a MOSFET (metal oxide semiconductor field effect transistor) (1) which is capable of reducing the on-resistance by decreasing the channel mobility even when the gate voltage is high. The MOSFET (1) comprises: an n-type substrate (11) that is composed of SiC and has a main surface having an off angle with respect to the {0001} plane of 50-65°; an n-type withstand voltage maintaining layer (13) that is composed of SiC and formed on the main surface (11A) of the substrate (11); a p-type well region (14) that is formed in the withstand voltage maintaining layer (13) at a distance from a first main surface (13A); a gate oxide film (18) that is formed on the well region (14); an n-type contact region (15) that is arranged between the well region (14) and the gate oxide film (18); a channel region (17) that connects the n-type contact region (15) with the withstand voltage maintaining layer (13); and a gate electrode (20) that is arranged on the gate oxide film (18). In the MOSFET (1), a high nitrogen concentration region (23) is formed in a region that contains the interface between the channel region (17) and the gate oxide film (18).
摘要翻译：公开了一种MOSFET（金属氧化物半导体场效应晶体管）（1），其即使在栅极电压高时也能够通过降低沟道迁移率来降低导通电阻。 MOSFET（1）包括：n型衬底（11），其由SiC构成，并且具有相对于{0001}面为50-65°的偏角的主表面; 形成在基板（11）的主表面（11A）上的由SiC构成的n型耐压保持层（13）; 形成在所述耐电压保持层（13）中距离第一主表面（13A）一定距离的p型阱区（14）; 形成在所述阱区域（14）上的栅极氧化膜（18）; 布置在阱区（14）和栅氧化膜（18）之间的n型接触区（15）; 将所述n型接触区域（15）与所述耐压保持层（13）连接的沟道区域（17）。和设置在栅氧化膜（18）上的栅电极（20）。在MOSFET（1）中，在包含沟道区域（17）和栅氧化膜（18）之间的界面的区域中形成高氮浓度区域（23）。

6. 发明申请

WO2014188794A1 SILICON CARBIDE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：硅碳化硅半导体器件
公开(公告)号：WO2014188794A1
公开(公告)日：2014-11-27
申请号：PCT/JP2014059726
申请日：2014-04-02
申请人： SUMITOMO ELECTRIC INDUSTRIES
发明人： WADA KEIJI , KANBARA KENJI
IPC分类号： H01L29/47 , H01L29/872
CPC分类号： H01L29/872 , H01L21/046 , H01L21/0495 , H01L29/0619 , H01L29/1608 , H01L29/36 , H01L29/47 , H01L29/6606
摘要： This silicon carbide semiconductor device (1) is provided with a silicon carbide layer (10), an insulating layer (20), a Schottky electrode (50) and a reaction region (2). The silicon carbide layer (10) contains a p-type region (3) that is in contact with a first main surface (10a) and an n-type region (14) that is in contact with the p-type region (3) and the first main surface (10a). The insulating layer (20) has a third main surface (20a), a fourth main surface (20b) and a side wall surface (20c) that communicates with the third main surface (20a) and the fourth main surface (20b), and the fourth main surface (20b) is in contact with the first main surface (10a). The Schottky electrode (50) is in contact with the first main surface (10a) and the side wall surface (20c). The reaction region (2) is in contact with the insulating layer (20), the Schottky electrode (50) and the p-type region (3). The reaction region (2) contains the elements that constitute the Schottky electrode (50), the elements that constitute the insulating layer (20), silicon and carbon. Consequently, there is provided a silicon carbide semiconductor device which has high withstand voltage and is capable of suppressing deterioration of the withstand voltage over time.
摘要翻译：该碳化硅半导体器件（1）具有碳化硅层（10），绝缘层（20），肖特基电极（50）和反应区域（2）。碳化硅层（10）包含与第一主表面（10a）接触的p型区域（3）和与p型区域（3）接触的n型区域（14）和第一主表面（10a）。绝缘层（20）具有与第三主表面（20a）和第四主表面（20b）连通的第三主表面（20a），第四主表面（20b）和侧壁表面（20c），以及第四主表面20b与第一主表面10a接触。肖特基电极（50）与第一主表面（10a）和侧壁表面（20c）接触。反应区域（2）与绝缘层（20），肖特基电极（50）和p型区域（3）接触。反应区域（2）包含构成肖特基电极（50）的元件，构成绝缘层（20）的元素，硅和碳。因此，提供了具有高耐受电压并能够抑制耐久电压劣化的碳化硅半导体器件。

7. 发明专利

JPH1033087A NON-HUMAN ANIMAL HAVING FUNCTIONALLY DEFECTIVE GLUTAMATE TRANSPORTER GENE 失效
公开(公告)号：JPH1033087A
公开(公告)日：1998-02-10
申请号：JP19365596
申请日：1996-07-23
申请人： TANAKA KOICHI , WADA KEIJI
发明人： TANAKA KOICHI , WADA KEIJI
IPC分类号： A01K67/027 , C12N15/09
摘要： PROBLEM TO BE SOLVED: To obtain non-human animal which has the functional defects of glutamate transporter gene in the chromosome of its somatic cells or in its productive cells and is useful for study on the physiological functions of proteins, elucidation of morbid physiology and causes of neurodegenerative diseases. SOLUTION: This non-human animal has a glutamate transporter gene, for example, GluT-1 gene and/or GlT1 gene, having deficiency in some part or having another gene such as a marker gene or a neomycin-resistant gene in the chromosome of its somatic cells or productive cells. This non-human animal is preferably a rodent, for example, mouse or the like.

8. 发明专利

JP2002274460A HEAD LAMP FOR BICYCLE PROVIDED WITH CONDENSED EMITTER 失效
公开(公告)号：JP2002274460A
公开(公告)日：2002-09-25
申请号：JP2001136689
申请日：2001-03-19
申请人： WADA KEIJI
发明人： WADA KEIJI
IPC分类号： B62J6/02 , F21S8/10 , F21W107/13 , F21Y105/00
摘要： PROBLEM TO BE SOLVED: To avoid a dangerous case that a bicycle is invisible for other person during not only its running but also its stop by securely emitting light of a head lamp when it stops at night so as to prevent the occurrence of an accident of the bicycle. SOLUTION: A condensed emitter 5 formed by a member containing condensed pigment is vertically attached to an inner face of an exterior case 1 by facing a lamp bulb 2 and a reflecting mirror 4 from a cover glass 3. Light of the lamp bulb 2 lit during running of the bicycle is stored in the condensed emitter 5 to emit light when it stops and the lamp bulb is turned off in order to let an oncoming car and a pedestrian recognize the existence of the bicycle so as to ensure safety.

9. 发明专利

DE112016004430T5 Verfahren zur Herstellung eines Siliziumkarbid-Epitaxiesubstrats, Verfahren zur Herstellung einer Siliziumkarbid-Halbleitervorrichtung und Vorrichtung zur Herstellung eines Siliziumkarbid-Epitaxiesubstrats 未知
公开(公告)号：DE112016004430T5
公开(公告)日：2018-07-05
申请号：DE112016004430
申请日：2016-08-02
申请人： SUMITOMO ELECTRIC INDUSTRIES
发明人： WADA KEIJI , DOI HIDEYUKI , ITOH HIRONORI
IPC分类号： H01L21/205 , C30B29/36 , H01L21/20 , H01L21/336 , H01L29/12 , H01L29/78
摘要： Bei der Bildung einer Siliziumkarbidschicht fallen, wenn eine X-Achse einen ersten Wert anzeigt, der in Prozenten einen Wert darstellt, der durch Dividieren einer Strömungsrate des Silans durch eine Strömungsrate des Wasserstoffs erhalten wird, und wenn eine Y-Achse einen zweiten Wert anzeigt, der eine Strömungsrate des Ammoniaks in sccm darstellt, der erste Wert und der zweite Wert in einen viereckigen Bereich, der von ersten Koordinaten, zweiten Koordinaten, dritten Koordinaten und vierten Koordinaten in XY-Ebenenkoordinaten umgeben ist. Die ersten Koordinaten sind (0,05, 6,5 × 10). Die zweiten Koordinaten sind (0,05, 4,5 × 10). Die dritten Koordinaten sind (0,22, 1,2 × 10). Die vierten Koordinaten sind (0,22, 1,3 × 10). Nach der Bildung der Siliziumkarbidschicht beträgt ein Durchschnittswert der Trägerkonzentration der Siliziumkarbidschicht mehr als oder gleich 1 × 10cmund weniger als oder gleich 2×10cm.

10. 发明专利

CA2797024A1 SILICON CARBIDE SEMICONDUCTOR DEVICE 未知
公开(公告)号：CA2797024A1
公开(公告)日：2012-10-11
申请号：CA2797024
申请日：2012-01-27
申请人： SUMITOMO ELECTRIC INDUSTRIES
发明人： MASUDA TAKEYOSHI , HIYOSHI TORU , WADA KEIJI
IPC分类号： H01L29/12 , H01L21/3065 , H01L21/336 , H01L29/78
摘要： A silicon carbide layer is epitaxially formed on a principal surface of a substrate (1). A groove having a side wall (6) that is inclined with respect to the principal surface is furnished in the silicon carbide layer. The side wall (6) has an off angle of 50º-65º with respect to the {0001} plane. A gate insulating film (8) is furnished over the side wall (6) of the silicon carbide layer. The silicon carbide layer includes a body region (3) facing a gate electrode (9) with the gate insulating film (8) therebetween, and having a first conduction type; and a pair of regions (2, 4) separated from one another by the body region (3), and having a second conduction type. The body region (3) has an impurity density of 5 × 1016cm-3 or greater. The degree of freedom in setting the threshold voltage can thereby be increased, while decline of channel mobility is minimized.

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