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1. 发明授权

US06356270B2 Efficient utilization of write-combining buffers 失效
标题翻译：高效利用写入组合缓冲区
公开(公告)号：US06356270B2
公开(公告)日：2002-03-12
申请号：US09053231
申请日：1998-03-31
申请人： Vladimir Pentkovski , Hsien-Cheng E. Hsieh , Hsien-Hsin Lee , Subramaniam Maiyuran
发明人： Vladimir Pentkovski , Hsien-Cheng E. Hsieh , Hsien-Hsin Lee , Subramaniam Maiyuran
IPC分类号： G06T160
CPC分类号： G06F9/30043 , G06F9/3824 , G06F12/0875
摘要： The present invention discloses a method and apparatus method for efficient utilization of write-combining buffers for a sequence of non-temporal stores to scattered locations. The method comprises: converting the sequence of non-temporal stores to stores to intermediate buffers; and grouping the stores to intermediate buffers into consecutive non-temporal stores. The consecutive non-temporal stores correspond to adjacent memory locations in the write-combining buffers.
摘要翻译：本发明公开了一种用于对分散位置的非时间存储序列的写合成缓冲器有效利用的方法和装置方法。该方法包括：将非时间存储序列转换为存储到中间缓冲器; 并将商店分组到中间缓冲器到连续的非时间商店。连续的非时间存储对应于写合成缓冲器中的相邻存储器位置。

2. 发明授权

US06223276B1 Pipelined processing of short data streams using data prefetching 失效
标题翻译：使用数据预取流水线处理短数据流
公开(公告)号：US06223276B1
公开(公告)日：2001-04-24
申请号：US09053376
申请日：1998-03-31
申请人： Hsien-Hsin Lee , Vladimir Pentkovski , Hsien-Cheng E. Hsieh
发明人： Hsien-Hsin Lee , Vladimir Pentkovski , Hsien-Cheng E. Hsieh
IPC分类号： G06F930
CPC分类号： G06F9/3875 , G06F9/383
摘要： The present invention discloses a method and apparatus for processing strips of data, each strip referencing a plurality of parameter sets stored in a memory. The method comprises: prefetching a plurality of parameter sets referenced in a first strip; performing an operation on each of the prefetched parameter sets; and concatenating a first strip and a second strip to eliminate a memory access latency in the second strip.
摘要翻译：本发明公开了一种用于处理数据条带的方法和装置，每个条带参考存储在存储器中的多个参数集。该方法包括：预取在第一条带中引用的多个参数集; 对每个预取参数集执行操作; 并且连接第一条带和第二条带以消除第二条带中的存储器访问等待时间。

3. 发明授权

US06369813B2 Processing polygon meshes using mesh pool window 失效
标题翻译：使用网格池窗口处理多边形网格
公开(公告)号：US06369813B2
公开(公告)日：2002-04-09
申请号：US09109257
申请日：1998-06-30
申请人： Vladimir Pentkovski , Deep Buch , Michael K. Dwyer , Hsien-Hsin Lee , Hsien-Cheng E. Hsieh
发明人： Vladimir Pentkovski , Deep Buch , Michael K. Dwyer , Hsien-Hsin Lee , Hsien-Cheng E. Hsieh
IPC分类号： G06T1500
CPC分类号： G06T17/20
摘要： The present invention is directed to a method and apparatus for processing normalized meshes. The normalized meshes are formed by N polygons which have M vertices. M vertex coordinates are stored in a vertex array corresponding to the M vertices of the N polygons. N polygon indices are stored in an index array. Each of the N polygon indices references a predetermined number of the M vertex coordinates. A first subset of the index array having N1 polygon indices is determined. A second subset of the vertex array is selected such that the second subset contains M1 vertex coordinates corresponding entirely to the N1 polygon indices in the first subset. The second subset defines a window having a small size relative to the vertex array. The M1 vertex coordinates in the second subset are processed to generate processed data. The processed data are then concurrently sent to a graphics processor in an on-line manner.
摘要翻译：本发明涉及一种用于处理归一化网格的方法和装置。归一化网格由具有M个顶点的N个多边形形成。 M顶点坐标存储在与N个多边形的M个顶点对应的顶点数组中。 N个多边形索引存储在索引数组中。 N个多边形索引中的每一个引用预定数量的M个顶点坐标。确定具有N1个多边形索引的索引阵列的第一子集。选择顶点阵列的第二子集，使得第二子集包含完全对应于第一子集中的N1多边形索引的M1顶点坐标。第二个子集定义相对于顶点数组具有小尺寸的窗口。处理第二个子集中的M1顶点坐标以产生处理后的数据。然后，处理的数据以在线方式同时发送到图形处理器。

4. 发明授权

US06643745B1 Method and apparatus for prefetching data into cache 失效
标题翻译：将数据预取到高速缓存中的方法和装置
公开(公告)号：US06643745B1
公开(公告)日：2003-11-04
申请号：US09053383
申请日：1998-03-31
申请人： Salvador Palanca , Niranjan L. Cooray , Angad Narang , Vladimir Pentkovski , Steve Tsai , Subramaniam Maiyuran , Jagannath Keshava , Hsien-Hsin Lee , Steve Spangler , Suresh Kuttuva , Praveen Mosur
发明人： Salvador Palanca , Niranjan L. Cooray , Angad Narang , Vladimir Pentkovski , Steve Tsai , Subramaniam Maiyuran , Jagannath Keshava , Hsien-Hsin Lee , Steve Spangler , Suresh Kuttuva , Praveen Mosur
IPC分类号： G06F1200
CPC分类号： G06F9/383 , G06F9/3842 , G06F12/0862 , G06F12/0897 , G06F2212/6028
摘要： A computer system is disclosed. The computer system includes a higher level cache, a lower level cache, a decoder to decode instructions, and a circuit coupled to the decoder. In one embodiment, the circuit, in response to a single decoded instruction, retrieves data from external memory and bypasses the lower level cache upon a higher level cache miss. In another embodiment, the circuit, in response to a first decoded instruction, issues a request to retrieve data at an address from external memory to place said data only in the lower level cache, detects a second cacheable decoded instruction to said address, and places said data in the higher level cache.
摘要翻译：公开了一种计算机系统。计算机系统包括较高级别的缓存，较低级别的缓存，解码指令的解码器以及耦合到解码器的电路。在一个实施例中，电路响应于单个解码的指令，在较高级别的高速缓存未命中时从外部存储器检索数据并绕过下一级高速缓存。在另一个实施例中，电路响应于第一解码指令发出从外部存储器的地址检索数据的请求，以将所述数据仅放置在较低级别的高速缓存中，检测到所述地址的第二可缓存解码指令，表示高级缓存中的数据。

5. 发明授权

US06978357B1 Method and apparatus for performing cache segment flush and cache segment invalidation operations 失效
标题翻译：用于执行高速缓存段刷新和缓存段无效操作的方法和装置
公开(公告)号：US06978357B1
公开(公告)日：2005-12-20
申请号：US09122349
申请日：1998-07-24
申请人： Lance Hacking , Shreekant Thakkar , Thomas Huff , Vladimir Pentkovski , Hsien-Cheng E. Hsieh
发明人： Lance Hacking , Shreekant Thakkar , Thomas Huff , Vladimir Pentkovski , Hsien-Cheng E. Hsieh
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/0804
摘要： A method and apparatus for including in a computer system, instructions for performing cache memory invalidate and cache memory flush operations. In one embodiment, the computer system comprises a cache memory having a plurality of cache lines each of which stores data, and a storage area to store a data operand. An execution unit is coupled to the storage area, and operates on data elements in the data operand to invalidate data in a predetermined portion of the plurality of cache lines in response to receiving a single instruction.
摘要翻译：一种用于在计算机系统中包括用于执行高速缓存存储器无效的指令和高速缓存存储器刷新操作的方法和装置。在一个实施例中，计算机系统包括具有存储数据的多个高速缓存行和存储数据操作数的存储区域的高速缓冲存储器。执行单元耦合到存储区域，并且响应于接收到单个指令，对数据操作数中的数据元素进行操作以使多个高速缓存行的预定部分中的数据无效。

6. 发明授权

US5995122A Method and apparatus for parallel conversion of color values from a single precision floating point format to an integer format 失效
标题翻译：将颜色值从单精度浮点格式并行转换为整数格式的方法和装置
公开(公告)号：US5995122A
公开(公告)日：1999-11-30
申请号：US71468
申请日：1998-04-30
申请人： Hsien-Cheng E. Hsieh , Thomas R. Huff , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
发明人： Hsien-Cheng E. Hsieh , Thomas R. Huff , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
IPC分类号： H03M7/24 , G06F13/00 , G06F15/80
CPC分类号： H03M7/24
摘要： A method and apparatus for parallel processing of graphics data are described. A number of color components are stored in a floating point format in at least one register of a set of 128-bit registers in a packed format. The color components in the floating point format are converted to numbers in an integer format. The numbers in the integer format are placed in at least one register of a set of 64-bit registers in the packed format. Color components are assembled for image pixels from the numbers in the integer format.
摘要翻译：描述用于并行处理图形数据的方法和装置。多个颜色分量以压缩格式在一组128位寄存器的至少一个寄存器中以浮点格式存储。浮点格式的颜色分量将以整数格式转换为数字。整数格式的数字以打包格式放置在一组64位寄存器的至少一个寄存器中。从整数格式的数字组装图像像素的颜色分量。

7. 发明授权

US06266769B1 Conversion between packed floating point data and packed 32-bit integer data in different architectural registers 失效
公开(公告)号：US06266769B1
公开(公告)日：2001-07-24
申请号：US09070891
申请日：1998-04-30
申请人： Mohammad A. F. Abdallah , Hsien-Cheng E. Hsieh , Thomas R. Huff , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
发明人： Mohammad A. F. Abdallah , Hsien-Cheng E. Hsieh , Thomas R. Huff , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
IPC分类号： G06F900
CPC分类号： H03M7/24
摘要： A method and instruction for converting a number between a floating point format and an integer format are described. Numbers are stored in the integer format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the integer format is converted to at least one number in the floating point format. The numbers in the floating point format are placed in a register of a second set of architectural registers in a packed format.

8. 发明授权

US06292815B1 Data conversion between floating point packed format and integer scalar format 失效
标题翻译：浮点打包格式与整数标量格式之间的数据转换
公开(公告)号：US06292815B1
公开(公告)日：2001-09-18
申请号：US09069796
申请日：1998-04-30
申请人： Mohammad A. F. Abdallah , Hsien-Cheng E. Hsieh , Thomas R. Huff , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
发明人： Mohammad A. F. Abdallah , Hsien-Cheng E. Hsieh , Thomas R. Huff , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
IPC分类号： G06F9302
CPC分类号： G06T1/20 , H03M7/24
摘要： A method and instruction for converting a number between a floating point format and an integer format are described. Numbers are stored in the integer format in a register of a first set of architectural registers in a scalar format. At least one of the numbers in the scalar format is converted to a number in the floating point format. The number in the floating point format is placed in a register of a second set of architectural registers in a packed format.
摘要翻译：描述用于在浮点格式和整数格式之间转换数字的方法和指令。数字以整数格式存储在标量格式的第一组架构寄存器的寄存器中。标量格式中的至少一个数字将以浮点格式转换为数字。浮点格式的数字以打包格式放置在第二组结构寄存器的寄存器中。

9. 发明授权

US06247116B1 Conversion from packed floating point data to packed 16-bit integer data in different architectural registers 失效
标题翻译：从打包浮点数据转换为不同体系结构寄存器中的16位整数数据
公开(公告)号：US06247116B1
公开(公告)日：2001-06-12
申请号：US09071001
申请日：1998-04-30
申请人： Mohammad A. F. Abdallah , Hsien-Cheng E. Hsieh , Thomas R. Huff , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
发明人： Mohammad A. F. Abdallah , Hsien-Cheng E. Hsieh , Thomas R. Huff , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
IPC分类号： G06F0900
CPC分类号： G06F9/3013 , G06F9/30025 , G06F9/30036 , G06F9/30109
摘要： A method and instruction for converting a number from a floating point format to an integer format are described. Numbers are stored in the floating point format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the floating point format is converted to at least one 16-bit number in the integer format. The 16-bit number in the integer format is placed in a register of a second set of architectural registers in the packed format.
摘要翻译：描述用于将数字从浮点格式转换为整数格式的方法和指令。数字以浮点格式存储在打包格式的第一组结构寄存器的寄存器中。浮点格式中的至少一个数字将以整数格式转换为至少一个16位数。整数格式的16位数字以打包格式放置在第二组体系结构寄存器的寄存器中。

10. 发明授权

US06502115B2 Conversion between packed floating point data and packed 32-bit integer data in different architectural registers 有权
标题翻译：在不同体系结构寄存器中的打包浮点数据和打包的32位整数数据之间进行转换
公开(公告)号：US06502115B2
公开(公告)日：2002-12-31
申请号：US09845610
申请日：2001-04-27
申请人： Mohammad A. F. Abdallah , Hsien-Cheng E. Hsieh , Thomas R. Huff , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
发明人： Mohammad A. F. Abdallah , Hsien-Cheng E. Hsieh , Thomas R. Huff , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
IPC分类号： G06F700
CPC分类号： H03M7/24
摘要： A method and instruction for converting a number between a floating point format and an integer format are described. Numbers are stored in the integer format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the integer format is converted to at least one number in the floating point format. The numbers in the floating point format are placed in a register of a second set of architectural registers in a packed format.
摘要翻译：描述用于在浮点格式和整数格式之间转换数字的方法和指令。数字以整数格式存储在打包格式的第一组架构寄存器的寄存器中。整数格式中的至少一个数字将以浮点格式转换为至少一个数字。浮点格式的数字以打包格式放置在第二组结构寄存器的寄存器中。

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