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1. 发明申请

US20060076597A1 Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers 审中-公开
公开(公告)号：US20060076597A1
公开(公告)日：2006-04-13
申请号：US11235866
申请日：2005-09-26
申请人： Vishnu Agarwal , Garo Derderian , Gurtej Sandhu , Weimin Li , Mark Visokay , Cem Basceri , Sam Yang
发明人： Vishnu Agarwal , Garo Derderian , Gurtej Sandhu , Weimin Li , Mark Visokay , Cem Basceri , Sam Yang
IPC分类号： H01L29/94
CPC分类号： H01L28/84 , H01L21/02183 , H01L21/02197 , H01L21/31637 , H01L28/55 , H01L28/65
摘要： Capacitors having increased capacitance include an enhanced-surface-area (rough-surfaced) electrically conductive layer or other layers that are compatible with the high-dielectric constant materials. In one approach, an enhanced-surface-area electrically conductive layer for such capacitors is formed by processing a ruthenium oxide layer at high temperature at or above 500° C. and low pressure 75 torr or below, most desirably 5 torr or below, to produce a roughened ruthenium layer having a textured surface with a mean feature size of at least about 100 Angstroms. The initial ruthenium oxide layer may be provided by chemical vapor deposition techniques or sputtering techniques or the like. The layer may be formed over an underlying electrically conductive layer. The processing may be performed in an inert ambient or in a reducing ambient. A nitrogen-supplying ambient or nitrogen-supplying reducing ambient may be used during the processing or afterwards to passivate the ruthenium for improved compatibility with high-dielectric-constant dielectric materials. Processing in an oxidizing ambient may also be performed to passivate the roughened layer. The roughened layer of ruthenium may be used to form an enhanced-surface-area electrically conductive layer. The resulting enhanced-surface-area electrically conductive layer may form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like. In another approach, a tungsten nitride layer is provided as an first electrode of such a capacitor. The capacitor, or at least the tungsten nitride layer, is annealed to increase the capacitance of the capacitor.

2. 发明申请

US20050048792A1 Atomic layer deposition apparatus 审中-公开
标题翻译：原子层沉积装置
公开(公告)号：US20050048792A1
公开(公告)日：2005-03-03
申请号：US10954845
申请日：2004-09-29
申请人： Garo Derderian , Cem Basceri , Gurtej Sandhu , Demetrius Sarigiannis
发明人： Garo Derderian , Cem Basceri , Gurtej Sandhu , Demetrius Sarigiannis
IPC分类号： C30B25/00 , C30B35/00 , H01L21/31
CPC分类号： C30B35/00 , C30B25/00 , C30B29/68
摘要： An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A fixed volume first precursor gas charge is provided within a gas flow path to the deposition chamber. A fixed volume purge gas charge is provided within the gas flow path serially upstream of the first precursor gas charge. The first precursor gas charge and the purge gas charge are serially flowed along the gas flow path to the substrate within the deposition chamber effective to form a monolayer on the substrate and purge at least some of the first precursor gas from the substrate. Apparatus are also disclosed.
摘要翻译：原子层沉积方法包括将半导体衬底定位在原子层沉积室内。在到达沉积室的气体流动路径内提供固定体积的第一前体气体进料。在第一前体气体装料的串联的气体流动路径内提供固定体积的吹扫气体装料。第一前体气体装料和吹扫气体装料沿着气体流动路径顺序地流动到沉积室内的基板，有效地在基板上形成单层，并且从基板清除至少一些第一前体气体。还公开了装置。

3. 发明申请

US20050039674A1 Atomic layer deposition method 失效
标题翻译：原子层沉积法
公开(公告)号：US20050039674A1
公开(公告)日：2005-02-24
申请号：US10956925
申请日：2004-09-30
申请人： Paul Castovillo , Cem Basceri , Garo Derderian , Gurtej Sandhu
发明人： Paul Castovillo , Cem Basceri , Garo Derderian , Gurtej Sandhu
IPC分类号： C23C16/34 , C23C14/06 , C23C14/08 , C23C16/40 , C23C16/44 , C23C16/455 , C30B25/14 , H01L21/285 , H01L21/316 , H01L21/768 , C30B23/00 , C30B25/00 , C30B28/12 , C30B28/14 , H01L21/8238
CPC分类号： C30B25/14 , C23C14/0641 , C23C14/081 , C23C16/34 , C23C16/403 , C23C16/45527 , C23C16/45531
摘要： An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A first precursor gas is flowed to the substrate within the atomic layer deposition chamber effective to form a first monolayer on the substrate. After forming the first monolayer, a reactive intermediate gas is flowed to the substrate within the deposition chamber. The reactive intermediate gas is capable of reaction with an intermediate reaction by-product from the first precursor flowing under conditions of the reactive intermediate gas flowing. After flowing the reactive intermediate gas, a second precursor gas is flowed to the substrate within the deposition chamber effective to form a second monolayer on the first monolayer. Other aspects and implementations are contemplated.
摘要翻译：原子层沉积方法包括将半导体衬底定位在原子层沉积室内。第一前体气体流到原子层沉积室内的衬底，有效地在衬底上形成第一单层。在形成第一单层之后，反应性中间气体流到沉积室内的衬底。反应性中间体气体能够与在反应性中间体气体流动的条件下流动的第一前体的中间反应副产物反应。在流动反应性中间气体之后，第二前体气体流到沉积室内的衬底，有效地在第一单层上形成第二单层。考虑了其他方面和实现。

4. 发明申请

US20050147751A1 Deposition methods 失效
公开(公告)号：US20050147751A1
公开(公告)日：2005-07-07
申请号：US11075017
申请日：2005-03-08
申请人： Demetrius Sarigiannis , Garo Derderian , Cem Basceri , Gurtej Sandhu , F. Gealy , Chris Carlson
发明人： Demetrius Sarigiannis , Garo Derderian , Cem Basceri , Gurtej Sandhu , F. Gealy , Chris Carlson
IPC分类号： C23C16/44 , C23C16/455 , C23C14/00 , C23C16/00
CPC分类号： C23C16/45519 , C23C16/4401 , C23C16/455
摘要： A deposition method includes positioning a substrate within a deposition chamber defined at least in part by chamber walls. At least one of the chamber walls comprises a chamber surface having a plurality of purge gas inlets to the chamber therein. A process gas is provided over the substrate effective to deposit a layer onto the substrate. During such providing, a material adheres to the chamber surface. Reactive purge gas is emitted to the deposition chamber from the purge gas inlets effective to form a reactive gas curtain over the chamber surface and away from the substrate, with such reactive gas reacting with such adhering material. Further implementations are contemplated.

5. 发明申请

US20060205228A1 Atomic layer deposition methods 有权
标题翻译：原子层沉积法
公开(公告)号：US20060205228A1
公开(公告)日：2006-09-14
申请号：US11414407
申请日：2006-04-28
申请人： Demetrius Sarigiannis , Garo Derderian , Cem Basceri , Gurtej Sandhu , F. Gealy , Chris Carlson
发明人： Demetrius Sarigiannis , Garo Derderian , Cem Basceri , Gurtej Sandhu , F. Gealy , Chris Carlson
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/32051 , C23C16/4404 , C23C16/4405 , C23C16/45531 , C23C16/45534 , H01L21/02178 , H01L21/02186 , H01L21/0228 , H01L21/28562 , H01L21/3141 , H01L21/31616
摘要： The invention includes an atomic layer deposition method of forming a layer of a deposited composition on a substrate. The method includes positioning a semiconductor substrate within an atomic layer deposition chamber. On the substrate, an intermediate composition monolayer is formed, followed by a desired deposited composition from reaction with the intermediate composition, collectively from flowing multiple different composition deposition precursors to the substrate within the deposition chamber. A material adheres to a chamber internal component surface from such sequentially forming. After such sequentially forming, a reactive gas flows to the chamber which is different in composition from the multiple different deposition precursors and which is effective to react with such adhering material. After the reactive gas flowing, such sequentially forming is repeated. Further implementations are contemplated.
摘要翻译：本发明包括在基板上形成沉积的组合物层的原子层沉积方法。该方法包括将半导体衬底定位在原子层沉积室内。在基材上形成中间组合物单层，随后是与中间体组合物反应所需的沉积组合物，统称为将多种不同的组合物沉积前体流到沉积室内的基底。材料粘附到室内部件表面，从而依次形成。在这种顺序形成之后，反应性气体流入到与多种不同的沉积前体不同的组合物中，并有效地与这种粘附材料反应。在反应气体流动之后，重复这种顺序形成。考虑进一步的实现。

6. 发明申请

US20060205227A1 Atomic layer deposition methods 有权
公开(公告)号：US20060205227A1
公开(公告)日：2006-09-14
申请号：US11413438
申请日：2006-04-28
申请人： Demetrius Sarigiannis , Garo Derderian , Cem Basceri , Gurtej Sandhu , F. Gealy , Chris Carlson
发明人： Demetrius Sarigiannis , Garo Derderian , Cem Basceri , Gurtej Sandhu , F. Gealy , Chris Carlson
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/32051 , C23C16/4404 , C23C16/4405 , C23C16/45531 , C23C16/45534 , H01L21/02178 , H01L21/02186 , H01L21/0228 , H01L21/28562 , H01L21/3141 , H01L21/31616
摘要： The invention includes an atomic layer deposition method of forming a layer of a deposited composition on a substrate. The method includes positioning a semiconductor substrate within an atomic layer deposition chamber. On the substrate, an intermediate composition monolayer is formed, followed by a desired deposited composition from reaction with the intermediate composition, collectively from flowing multiple different composition deposition precursors to the substrate within the deposition chamber. A material adheres to a chamber internal component surface from such sequentially forming. After such sequentially forming, a reactive gas flows to the chamber which is different in composition from the multiple different deposition precursors and which is effective to react with such adhering material. After the reactive gas flowing, such sequentially forming is repeated. Further implementations are contemplated.

7. 发明授权

US06940112B2 Integrated capacitors fabricated with conductive metal oxides 失效
标题翻译：用导电金属氧化物制成的集成电容器
公开(公告)号：US06940112B2
公开(公告)日：2005-09-06
申请号：US10234351
申请日：2002-08-30
申请人： Howard E. Rhodes , Mark Visokay , Tom Graettinger , Dan Gealy , Gurtej Sandhu , Cem Basceri , Steve Cummings
发明人： Howard E. Rhodes , Mark Visokay , Tom Graettinger , Dan Gealy , Gurtej Sandhu , Cem Basceri , Steve Cummings
IPC分类号： C23C16/40 , H01L21/02 , H01L21/76
CPC分类号： H01L28/60 , C23C16/40 , H01L28/55 , H01L28/90
摘要： A capacitor for a memory device is formed with a conductive oxide for a bottom electrode. The conductive oxide (RuOx) is deposited under low temperatures as an amorphous film. As a result, the film is conformally deposited over a three dimensional, folding structure. Furthermore, a subsequent polishing step is easily performed on the amorphous film, increasing wafer throughput. After deposition and polishing, the film is crystallized in a non-oxidizing ambient.
摘要翻译：用于存储器件的电容器形成有用于底部电极的导电氧化物。导电氧化物（RuO x S）在低温下作为非晶膜沉积。结果，膜被共形沉积在三维折叠结构上。此外，随后的研磨步骤容易地在非晶膜上进行，提高了晶片生产量。沉积和抛光后，膜在非氧化环境中结晶。

8. 发明授权

US06869877B2 Integrated capacitors fabricated with conductive metal oxides 失效
标题翻译：用导电金属氧化物制成的集成电容器
公开(公告)号：US06869877B2
公开(公告)日：2005-03-22
申请号：US10234581
申请日：2002-08-30
申请人： Howard E. Rhodes , Mark Visokay , Tom Graettinger , Dan Gealy , Gurtej Sandhu , Cem Basceri , Steve Cummings
发明人： Howard E. Rhodes , Mark Visokay , Tom Graettinger , Dan Gealy , Gurtej Sandhu , Cem Basceri , Steve Cummings
IPC分类号： C23C16/40 , H01L21/02 , H01L21/44
CPC分类号： H01L28/60 , C23C16/40 , H01L28/55 , H01L28/90
摘要： A capacitor for a memory device is formed with a conductive oxide for a bottom electrode. The conductive oxide (RuOx) is deposited under low temperatures as an amorphous film. As a result, the film is conformally deposited over a three dimensional, folding structure. Furthermore, a subsequent polishing step is easily performed on the amorphous film, increasing wafer throughput. After deposition and polishing, the film is crystallized in a non-oxidizing ambient.
摘要翻译：用于存储器件的电容器形成有用于底部电极的导电氧化物。导电氧化物（RuOx）在低温下作为非晶膜沉积。结果，膜被共形沉积在三维折叠结构上。此外，随后的研磨步骤容易地在非晶膜上进行，提高了晶片生产量。沉积和抛光后，膜在非氧化环境中结晶。

9. 发明授权

US06492241B1 Integrated capacitors fabricated with conductive metal oxides 有权
标题翻译：用导电金属氧化物制成的集成电容器
公开(公告)号：US06492241B1
公开(公告)日：2002-12-10
申请号：US09546492
申请日：2000-04-10
申请人： Howard E. Rhodes , Mark Visokay , Tom Graettinger , Dan Gealy , Gurtej Sandhu , Cem Basceri , Steve Cummings
发明人： Howard E. Rhodes , Mark Visokay , Tom Graettinger , Dan Gealy , Gurtej Sandhu , Cem Basceri , Steve Cummings
IPC分类号： H01L2972
CPC分类号： H01L28/60 , C23C16/40 , H01L28/55 , H01L28/90
摘要： A capacitor for a memory device is formed with a conductive oxide for a bottom electrode. The conductive oxide (RuOx) is deposited under low temperatures as an amorphous film. As a result, the film is conformally deposited over a three dimensional, folding structure. Furthermore, a subsequent polishing step is easily performed on the amorphous film, increasing wafer throughput. After deposition and polishing, the film is crystallized in a non-oxidizing ambient.
摘要翻译：用于存储器件的电容器形成有用于底部电极的导电氧化物。导电氧化物（RuOx）在低温下作为非晶膜沉积。结果，膜被共形沉积在三维折叠结构上。此外，随后的研磨步骤容易地在非晶膜上进行，提高了晶片生产量。沉积和抛光后，膜在非氧化环境中结晶。

10. 发明申请

US20060154382A1 Capacitor with high dielectric constant materials and method of making 审中-公开
标题翻译：具有高介电常数材料和制作方法的电容器
公开(公告)号：US20060154382A1
公开(公告)日：2006-07-13
申请号：US11346676
申请日：2006-02-03
申请人： Cem Basceri , Gurtej Sandhu , Mark Visokay
发明人： Cem Basceri , Gurtej Sandhu , Mark Visokay
IPC分类号： H01L21/00 , H01L21/20
CPC分类号： H01L28/56 , H01L27/10811
摘要： Stabilized capacitors and DRAM cells using high dielectric constant oxide dielectric materials such as Ta2O5 and BaxSr(1-x)TiO3, and methods of making such capacitors and DRAM cells are provided. One method includes providing a conductive oxide electrode, oxidizing at least the upper surface of the conductive oxide electrode, depositing a first layer of a high dielectric constant oxide dielectric material on the conductive oxide electrode, oxidizing the first layer of the high dielectric constant oxide dielectric material under oxidizing conditions, depositing a second layer of the high dielectric constant oxide dielectric material on the first layer of the dielectric, and depositing an upper layer electrode on the second layer of the high dielectric constant oxide dielectric material.
摘要翻译：使用高介电常数氧化物介电材料如Ta 2 O 5和Ba x Sr（1-x）的稳定电容器和DRAM单元）和提供制造这种电容器和DRAM单元的方法。一种方法包括提供导电氧化物电极，至少氧化导电氧化物电极的上表面，在导电氧化物电极上沉积高介电常数氧化物电介质材料的第一层，氧化高介电常数氧化物电介质的第一层在氧化条件下的材料，在所述电介质的第一层上沉积高介电常数氧化物介电材料的第二层，以及在所述高介电常数氧化物介电材料的第二层上沉积上层电极。

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