专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08930670B2 Partition redispatching using page tracking 有权
标题翻译：使用页面跟踪进行分区重新分配
公开(公告)号：US08930670B2
公开(公告)日：2015-01-06
申请号：US11936456
申请日：2007-11-07
申请人： Vaijayanthimala K. Anand , Bret R. Olszewski , Mysore Sathyanarayana Srinivas
发明人： Vaijayanthimala K. Anand , Bret R. Olszewski , Mysore Sathyanarayana Srinivas
IPC分类号： G06F12/06 , G06F12/10
CPC分类号： G06F12/1009 , G06F2212/401
摘要： Illustrated embodiments provide a computer implemented method and data processing system for redispatching a partition by tracking a set of memory pages, belonging to the dispatched partition. In one illustrative embodiment the computer implemented method comprises finding an effective page address to real page address mapping for a page address miss in response to determining the page address miss in a page addressing buffer, and saving the mapping as an entry in an array. The computer implemented method creates a preserved array from the array in response to determining the dispatched partition to be an undispatched partition. The computer implemented method further analyzes of the preserved array for a compressed page in response to determining the undispatched partition is now redispatched, and decompresses the compressed page prior to the partition being redispatched.
摘要翻译：说明的实施例提供了一种计算机实现的方法和数据处理系统，用于通过跟踪属于所分派的分区的一组存储器页来重新分配分区。在一个说明性实施例中，计算机实现的方法包括响应于确定页寻址缓冲器中的页面地址未命中而找到页面地址未命中的实际页面地址映射的有效页面地址，并将映射保存为阵列中的条目。计算机实现的方法从数组中创建一个保留的数组，以响应将分派的分区确定为未分配的分区。计算机实现的方法进一步分析压缩页面的保留数组，以响应确定未分配的分区现在被重新分配，并在重新分配分区之前解压缩压缩页面。

2. 发明申请

US20090119474A1 PARTITION REDISPATCHING USING PAGE TRACKING 有权
标题翻译：使用页面跟踪进行分区重新分类
公开(公告)号：US20090119474A1
公开(公告)日：2009-05-07
申请号：US11936456
申请日：2007-11-07
申请人： Vaijayanthimala K. Anand , Bret R. Olszewski , Mysore Sathyanarayana Srinivas
发明人： Vaijayanthimala K. Anand , Bret R. Olszewski , Mysore Sathyanarayana Srinivas
IPC分类号： G06F13/00
CPC分类号： G06F12/1009 , G06F2212/401
摘要： Illustrated embodiments provide a computer implemented method and data processing system for redispatching a partition by tracking a set of memory pages, belonging to the dispatched partition. In one illustrative embodiment the computer implemented method comprises finding an effective page address to real page address mapping for a page address miss to create a found real page address and page size combination, responsive to determining the page address miss in a page addressing buffer, and saving the found real page address and page size combination as an entry in set of entries in an array. Further in the computer implemented method, creating a preserved array from the array, responsive to determining the dispatched partition to be an undispatched partition. The computer implemented method further, analyzing each entry of the preserved array for a compressed page, responsive to determining the undispatched partition is now redispatched, and invoking a partition management firmware function to decompress the compressed page, prior to the partition being redispatched, responsive to determining a compressed page.
摘要翻译：说明的实施例提供了一种计算机实现的方法和数据处理系统，用于通过跟踪属于所分派的分区的一组存储器页来重新分配分区。在一个说明性实施例中，计算机实现的方法包括：响应于确定页面寻址缓冲器中的页面地址未命中，找到用于寻址页面地址的真实页面地址映射以产生找到的真实页面地址和页面大小组合的有效页面地址，以及将发现的真实页面地址和页面大小组合保存为数组中的条目集中的条目。此外，在计算机实现的方法中，响应于将分派的分区确定为未分配的分区，从阵列创建保留的数组。计算机实现的方法还包括：响应于确定未分配的分区现在被重新分配，分析压缩页面的保留数组的每个条目，并且在重新分配分区之前调用分区管理固件功能来解压缩压缩页面，响应于确定压缩页面。

3. 发明授权

US08392659B2 Extending cache capacity on multiple-core processor systems 有权
标题翻译：在多核处理器系统上扩展缓存容量
公开(公告)号：US08392659B2
公开(公告)日：2013-03-05
申请号：US12612767
申请日：2009-11-05
申请人： Vaijayanthimala K. Anand , Diane Garza Flemming , William A. Maron , Mysore Sathyanarayana Srinivas
发明人： Vaijayanthimala K. Anand , Diane Garza Flemming , William A. Maron , Mysore Sathyanarayana Srinivas
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F2212/601
摘要： A method, programmed medium and system are provided for enabling a core's cache capacity to be increased by using the caches of the disabled or non-enabled cores on the same chip. Caches of disabled or non-enabled cores on a chip are made accessible to store cachelines for those chip cores that have been enabled, thereby extending cache capacity of enabled cores.
摘要翻译：提供了一种编程介质和系统，用于通过使用同一芯片上的禁用或非使能内核的高速缓存来实现内核的高速缓存容量的增加。对芯片上的禁用或非启用内核的缓存进行访问，以存储已启用的那些芯片内核的高速缓存线，从而扩展启用核心的高速缓存容量。

4. 发明申请

US20110107031A1 Extended Cache Capacity 有权
标题翻译：扩展缓存容量
公开(公告)号：US20110107031A1
公开(公告)日：2011-05-05
申请号：US12612767
申请日：2009-11-05
申请人： Vaijayanthimala K. Anand , Diane Garza Flemming , William A. Maron , Mysore Sathyanarayana Srinivas
发明人： Vaijayanthimala K. Anand , Diane Garza Flemming , William A. Maron , Mysore Sathyanarayana Srinivas
IPC分类号： G06F12/08 , G06F12/00 , G06F9/44
CPC分类号： G06F12/084 , G06F2212/601
摘要： A method, programmed medium and system are provided for enabling a core's cache capacity to be increased by using the caches of the disabled or non-enabled cores on the same chip. Caches of disabled or non-enabled cores on a chip are made accessible to store cachelines for those chip cores that have been enabled, thereby extending cache capacity of enabled cores.
摘要翻译：提供了一种编程介质和系统，用于通过使用同一芯片上的禁用或非使能内核的高速缓存来实现内核的高速缓存容量的增加。对芯片上的禁用或非启用内核的缓存进行访问，以存储已启用的那些芯片内核的高速缓存线，从而扩展启用核心的高速缓存容量。

5. 发明申请

US20090182893A1 CACHE COHERENCE IN A VIRTUAL MACHINE MANAGED SYSTEM 审中-公开
标题翻译：虚拟机管理系统中的高速缓存
公开(公告)号：US20090182893A1
公开(公告)日：2009-07-16
申请号：US11972788
申请日：2008-01-11
申请人： Vaijayanthimala K. Anand , Bret Ronald Olszewski , Mysore Sathyanarayana Srinivas
发明人： Vaijayanthimala K. Anand , Bret Ronald Olszewski , Mysore Sathyanarayana Srinivas
IPC分类号： G06F15/173
CPC分类号： G06F15/16 , G06F12/0831
摘要： A method, a system, and computer readable program code for managing cache coherence in a virtual machine managed system are provided. In response to a processor issuing a message to be broadcast, a determination is made as to whether the processor is part of a virtual domain. In response to a determination that the processor is part of the virtual domain, the message and a first bit mask are sent from a source node to a destination node. In response to receiving the message and the first bit mask, one of a primary link or a secondary link is selected to send the message and the first bit mask over, forming a selected link. The message and the first bit mask are sent to the destination node over the selected link.
摘要翻译：提供了一种用于管理虚拟机管理系统中的高速缓存一致性的方法，系统和计算机可读程序代码。响应于处理器发出要广播的消息，确定处理器是否是虚拟域的一部分。响应于处理器是虚拟域的一部分的确定，消息和第一位掩码从源节点发送到目的地节点。响应于接收到所述消息和所述第一位掩码，选择主链路或辅助链路中的一个以发送所述消息和所述第一位掩码，从而形成所选择的链路。消息和第一个位掩码通过所选链接发送到目标节点。

6. 发明授权

US08291430B2 Optimizing system performance using spare cores in a virtualized environment 有权
标题翻译：在虚拟化环境中使用备用内核优化系统性能
公开(公告)号：US08291430B2
公开(公告)日：2012-10-16
申请号：US12500628
申请日：2009-07-10
申请人： Vaijayanthimala K. Anand , Mysore Sathyanarayana Srinivas
发明人： Vaijayanthimala K. Anand , Mysore Sathyanarayana Srinivas
IPC分类号： G06F9/46
CPC分类号： G06F9/45533 , G06F9/5077
摘要： A mechanism for optimizing system performance using spare processing cores in a virtualized environment. When detecting a workload partition needs to run on a virtual processor in the virtualized system, a state of the virtual processor is changed to a wait state. A first node comprising memory that is local to the workload partition is determined. A determination is also made as to whether a non-spare processor core in the first node is available to run the workload partition. If no non-spare processor core is available, a free non-spare processor core in a second node is located, and the state of the free non-spare processor core in the second node is changed to an inactive state. The state of a spare processor core in the first node is changed to an active state, and the workload partition is dispatched to the spare processor core in the first node for execution.
摘要翻译：在虚拟化环境中使用备用处理核心优化系统性能的机制。当检测到工作负载分区需要在虚拟化系统中的虚拟处理器上运行时，虚拟处理器的状态被改变为等待状态。确定包括工作负载分区本地的存储器的第一节点。还确定第一节点中的非备用处理器核心是否可用于运行工作负载分区。如果没有非备用处理器核心可用，则定位第二节点中的空闲非备用处理器核心，并且将第二节点中的空闲非备用处理器核心的状态改变为非活动状态。第一个节点中的备用处理器核心的状态更改为活动状态，并将工作负载分区分派到第一个节点中的备用处理器核心，以执行。

7. 发明申请

US20110010709A1 Optimizing System Performance Using Spare Cores in a Virtualized Environment 有权
标题翻译：在虚拟化环境中使用备用内核优化系统性能
公开(公告)号：US20110010709A1
公开(公告)日：2011-01-13
申请号：US12500628
申请日：2009-07-10
申请人： Vaijayanthimala K. Anand , Mysore Sathyanarayana Srinivas
发明人： Vaijayanthimala K. Anand , Mysore Sathyanarayana Srinivas
IPC分类号： G06F9/44
CPC分类号： G06F9/45533 , G06F9/5077
摘要： A mechanism for optimizing system performance using spare processing cores in a virtualized environment. When detecting a workload partition needs to run on a virtual processor in the virtualized system, a state of the virtual processor is changed to a wait state. A first node comprising memory that is local to the workload partition is determined. A determination is also made as to whether a non-spare processor core in the first node is available to run the workload partition. If no non-spare processor core is available, a free non-spare processor core in a second node is located, and the state of the free non-spare processor core in the second node is changed to an inactive state. The state of a spare processor core in the first node is changed to an active state, and the workload partition is dispatched to the spare processor core in the first node for execution.
摘要翻译：在虚拟化环境中使用备用处理核心优化系统性能的机制。当检测到工作负载分区需要在虚拟化系统中的虚拟处理器上运行时，虚拟处理器的状态被改变为等待状态。确定包括工作负载分区本地的存储器的第一节点。还确定第一节点中的非备用处理器核心是否可用于运行工作负载分区。如果没有非备用处理器核心可用，则定位第二节点中的空闲非备用处理器核心，并且将第二节点中的空闲非备用处理器核心的状态改变为非活动状态。第一个节点中的备用处理器核心的状态更改为活动状态，并将工作负载分区分派到第一个节点中的备用处理器核心，以执行。

8. 发明授权

US08745622B2 Standalone software performance optimizer system for hybrid systems 有权
标题翻译：混合系统的独立软件性能优化系统
公开(公告)号：US08745622B2
公开(公告)日：2014-06-03
申请号：US12427746
申请日：2009-04-22
申请人： Greg R. Mewhinney , Diane Garza Flemming , David B. Whitworth , William A. Maron , Mysore Sathyanarayana Srinivas
发明人： Greg R. Mewhinney , Diane Garza Flemming , David B. Whitworth , William A. Maron , Mysore Sathyanarayana Srinivas
IPC分类号： G06F9/50 , G06F9/48
CPC分类号： G06F9/5033 , G06F9/4843 , G06F9/50 , G06F9/5044
摘要： Standalone software performance optimizer systems for hybrid systems include a hybrid system having a plurality of processors, memory operably connected to the processors, an operating system including a dispatcher loaded into the memory, a multithreaded application read into the memory, and a static performance analysis program loaded into the memory; wherein the static performance analysis program instructs at least one processor to perform static performance analysis on each of the threads, the static performance analysis program instructs at least one processor to assign each thread to a CPU class based on the static performance analysis, and the static performance analysis program instructs at least one processor to store each thread's CPU class. An embodiment of the invention may also include the dispatcher optimally mapping threads to processors using thread CPU classes and remapping threads to processors when a runtime performance analysis classifies a thread differently from the static performance analysis.
摘要翻译：用于混合系统的独立软件性能优化器系统包括具有多个处理器的混合系统，可操作地连接到处理器的存储器，包括加载到存储器中的调度器，读入存储器的多线程应用的操作系统和静态性能分析程序加载到内存中; 其中所述静态性能分析程序指示至少一个处理器对每个所述线程执行静态性能分析，所述静态性能分析程序指示至少一个处理器基于所述静态性能分析将每个线程分配给CPU类，并且所述静态性能分析程序指示至少一个处理器存储每个线程的CPU类。本发明的实施例还可以包括调度器，当运行时性能分析将线程与静态性能分析不同的方式进行分类时，线程CPU类将线程最优地映射到处理器并将线程重新映射到处理器。

9. 发明授权

US08566539B2 Managing thermal condition of a memory 失效
标题翻译：管理记忆的热状况
公开(公告)号：US08566539B2
公开(公告)日：2013-10-22
申请号：US12353343
申请日：2009-01-14
申请人： Diane Garza Flemming , Ghadir Robert Gholami , Octavian Florin Herescu , William A Maron , Mysore Sathyanarayana Srinivas
发明人： Diane Garza Flemming , Ghadir Robert Gholami , Octavian Florin Herescu , William A Maron , Mysore Sathyanarayana Srinivas
IPC分类号： G06F13/00
CPC分类号： G06F12/0802 , G06F1/206 , G06F9/5016 , G06F9/5077 , G06F9/5094 , Y02D10/22
摘要： A method, system, and computer usable program product for managing thermal condition of a memory are provided in the illustrative embodiments. A condition that a threshold value of a thermal condition of the memory has been exceeded or is likely to be exceeded is identified. A portion of a first workload is identified as being a cause of exceeding the threshold. A second portion of a second workload is identified, the second portion not causing the threshold to be exceeded when executed. A set of operations corresponding to the first portion is interleaved with a second set of operations corresponding to the second portion. The interleaved first and second portions of the first and second workloads are executed, causing the thermal condition of the memory to remain below the threshold. The second portion may use a second memory, a second area of the memory, or a combination thereof when executing.
摘要翻译：在说明性实施例中提供了用于管理存储器的热状态的方法，系统和计算机可用程序产品。识别存储器的热条件的阈值已经被超过或可能被超过的条件。第一工作负载的一部分被识别为超出阈值的原因。识别第二工作负载的第二部分，当执行时不引起阈值的第二部分。对应于第一部分的一组操作与对应于第二部分的第二组操作进行交织。执行第一和第二工作负载的交织的第一和第二部分，使得存储器的热状态保持在阈值以下。第二部分可以在执行时使用第二存储器，存储器的第二区域或其组合。

10. 发明授权

US08146087B2 System and method for enabling micro-partitioning in a multi-threaded processor 有权
标题翻译：用于在多线程处理器中实现微分区的系统和方法
公开(公告)号：US08146087B2
公开(公告)日：2012-03-27
申请号：US11972361
申请日：2008-01-10
申请人： Men-Chow Chiang , Sujatha Kashyap , Mysore Sathyanarayana Srinivas
发明人： Men-Chow Chiang , Sujatha Kashyap , Mysore Sathyanarayana Srinivas
IPC分类号： G06F9/46
CPC分类号： G06F12/1036 , G06F9/5061
摘要： A system and method for allowing jobs originating from different partitions to simultaneously utilize different hardware threads on a processor by concatenating partition identifiers with virtual page identifiers within a processor's translation lookaside buffer is presented. The device includes a translation lookaside buffer that translates concatenated virtual addresses to system-wide real addresses. The device generates concatenated virtual addresses using a partition identifier, which corresponds to a job's originating partition, and a virtual page identifier, which corresponds to the executing instruction, such as an instruction address or data address. In turn, each concatenated virtual address is different, which translates in the translation lookaside buffer to a unique system-wide real address. As such, jobs originating from different partitions are able to simultaneously execute on the device and, therefore, fully utilize each of the device's hardware threads.
摘要翻译：提出了一种用于允许源自不同分区的作业同时利用处理器中的不同硬件线程的系统和方法，其通过将分区标识符与处理器的翻译后备缓冲器内的虚拟页面标识符相连接。该设备包括翻译后备缓冲区，将连接的虚拟地址转换为系统范围的实际地址。设备使用对应于作业的始发分区的分区标识符和对应于执行指令（诸如指令地址或数据地址）的虚拟页面标识符来生成级联的虚拟地址。反过来，每个连接的虚拟地址是不同的，这将翻译后备缓冲区转换为唯一的系统范围的实际地址。因此，源自不同分区的作业能够在设备上同时执行，并因此充分利用设备的每个硬件线程。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式