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1. 发明授权

US08438341B2 Common memory programming 有权
标题翻译：常用内存编程
公开(公告)号：US08438341B2
公开(公告)日：2013-05-07
申请号：US12816588
申请日：2010-06-16
申请人： Ulrich A. Finkler , Steven N. Hirsch , Harold E. Reindel
发明人： Ulrich A. Finkler , Steven N. Hirsch , Harold E. Reindel
IPC分类号： G06F12/00
CPC分类号： G06F9/544
摘要： A method for unidirectional communication between tasks includes providing a first task having access to an amount of virtual memory, blocking a communication channel portion of said first task's virtual memory, such that the first task cannot access said portion, providing a second task, having access to an amount of virtual memory equivalent to the first task's virtual memory, wherein a communication channel portion of the second task's virtual memory corresponding to the blocked portion of the first task's virtual memory is marked as writable, transferring the communication channel memory of the second task to the first task, and unblocking the communication channel memory of the first task.
摘要翻译：一种用于任务之间的单向通信的方法包括提供具有对一定量的虚拟存储器的访问的第一任务，阻止所述第一任务的虚拟存储器的通信信道部分，使得第一任务不能访问所述部分，提供第二任务，涉及与第一任务的虚拟存储器相当的虚拟存储器的量，其中与第一任务的虚拟存储器的被阻止部分相对应的第二任务的虚拟存储器的通信信道部分被标记为可写，传送第二任务的通信信道存储器到第一个任务，并解除第一个任务的通信通道存储器。

2. 发明申请

US20110314238A1 COMMON MEMORY PROGRAMMING 有权
标题翻译：通用记忆编程
公开(公告)号：US20110314238A1
公开(公告)日：2011-12-22
申请号：US12816588
申请日：2010-06-16
申请人： Ulrich A. Finkler , Steven N. Hirsch , Harold E. Reindel
发明人： Ulrich A. Finkler , Steven N. Hirsch , Harold E. Reindel
IPC分类号： G06F12/00 , G06F12/10 , G06F12/14 , G06F12/16
CPC分类号： G06F9/544
摘要： A method for unidirectional communication between tasks includes providing a first task having access to an amount of virtual memory, blocking a communication channel portion of said first task's virtual memory, such that the first task cannot access said portion, providing a second task, having access to an amount of virtual memory equivalent to the first task's virtual memory, wherein a communication channel portion of the second task's virtual memory corresponding to the blocked portion of the first task's virtual memory is marked as writable, transferring the communication channel memory of the second task to the first task, and unblocking the communication channel memory of the first task.
摘要翻译：一种用于任务之间的单向通信的方法包括提供具有对一定量的虚拟存储器的访问的第一任务，阻止所述第一任务的虚拟存储器的通信信道部分，使得第一任务不能访问所述部分，提供第二任务，涉及与第一任务的虚拟存储器相当的虚拟存储器的量，其中与第一任务的虚拟存储器的被阻止部分相对应的第二任务的虚拟存储器的通信信道部分被标记为可写，传送第二任务的通信信道存储器到第一个任务，并解除第一个任务的通信通道存储器。

3. 发明授权

US5727187A Method of using logical names in post-synthesis electronic design automation systems 失效
标题翻译：后合成电子设计自动化系统中使用逻辑名称的方法
公开(公告)号：US5727187A
公开(公告)日：1998-03-10
申请号：US521697
申请日：1995-08-31
申请人： Carol L. Lemche , Harold E. Reindel
发明人： Carol L. Lemche , Harold E. Reindel
IPC分类号： G06T1/00 , G06F17/16
CPC分类号： G06T1/00
摘要： A method used by an electronic design automation system for allowing the use of logical names from a register transfer level description of an integrated circuit design in timing notes and simulation tests written for timing analysis and simulation programs. A synthesis program generates a state map file containing an entry for the logical name for each state defined in the register transfer level description of the integrated circuit. The gate level name generated by the synthesis program corresponding to the logical state name is stored in the entry providing a one to one mapping of a logical state name to a gate level state name. The state map file is input to timing analysis and simulation programs wherein references to the logical state names in timing notes and simulation tests are translated to gate level state names before further processing.
摘要翻译：电子设计自动化系统使用的方法，用于允许在针对时序分析和仿真程序编写的时序注释和仿真测试中使用集成电路设计的寄存器传输级别描述中的逻辑名称。合成程序生成包含在集成电路的寄存器传送级别描述中定义的每个状态的逻辑名的条目的状态图文件。将由逻辑状态名称对应的合成程序生成的门级别名称存储在提供逻辑状态名称与门级状态名称的一对一映射的条目中。将状态图文件输入到定时分析和仿真程序，其中在进一步处理之前，将时序注释和模拟测试中的逻辑状态名称的引用转换为门级状态名称。

4. 发明授权

US5805861A Method of stabilizing component and net names of integrated circuits in electronic design automation systems 失效
标题翻译：稳定电子设计自动化系统中集成电路的组件和网络名称的方法
公开(公告)号：US5805861A
公开(公告)日：1998-09-08
申请号：US524017
申请日：1995-08-29
申请人： Douglas J. Gilbert , James E. Rezek , Harold E. Reindel , Allen B. A. Tabbert
发明人： Douglas J. Gilbert , James E. Rezek , Harold E. Reindel , Allen B. A. Tabbert
IPC分类号： G06F17/50 , H02L21/70
CPC分类号： G06F17/5045
摘要： A method used by an electronic design automation system for stabilizing the names of components and nets of an integrated circuit from one design version to another. A previous integrated circuit design version and a current integrated circuit design version are partitioned into multiple cones of logic design. Each cone of logic design is defined by a path from a logic designer-defined apex net to a logic designer-defined base net affecting the apex net. Selected cones of logic design are compared. If the selected cones have identical logical structure, the component and net names of the previous integrated circuit design version are transferred to the current integrated circuit design version. If the selected cones of logic design do not have identical structure, then the component and net names for subsections of the selected cones of logic design that do have identical logical structure are transferred to the current integrated circuit design version, and new component and net names are assigned to those subsections of the selected cones of logic design from the current integrated circuit design version which did not exist in the previous integrated circuit design version.
摘要翻译：电子设计自动化系统使用的方法，用于将集成电路的组件和网络的名称从一个设计版本稳定到另一个。以前的集成电路设计版本和当前的集成电路设计版本分为多个逻辑设计锥。逻辑设计的每一个锥体由一个从逻辑设计者定义的顶点网络到影响顶点网络的逻辑设计者定义的基准网络的路径来定义。选择的逻辑设计锥被比较。如果选择的锥体具有相同的逻辑结构，则先前集成电路设计版本的组件和网络名称将转移到当前的集成电路设计版本。如果所选择的逻辑设计锥不具有相同的结构，那么确定具有相同逻辑结构的所选择的逻辑设计锥的部分和网名被转移到当前的集成电路设计版本，并且新的组件和网名被分配到从先前的集成电路设计版本中不存在的当前集成电路设计版本中选择的逻辑设计锥的那些子部分。

5. 发明授权

US06609228B1 Latch clustering for power optimization 失效
标题翻译：锁存聚类功能优化
公开(公告)号：US06609228B1
公开(公告)日：2003-08-19
申请号：US09713571
申请日：2000-11-15
申请人： Paul H. Bergeron , Keith M. Carrig , Alvar A. Dean , Roger P. Gregor , David J. Hathaway , David E. Lackey , Harold E. Reindel , Larry Wissel
发明人： Paul H. Bergeron , Keith M. Carrig , Alvar A. Dean , Roger P. Gregor , David J. Hathaway , David E. Lackey , Harold E. Reindel , Larry Wissel
IPC分类号： G06F1750
CPC分类号： G06F17/5072 , G06F2217/78
摘要： A method and structure of clock optimization including creating an initial placement of clock feeding circuits according to clock signal requirements; identifying clusters of the clock feeding circuits, wherein each cluster includes a distinct clock signal supply device to which each clock feeding circuit within the cluster is connected; changing pin connections between the clock feeding circuits and clock signal supply devices to switch selected ones of the clock feeding circuits to different clusters to reduce lengths of wires between the clock feeding circuits and the clock signal supply devices within each cluster; and adjusting positions of the clock feeding circuits within design constraints to further reduce the lengths of the wires.
摘要翻译：时钟优化的方法和结构，包括根据时钟信号要求创建时钟馈电电路的初始放置; 识别所述时钟馈送电路的簇，其中每个簇包括与所述簇内的每个时钟馈送电路连接的不同的时钟信号供应装置; 改变时钟馈电电路和时钟信号供应装置之间的引脚连接，以将选定的时钟馈电电路切换到不同的簇，以减少时钟馈送电路和每个集群内的时钟信号供应装置之间的导线长度; 以及在设计约束内调整时钟馈电电路的位置，以进一步减少电线的长度。

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