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1. 发明授权

US08222114B2 Manufacturing approach for collector and a buried layer of bipolar transistor 有权
标题翻译：集电极的制造方法和双极晶体管的埋层
公开(公告)号：US08222114B2
公开(公告)日：2012-07-17
申请号：US12979907
申请日：2010-12-28
申请人： Tzuyin Chiu , TungYuan Chu , YungChieh Fan , Wensheng Qian , Fan Chen , Jiong Xu , Haifang Zhang
发明人： Tzuyin Chiu , TungYuan Chu , YungChieh Fan , Wensheng Qian , Fan Chen , Jiong Xu , Haifang Zhang
IPC分类号： H01L21/331 , H01L21/22
CPC分类号： H01L29/7371 , H01L21/76237 , H01L21/76264 , H01L29/0653 , H01L29/0821 , H01L29/66272
摘要： This invention disclosed a novel manufacturing approach of collector and buried layer of a bipolar transistor. One aspect of the invention is that an oxide-nitride-oxide (ONO) sandwich structure is employed instead of oxide-nitride dual layer structure before trench etching. Another aspect is, through the formation of silicon oxide spacer in trench sidewall and silicon oxide remaining in trench bottom in the deposition and etch back process, the new structure hard mask can effectively protect active region from impurity implanted in ion implantation process.
摘要翻译：本发明公开了双极晶体管的集电极和掩埋层的新颖制造方法。本发明的一个方面是在沟槽蚀刻之前采用氧化物 - 氮化物 - 氧化物（ONO）夹层结构代替氧化氮化物双层结构。另一方面是，通过在沉积和回蚀工艺中在沟槽侧壁中形成氧化硅隔离物和保留在沟槽底部的氧化硅，新的结构硬掩模可以有效地保护有源区域免于植入离子注入过程中的杂质。

2. 发明授权

US08420495B2 Manufacturing approach for collector and a buried layer of bipolar transistor 有权
标题翻译：集电极的制造方法和双极晶体管的埋层
公开(公告)号：US08420495B2
公开(公告)日：2013-04-16
申请号：US12979999
申请日：2010-12-28
申请人： Tzuyin Chiu , TungYuan Chu , YungChieh Fan , Wensheng Qian , Fan Chen , Jiong Xu , Haifang Zhang
发明人： Tzuyin Chiu , TungYuan Chu , YungChieh Fan , Wensheng Qian , Fan Chen , Jiong Xu , Haifang Zhang
IPC分类号： H01L21/338 , H01L21/428 , H01L21/38 , H01L21/00
CPC分类号： H01L29/732 , H01L29/0821 , H01L29/66272
摘要： This invention disclosed a manufacturing approach of collector and buried layer of a bipolar transistor. One aspect of the invention is that a pseudo buried layer, i.e, collector buried layer, is manufactured by ion implantation and thermal anneal. This pseudo buried layer has a small area, which makes deep trench isolation to divide pseudo buried layer unnecessary in subsequent process. Another aspect is, the doped area, i.e, collector, is formed by ion implantation instead of high cost epitaxy process. This invention simplified the manufacturing process, as a consequence, saved manufacturing cost.
摘要翻译：本发明公开了双极晶体管的集电极和掩埋层的制造方法。本发明的一个方面是通过离子注入和热退火制造伪掩埋层，即集电极掩埋层。该伪掩埋层具有小的面积，这使得深沟槽隔离以在随后的工艺中不需要划分伪掩埋层。另一方面是，通过离子注入形成掺杂区域，即集电极，而不是高成本的外延工艺。本发明简化了制造过程，结果节省了制造成本。

3. 发明授权

US08674480B2 High voltage bipolar transistor with pseudo buried layers 有权
标题翻译：具有伪埋层的高压双极晶体管
公开(公告)号：US08674480B2
公开(公告)日：2014-03-18
申请号：US12966078
申请日：2010-12-13
申请人： Tzuyin Chiu , TungYuan Chu , Wensheng Qian , YungChieh Fan , Jun Hu , Donghua Liu , Yukun Lv
发明人： Tzuyin Chiu , TungYuan Chu , Wensheng Qian , YungChieh Fan , Jun Hu , Donghua Liu , Yukun Lv
IPC分类号： H01L29/66
CPC分类号： H01L21/76232 , H01L21/8249 , H01L27/0623 , H01L29/0657 , H01L29/0821 , H01L29/41708 , H01L29/66242 , H01L29/66287 , H01L29/7322 , H01L29/7378
摘要： A high voltage bipolar transistor with shallow trench isolation (STI) comprises the areas of a collector formed by implanting first electric type impurities into active area and connected with pseudo buried layers at two sides; Pseudo buried layers which are formed by implanting high dose first type impurity through the bottoms of STI at two sides if active area, and do not touch directly; deep contact through field oxide to contact pseudo buried layers and pick up the collectors; a base deposited on the collector by epitaxial growth and in-situ doped by second electric type impurity, in which the intrinsic base touches local collector and extrinsic base is used for base pick-up; a emitter which is a polysilicon layer deposited on the intrinsic base and doped with first electric type impurities. This invention makes the depletion region of collector/base junction from 1D (vertical) distribution to 2D (vertical and lateral) distribution. The bipolar transistor's breakdown voltages are increased by only enlarge active critical dimension (CD). This is low-cost process.
摘要翻译：具有浅沟槽隔离（STI）的高电压双极晶体管包括通过将第一电型杂质注入有源区并且在两侧与伪掩埋层连接而形成的集电极的区域; 伪埋层是通过在两侧的STI两侧植入高剂量第一类杂质而形成的，如果有活动区域，并且不直接接触; 通过场氧化物深接触接触伪埋层并拾取集电器; 通过外延生长沉积在集电体上并通过第二电型杂质原位掺杂的基极，其中本征基极接触局部集电极和外部基极用于基极拾取; 作为沉积在本征基底上并掺杂有第一电型杂质的多晶硅层的发射极。本发明使集电极/基极结的耗尽区从1D（垂直）分布到2D（垂直和横向）分布。双极晶体管的击穿电压仅通过增加主动临界尺寸（CD）来增加。这是低成本的过程。

4. 发明申请

US20110147892A1 Bipolar Transistor with Pseudo Buried Layers 审中-公开
标题翻译：具有伪埋层的双极晶体管
公开(公告)号：US20110147892A1
公开(公告)日：2011-06-23
申请号：US12966241
申请日：2010-12-13
申请人： Tzuyin Chiu , TungYuan Chu , Wensheng Qian , YungChieh Fan
发明人： Tzuyin Chiu , TungYuan Chu , Wensheng Qian , YungChieh Fan
IPC分类号： H01L29/70 , H01L21/331
CPC分类号： H01L29/732 , H01L21/76232 , H01L29/0821 , H01L29/41708 , H01L29/66287
摘要： A structure and fabrication method for a bipolar transistor with shallow trench isolation (STI) comprises a collector formed by implanting first electric type impurity in active area; pseudo buried layers at the bottom of STI at both sides of active area by implanting heavy dose of first electric type impurity; deep contacts through field oxide to connect to pseudo buried layers and to pick up the collector; a base, a thin film deposited on the collector and doped with second electric type impurity; an emitter, a polysilicon film doped by heavy dose implant of first electric type impurity. This transistor has smaller device area, less parasitic effect, less photo layers and lower process cost.
摘要翻译：具有浅沟槽隔离（STI）的双极晶体管的结构和制造方法包括通过在有源区域中注入第一电型杂质而形成的集电极; 通过植入重剂量的第一电型杂质，在有源区两侧STI底部的伪埋层; 通过场氧化物进行深度接触以连接到伪掩埋层并拾取收集器; 基底，沉积在集电体上并掺杂有第二电型杂质的薄膜; 发射极，通过第一电离杂质的大剂量注入掺杂的多晶硅膜。该晶体管具有较小的器件面积，较少的寄生效应，较少的照相层和较低的工艺成本。

5. 发明授权

US08421185B2 Parasitic vertical PNP bipolar transistor in BiCMOS process 有权
标题翻译： BiCMOS工艺中寄生垂直PNP双极晶体管
公开(公告)号：US08421185B2
公开(公告)日：2013-04-16
申请号：US12978552
申请日：2010-12-25
申请人： Tzuyin Chiu , TungYuan Chu , Wensheng Qian , YungChieh Fan , Donghua Liu , Jun Hu
发明人： Tzuyin Chiu , TungYuan Chu , Wensheng Qian , YungChieh Fan , Donghua Liu , Jun Hu
IPC分类号： H01L29/70
CPC分类号： H01L29/0821 , H01L21/743 , H01L21/76224 , H01L21/8249 , H01L27/0623 , H01L29/1004 , H01L29/66242 , H01L29/66287 , H01L29/732 , H01L29/7371 , H01L2924/0002 , H01L2924/00
摘要： A parasitic vertical PNP device in one type of BiCMOS process with shallow trench isolation (STI) comprises a collector formed by a p type impurity ion implantation layer inside active area, the bottom of collector connects to a p type buried layer, the p type pseudo buried layer is formed in bottom of shallow trench at both sides of collector active region through ion implantation, deep contacts through field oxide to connect pseudo buried layers and to pick up the collector; a base, formed by n type impurity ion implantation layer which sits on top of above stated collector; an emitter, a p type epitaxy layer lies above base and is connected out directly by a metal contact. Part of the p type epitaxy layer is converted into n type, which serves as connection path of base. Present invented PNP can be used as output device of BiCMOS high frequency circuit. It has a small device area and conduction resistance.
摘要翻译：具有浅沟槽隔离（STI）的一种类型的BiCMOS工艺中的寄生垂直PNP器件包括由有源区内的ap型杂质离子注入层形成的集电极，集电极的底部连接到ap型掩埋层，p型伪掩埋层通过离子注入形成在集电极有源区两侧的浅沟底部，通过场氧化物深接触连接伪埋层并拾取收集器; 由位于上述收集器顶部的n型杂质离子注入层形成的基底; 发射极，p型外延层位于基底之上，并通过金属接触直接连接。 p型外延层的一部分被转换为n型，其用作基极的连接路径。本发明的PNP可用作BiCMOS高频电路的输出装置。它具有小的器件面积和导通电阻。

6. 发明授权

US08420475B2 Parasitic vertical PNP bipolar transistor and its fabrication method in BiCMOS process 有权
标题翻译：寄生垂直PNP双极晶体管及其在BiCMOS工艺中的制造方法
公开(公告)号：US08420475B2
公开(公告)日：2013-04-16
申请号：US12975545
申请日：2010-12-22
申请人： Tzuyin Chiu , TungYuan Chu , Wensheng Qian , YungChieh Fan , Donghua Liu , Jun Hu
发明人： Tzuyin Chiu , TungYuan Chu , Wensheng Qian , YungChieh Fan , Donghua Liu , Jun Hu
IPC分类号： H01L21/8238
CPC分类号： H01L29/732 , H01L21/8249 , H01L27/0623 , H01L29/0821 , H01L29/1004 , H01L29/66242 , H01L29/66287 , H01L29/7371
摘要： This invention published a parasitic vertical PNP bipolar transistor in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process; the bipolar transistor comprises a collector, a base and an emitter. Collector is formed by active region with p-type ion implanting layer. It connects a p-type buried layer which formed in the bottom region of STI (Shallow Trench Isolation). The collector terminal connection is through the p-type buried layer and the adjacent active region. The base is formed by active region with n type ion implanting which is on the collector. Its connection is through the original p-type epitaxy layer after converting to n-type. The emitter is formed by the p-type epitaxy layer on the base region with heavy p-type doped. This invention also comprises the fabrication method of this parasitic vertical PNP bipolar in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process. And this PNP bipolar transistor can be used as the IO (Input/Output) device in high speed, high current and power gain BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) circuits. It also provides a device option with low cost.
摘要翻译：本发明公开了BiCMOS（双极互补金属氧化物半导体）工艺中的寄生垂直PNP双极晶体管; 双极晶体管包括集电极，基极和发射极。集电极由具有p型离子注入层的有源区形成。它连接形成在STI底部区域（浅沟槽隔离）的p型掩埋层。集电极端子连接通过p型掩埋层和相邻的有源区。基极由在集电极上的n型离子注入的有源区形成。其连接是通过原始的p型外延层转换为n型。发射极由重p型掺杂的基极区上的p型外延层形成。本发明还包括BiCMOS（双极互补金属氧化物半导体）工艺中该寄生垂直PNP双极的制造方法。而这种PNP双极晶体管可以用作高速，大电流和功率增益BiCMOS（双极互补金属氧化物半导体）电路中的IO（输入/输出）器件。它还提供低成本的设备选项。

7. 发明授权

US08289118B2 Stacked inductor 有权
标题翻译：堆叠电感
公开(公告)号：US08289118B2
公开(公告)日：2012-10-16
申请号：US12963462
申请日：2010-12-08
申请人： Tzuyin Chiu , Xiangming Xu , Miao Cai
发明人： Tzuyin Chiu , Xiangming Xu , Miao Cai
IPC分类号： H01F21/02 , H01F5/00 , H01F27/28
CPC分类号： H01F17/0013
摘要： A stacked inductor with combined metal layers is represented in this invention. The stacked inductor includes: a top layer metal coil, and at least two lower layer metal coils, the metal coils being aligned with each other; adjacent metal coils being connected at the corresponding ends through a via; wherein, each of the lower layer metal coils is consisted of plural layers of metal lines which are interconnected. With the same chip area, the stacked inductor of the present invention can achieve higher inductance and Q factor because of the mutual inductance generated from the plural layers of metal lines and the reduced parasitic resistance.
摘要翻译：具有组合金属层的堆叠电感器在本发明中被表示。堆叠电感器包括：顶层金属线圈和至少两个下层金属线圈，金属线圈彼此对准; 相邻的金属线圈通过通孔在相应的端部连接; 其中，每个下层金属线圈由互连的多层金属线构成。由于相同的芯片面积，由于由多层金属线产生的互感和降低的寄生电阻，本发明的层叠电感器可以实现更高的电感和Q因数。

8. 发明授权

US08227832B2 SiGe heterojunction bipolar transistor multi-finger structure 有权
标题翻译： SiGe异质结双极晶体管多指结构
公开(公告)号：US08227832B2
公开(公告)日：2012-07-24
申请号：US12971063
申请日：2010-12-17
申请人： Tzuyin Chiu , Zhengliang Zhou , Xiongbin Chen
发明人： Tzuyin Chiu , Zhengliang Zhou , Xiongbin Chen
IPC分类号： H01L29/66
CPC分类号： H01L29/7378 , H01L29/0692 , H01L29/0821
摘要： The present invention provides a multi-finger structure of a SiGe heterojunction bipolar transistor (HBT). It is consisted of plural SiGe HBT single cells. The multi-finger structure is in a form of C/BEBC/BEBC/.../C, wherein, C, B, E respectively stands for collector, base and emitter; CBEBC stands for a SiGe HBT single cell. The collector region is consisted of an n type ion implanted layer inside the active region. The bottom of the implanted layer is connected to two n type pseudo buried layers. The two pseudo buried layers are formed through implantation to the bottom of the shallow trenches that surround the collector active region. Two collectors are picked up by deep trench contact through the field oxide above the two pseudo buried layers. The present invention can reduce junction capacitance, decrease collector electrode output resistance, and improve device frequency characteristics.
摘要翻译：本发明提供了一种SiGe异质结双极晶体管（HBT）的多指结构。它由多个SiGe HBT单电池组成。多指结构为C / BEBC / BEBC / ... / C，其中C，B，E分别代表集电极，基极和发射极; CBEBC代表SiGe HBT单电池。集电极区域由有源区域内的n型离子注入层构成。注入层的底部连接到两个n型伪埋层。两个伪埋层通过注入到围绕收集器有源区的浅沟槽的底部而形成。通过深沟槽接触通过两个伪埋层之上的场氧化物拾取两个集电极。本发明可以减少结电容，降低集电极输出电阻，提高器件频率特性。

9. 发明授权

US08441333B2 Stack inductor with different metal thickness and metal width 有权
标题翻译：堆叠电感器具有不同的金属厚度和金属宽度
公开(公告)号：US08441333B2
公开(公告)日：2013-05-14
申请号：US12958080
申请日：2010-12-01
申请人： Tzuyin Chiu , Xiangming Xu , Miao Cai
发明人： Tzuyin Chiu , Xiangming Xu , Miao Cai
IPC分类号： H01F5/00 , H01F27/28
CPC分类号： H01L23/5227 , H01F17/0013 , H01F2017/0073 , H01L2924/0002 , H01L2924/00
摘要： A stacked inductor with different metal thickness and metal width. The stacked inductor comprises top and bottom metal traces which are aligned with each other. The thickness and width of the top and bottom metal traces are different. The top and bottom metal traces are connected at the end of metal trace with via holes. The inductance is increased with the use of the mutual inductance between top and bottom metal layers The parasitic resistor is reduced due to the difference of the top and bottom metal widths.
摘要翻译：具有不同金属厚度和金属宽度的堆叠电感器。堆叠的电感器包括彼此对准的顶部和底部金属迹线。顶部和底部金属轨迹的厚度和宽度是不同的。顶部和底部金属轨迹在金属轨迹末端与通孔相连。使用顶部和底部金属层之间的互感，电感增加。由于顶部和底部金属宽度的差异，寄生电阻减小。

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