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1. 发明申请

US20180032648A1 SIMULATION METHOD OF CMP PROCESS 审中-公开
公开(公告)号：US20180032648A1
公开(公告)日：2018-02-01
申请号：US15283286
申请日：2016-09-30
申请人： Yun Cao , Huan Kan , Fang Wei , Jun Zhu , Yukun Lv , Xusheng Zhang
发明人： Yun Cao , Huan Kan , Fang Wei , Jun Zhu , Yukun Lv , Xusheng Zhang
IPC分类号： G06F17/50 , H01L21/768
CPC分类号： G06F17/504 , G06F2217/16 , H01L21/76819
摘要： The invention disclosed a simulation method of CMP process, comprising: firstly, building a CMP model, and forming a matrix table of line width logarithm-density according to the CMP model, and making each intersection of the matrix table correspond to each CMP result under the corresponding line width and density; secondly, dividing a layout into a plurality of grids, and converting the equivalent line width and density of each grid into the coordinate of line width logarithm-density in the matrix table; thirdly, fitting and calculating preliminary CMP simulation results of each grid according to the coordinate of each grid in the matrix table and the CMP simulation results of its adjacent intersections of the matrix table; then, fitting and computing final CMP simulation results of each grid according to a related weighting factor which considers the impact of adjacent grids for the current grid on the layout; finally, outputting the final CMP simulation results of the whole layout.

2. 发明申请

US20110140239A1 High Voltage Bipolar Transistor with Pseudo Buried Layers 有权
标题翻译：具有伪埋层的高电压双极晶体管
公开(公告)号：US20110140239A1
公开(公告)日：2011-06-16
申请号：US12966078
申请日：2010-12-13
申请人： Tzuyin CHIU , TungYuan CHU , Wensheng QIAN , YungChieh FAN , Jun HU , Donghua LIU , Yukun LV
发明人： Tzuyin CHIU , TungYuan CHU , Wensheng QIAN , YungChieh FAN , Jun HU , Donghua LIU , Yukun LV
IPC分类号： H01L29/70
CPC分类号： H01L21/76232 , H01L21/8249 , H01L27/0623 , H01L29/0657 , H01L29/0821 , H01L29/41708 , H01L29/66242 , H01L29/66287 , H01L29/7322 , H01L29/7378
摘要： A high voltage bipolar transistor with shallow trench isolation (STI) comprises the areas of a collector formed by implanting first electric type impurities into active area and connected with pseudo buried layers at two sides; Pseudo buried layers which are formed by implanting high dose first type impurity through the bottoms of STI at two sides if active area, and do not touch directly; deep contact through field oxide to contact pseudo buried layers and pick up the collectors; a base deposited on the collector by epitaxial growth and in-situ doped by second electric type impurity, in which the intrinsic base touches local collector and extrinsic base is used for base pick-up; a emitter which is a polysilicon layer deposited on the intrinsic base and doped with first electric type impurities. This invention makes the depletion region of collector/base junction from 1D (vertical) distribution to 2D (vertical and lateral) distribution. The bipolar transistor's breakdown voltages are increased by only enlarge active critical dimension (CD). This is low-cost process.
摘要翻译：具有浅沟槽隔离（STI）的高电压双极晶体管包括通过将第一电型杂质注入有源区并且在两侧与伪掩埋层连接而形成的集电极的区域; 伪埋层是通过在两侧的STI两侧植入高剂量第一类杂质而形成的，如果有活动区域，并且不直接接触; 通过场氧化物深接触接触伪埋层并拾取集电器; 通过外延生长沉积在集电体上并通过第二电型杂质原位掺杂的基极，其中本征基极接触局部集电极和外部基极用于基极拾取; 作为沉积在本征基底上并掺杂有第一电型杂质的多晶硅层的发射极。本发明使集电极/基极结的耗尽区从1D（垂直）分布到2D（垂直和横向）分布。双极晶体管的击穿电压仅通过增加主动临界尺寸（CD）来增加。这是低成本的过程。

3. 发明申请

US20160291458A1 METHOD INTEGRATING TARGET OPTIMIZATION AND OPTICAL PROXIMITY CORRECTION 审中-公开
标题翻译：方法集成目标优化和光学近似校正
公开(公告)号：US20160291458A1
公开(公告)日：2016-10-06
申请号：US14753192
申请日：2015-06-29
申请人： Daquan He , Fang Wei , Jun Zhu , Yukun Lv , Xusheng Zhang
发明人： Daquan He , Fang Wei , Jun Zhu , Yukun Lv , Xusheng Zhang
IPC分类号： G03F1/36 , G06F17/50
CPC分类号： G03F1/36
摘要： A method integrating target optimization and optical proximity correction including: fragmenting sides of a target pattern in the metal layer to form a plurality of fragments; simulating the target pattern and calculating image log slope of each fragment; calculating a target pattern optimal parameter for each fragment which is a product of three parameters including the image log slope, overlap ratio of the target pattern and a via pattern in a via layer, and critical dimension; optimizing the target pattern based on the target pattern optimal parameter; preforming optical proximity correction to the optimized target pattern; determining whether the corrected target pattern meets requirements; if yes, ending the target optimization and optical proximity correction; otherwise, using the corrected target pattern as a current target pattern and iterate from the step of simulating the target pattern and calculating image log slope of each fragment.
摘要翻译：一种集成目标优化和光学邻近校正的方法，包括：金属层中的目标图案的碎裂边以形成多个碎片; 模拟目标模式并计算每个片段的图像对数斜率; 计算每个片段的目标图案最优参数，该三个参数的乘积包括图像对数斜率，目标图案的重叠率和通孔层中的通孔图案以及临界尺寸; 基于目标模式优化参数优化目标模式; 对优化的目标图案进行光学邻近校正; 确定校正的目标模式是否满足要求; 如果是，结束目标优化和光学邻近校正; 否则，使用校正的目标图案作为当前目标图案，并且从模拟目标图案的步骤并且计算每个片段的图像对数斜率来迭代。

4. 发明申请

US20180144929A1 METHOD FOR FORMING HIGH ASPECT RATIO PATTERNING STRUCTURE 有权
公开(公告)号：US20180144929A1
公开(公告)日：2018-05-24
申请号：US15385884
申请日：2016-12-21
申请人： Peng Liu , Qiyan Feng , Yu Ren , Yukun Lv , Jun Zhu , Hsusheng Chang
发明人： Peng Liu , Qiyan Feng , Yu Ren , Yukun Lv , Jun Zhu , Hsusheng Chang
IPC分类号： H01L21/027 , H01L21/311 , H01L21/02 , G03F7/095
CPC分类号： H01L21/0273 , G03F7/095 , H01L21/02271 , H01L21/02282 , H01L21/3065 , H01L21/3081 , H01L21/31116 , H01L21/31138
摘要： The invention disclosed a method for forming high aspect ratio patterning structure. Firstly, forming a dielectric film ashing stop layer, a first photoresist layer, a first hard mask layer and a second photoresist layer on a semiconductor substrate in turn. A second hard mask layer having a high etch selectivity ratio with the first photoresist layer is formed on top surface and sidewall of the pattern by utilizing a low temperature chemical vapor deposition process, which can be a protect for the pattern sidewall during the later etching process of the first photoresist layer. So, the cone-shaped or the bowling-shaped photoresist morphology caused by plasma bombardment can be avoided. Therefore, the problems of the insufficient of selectivity ratio, burrs at the edge of the pattern and larger critical dimension can be solved, and the implanted ions can be well distributed according to the design of the device.

5. 发明授权

US09666472B2 Method for establishing mapping relation in STI etch and controlling critical dimension of STI 有权
公开(公告)号：US09666472B2
公开(公告)日：2017-05-30
申请号：US15083292
申请日：2016-03-29
申请人： Jin Xu , Qiyan Feng , Yu Ren , Yukun Lv , Xusheng Zhang
发明人： Jin Xu , Qiyan Feng , Yu Ren , Yukun Lv , Xusheng Zhang
IPC分类号： H01L21/00 , H01L21/762 , H01L21/027 , H01L21/308 , H01L21/66
CPC分类号： H01L21/76224 , H01L21/0276 , H01L21/3081 , H01L21/3083 , H01L21/3086 , H01L22/12 , H01L22/20
摘要： The present invention provides a method for controlling a critical dimension of shallow trench isolations in a STI etch process, comprises the following steps: before the STI etch process, pre-establishing a mapping relation between a post-etch and pre-etch critical dimension difference of a BARC layer and a thickness of the BARC layer; and during the STI etch process after coating the BARC layer, measuring the thickness of the BARC layer and determining a trimming time for a hard mask layer according to a critical dimension difference corresponding to the measured thickness in the mapping relation and a critical dimension of a photoresist pattern, then performing a trimming process for the hard mask layer lasting the trimming time to make a critical dimension of the hard mask layer equal to a required critical dimension of an active area, and etching a substrate to form shallow trenches with a predetermined critical dimension.

6. 发明申请

US20170025304A1 METHOD FOR ESTABLISHING MAPPING RELATION IN STI ETCH AND CONTROLLING CRITICAL DIMENSION OF STI 有权
标题翻译：用于建立STI蚀刻中的映射关系和控制STI的关键尺寸的方法
公开(公告)号：US20170025304A1
公开(公告)日：2017-01-26
申请号：US15083292
申请日：2016-03-29
申请人： Jin Xu , Qiyan Feng , Yu Ren , Yukun Lv , Xusheng Zhang
发明人： Jin Xu , Qiyan Feng , Yu Ren , Yukun Lv , Xusheng Zhang
IPC分类号： H01L21/762 , H01L21/308 , H01L21/66 , H01L21/027
CPC分类号： H01L21/76224 , H01L21/0276 , H01L21/3081 , H01L21/3083 , H01L21/3086 , H01L22/12 , H01L22/20
摘要： The present invention provides a method for controlling a critical dimension of shallow trench isolations in a STI etch process, comprises the following steps: before the STI etch process, pre-establishing a mapping relation between a post-etch and pre-etch critical dimension difference of a BARC layer and a thickness of the BARC layer; and during the STI etch process after coating the BARC layer, measuring the thickness of the BARC layer and determining a trimming time for a hard mask layer according to a critical dimension difference corresponding to the measured thickness in the mapping relation and a critical dimension of a photoresist pattern, then performing a trimming process for the hard mask layer lasting the trimming time to make a critical dimension of the hard mask layer equal to a required critical dimension of an active area, and etching a substrate to form shallow trenches with a predetermined critical dimension.
摘要翻译：本发明提供了一种用于在STI蚀刻工艺中控制浅沟槽隔离的临界尺寸的方法，包括以下步骤：在STI蚀刻工艺之前，预先建立蚀刻后和临界尺寸之间的临界尺寸差的映射关系的BARC层和BARC层的厚度; 并且在涂覆BARC层之后的STI蚀刻工艺期间，测量BARC层的厚度并根据对应于映射关系中的测量厚度的临界尺寸差异确定硬掩模层的修剪时间，并且确定光刻胶图案，然后对硬掩模层进行修整处理以保持修剪时间，以使硬掩模层的临界尺寸等于有源区的所需临界尺寸，并蚀刻衬底以形成具有预定临界值的浅沟槽尺寸。

7. 发明授权

US08674480B2 High voltage bipolar transistor with pseudo buried layers 有权
标题翻译：具有伪埋层的高压双极晶体管
公开(公告)号：US08674480B2
公开(公告)日：2014-03-18
申请号：US12966078
申请日：2010-12-13
申请人： Tzuyin Chiu , TungYuan Chu , Wensheng Qian , YungChieh Fan , Jun Hu , Donghua Liu , Yukun Lv
发明人： Tzuyin Chiu , TungYuan Chu , Wensheng Qian , YungChieh Fan , Jun Hu , Donghua Liu , Yukun Lv
IPC分类号： H01L29/66
CPC分类号： H01L21/76232 , H01L21/8249 , H01L27/0623 , H01L29/0657 , H01L29/0821 , H01L29/41708 , H01L29/66242 , H01L29/66287 , H01L29/7322 , H01L29/7378
摘要： A high voltage bipolar transistor with shallow trench isolation (STI) comprises the areas of a collector formed by implanting first electric type impurities into active area and connected with pseudo buried layers at two sides; Pseudo buried layers which are formed by implanting high dose first type impurity through the bottoms of STI at two sides if active area, and do not touch directly; deep contact through field oxide to contact pseudo buried layers and pick up the collectors; a base deposited on the collector by epitaxial growth and in-situ doped by second electric type impurity, in which the intrinsic base touches local collector and extrinsic base is used for base pick-up; a emitter which is a polysilicon layer deposited on the intrinsic base and doped with first electric type impurities. This invention makes the depletion region of collector/base junction from 1D (vertical) distribution to 2D (vertical and lateral) distribution. The bipolar transistor's breakdown voltages are increased by only enlarge active critical dimension (CD). This is low-cost process.
摘要翻译：具有浅沟槽隔离（STI）的高电压双极晶体管包括通过将第一电型杂质注入有源区并且在两侧与伪掩埋层连接而形成的集电极的区域; 伪埋层是通过在两侧的STI两侧植入高剂量第一类杂质而形成的，如果有活动区域，并且不直接接触; 通过场氧化物深接触接触伪埋层并拾取集电器; 通过外延生长沉积在集电体上并通过第二电型杂质原位掺杂的基极，其中本征基极接触局部集电极和外部基极用于基极拾取; 作为沉积在本征基底上并掺杂有第一电型杂质的多晶硅层的发射极。本发明使集电极/基极结的耗尽区从1D（垂直）分布到2D（垂直和横向）分布。双极晶体管的击穿电压仅通过增加主动临界尺寸（CD）来增加。这是低成本的过程。

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