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    • 1. 发明授权
    • Stacked inductor
    • 堆叠电感
    • US08289118B2
    • 2012-10-16
    • US12963462
    • 2010-12-08
    • Tzuyin ChiuXiangming XuMiao Cai
    • Tzuyin ChiuXiangming XuMiao Cai
    • H01F21/02H01F5/00H01F27/28
    • H01F17/0013
    • A stacked inductor with combined metal layers is represented in this invention. The stacked inductor includes: a top layer metal coil, and at least two lower layer metal coils, the metal coils being aligned with each other; adjacent metal coils being connected at the corresponding ends through a via; wherein, each of the lower layer metal coils is consisted of plural layers of metal lines which are interconnected. With the same chip area, the stacked inductor of the present invention can achieve higher inductance and Q factor because of the mutual inductance generated from the plural layers of metal lines and the reduced parasitic resistance.
    • 具有组合金属层的堆叠电感器在本发明中被表示。 堆叠电感器包括:顶层金属线圈和至少两个下层金属线圈,金属线圈彼此对准; 相邻的金属线圈通过通孔在相应的端部连接; 其中,每个下层金属线圈由互连的多层金属线构成。 由于相同的芯片面积,由于由多层金属线产生的互感和降低的寄生电阻,本发明的层叠电感器可以实现更高的电感和Q因数。
    • 2. 发明申请
    • STACKED INDUCTOR
    • 堆叠电感器
    • US20110133879A1
    • 2011-06-09
    • US12963462
    • 2010-12-08
    • Tzuyin CHIUXiangming XuMiao Cai
    • Tzuyin CHIUXiangming XuMiao Cai
    • H01F5/00
    • H01F17/0013
    • A stacked inductor with combined metal layers is represented in this invention. The stacked inductor includes: a top layer metal coil, and at least two lower layer metal coils, the metal coils being aligned with each other; adjacent metal coils being connected at the corresponding ends through a via; wherein, each of the lower layer metal coils is consisted of plural layers of metal lines which are interconnected. With the same chip area, the stacked inductor of the present invention can achieve higher inductance and Q factor because of the mutual inductance generated from the plural layers of metal lines and the reduced parasitic resistance.
    • 具有组合金属层的堆叠电感器在本发明中被表示。 堆叠电感器包括:顶层金属线圈和至少两个下层金属线圈,金属线圈彼此对准; 相邻的金属线圈通过通孔在相应的端部连接; 其中,每个下层金属线圈由互连的多层金属线构成。 由于相同的芯片面积,由于由多层金属线产生的互感和降低的寄生电阻,本发明的层叠电感器可以实现更高的电感和Q因数。
    • 7. 发明授权
    • Pin soldering for printed circuit board failure testing
    • 针焊接印刷电路板故障测试
    • US08534136B2
    • 2013-09-17
    • US12751061
    • 2010-03-31
    • Dongji XieMiao CaiBoyi Wu
    • Dongji XieMiao CaiBoyi Wu
    • G01N3/08
    • G01N3/08G01N2203/0226G01N2203/0286
    • Systems and methods for performing pin-pull testing of a printed circuit board (PCB) are presented. The pin-pull testing generally involves the use of a standard tensile tester that is useful for performing other tests aside from pin-pull testing. In this regard, a non-specific pin may be used in conjunction with the tensile tester without the need to purchase or manufacture pins specially adapted for use with a specially designed tensile tester. Additionally, the pin-pull testing may include application of heat to the pin by way of an external heat supply such that the need of a heater integrated into the testing device to heat a pin during the testing may be eliminated. As such, a common heating element (e.g., a standard soldering iron) may be employed by applying heat to a pin directly with the external heat supply. Additionally, a dying process is presented that may be performed on a PCB prior to the pin-pull test that allows for evaluation of the presence of cracks in the PCB adjacent to a contact pad prior to the execution of the pin-pull test.
    • 提出了一种用于执行印刷电路板(PCB)引脚测试的系统和方法。 引脚测试通常涉及使用标准拉伸试验机,除了引脚拉力测试外,它还可用于执行其他试验。 在这方面,非特定销可以与拉力试验机一起使用,而不需要购买或制造专门用于特殊设计的拉伸试验机的销。 此外,引脚测试可以包括通过外部热源向引脚施加热量,使得可以消除在测试期间集成到测试装置中以加热引脚的加热器的需要。 因此,可以通过与外部热源直接对销进行加热来采用普通的加热元件(例如,标准烙铁)。 另外,提供了可以在引脚测试之前在PCB上执行的垂死过程,其允许在执行引脚测试之前评估邻近接触焊盘的PCB中存在的裂纹。