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1. 发明授权

US07474579B2 Use of periodic refresh in medium retention memory arrays 有权
标题翻译：在介质保留存储器阵列中使用定期更新
公开(公告)号：US07474579B2
公开(公告)日：2009-01-06
申请号：US11613832
申请日：2006-12-20
申请人： Colin S. Bill , Swaroop Kaza , Wei Daisy Cai , Tzu-Ning Fang , David Gaun , Eugen Gershon , Michael A. Van Buskirk , Jean Wu
发明人： Colin S. Bill , Swaroop Kaza , Wei Daisy Cai , Tzu-Ning Fang , David Gaun , Eugen Gershon , Michael A. Van Buskirk , Jean Wu
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40615 , G11C13/0033 , G11C13/0069 , G11C16/3431
摘要： Systems and methods are disclosed that facilitate extending data retention time in a data retention device, such as a nanoscale resistive memory cell array, via assessing a resistance level in a tracking element associated with the memory array and refreshing the memory array upon a determination that the resistance of the tracking element has reached or exceeded a predetermined reference threshold resistance value. The tracking element can be a memory cell within the array itself and can have an initial resistance value that is substantially higher than an initial resistance value for a programmed memory cell in the array, such that resistance increase in the tracking cell will cause the tracking cell to reach the threshold value and trigger refresh of the array before data corruption/loss occurs in the core memory cells.
摘要翻译：公开了通过评估与存储器阵列相关联的跟踪元件中的电阻水平并在确定存储器阵列的情况下刷新存储器阵列时有助于在诸如纳米级电阻存储器单元阵列之类的数据保持装置中扩展数据保留时间的系统和方法跟踪元件的电阻已达到或超过预定参考阈值电阻值。跟踪元件可以是阵列本身内的存储器单元，并且可以具有基本上高于阵列中的编程存储器单元的初始电阻值的初始电阻值，使得跟踪单元中的电阻增加将导致跟踪单元在核心存储器单元中发生数据损坏/丢失之前达到阈值并触发阵列刷新。

2. 发明申请

US20080151669A1 USE OF PERIODIC REFRESH IN MEDIUM RETENTION MEMORY ARRAYS 有权
标题翻译：在中继记忆阵列中使用周期性刷新
公开(公告)号：US20080151669A1
公开(公告)日：2008-06-26
申请号：US11613832
申请日：2006-12-20
申请人： Colin S. Bill , Swaroop Kaza , Wei Daisy Cai , Tzu-Ning Fang , David Gaun , Eugen Gershon , Michael A. Van Buskirk , Jean Wu
发明人： Colin S. Bill , Swaroop Kaza , Wei Daisy Cai , Tzu-Ning Fang , David Gaun , Eugen Gershon , Michael A. Van Buskirk , Jean Wu
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40615 , G11C13/0033 , G11C13/0069 , G11C16/3431
摘要： Systems and methods are disclosed that facilitate extending data retention time in a data retention device, such as a nanoscale resistive memory cell array, via assessing a resistance level in a tracking element associated with the memory array and refreshing the memory array upon a determination that the resistance of the tracking element has reached or exceeded a predetermined reference threshold resistance value. The tracking element can be a memory cell within the array itself and can have an initial resistance value that is substantially higher than an initial resistance value for a programmed memory cell in the array, such that resistance increase in the tracking cell will cause the tracking cell to reach the threshold value and trigger refresh of the array before data corruption/loss occurs in the core memory cells.
摘要翻译：公开了通过评估与存储器阵列相关联的跟踪元件中的电阻水平并在确定存储器阵列的情况下刷新存储器阵列时有助于在诸如纳米级电阻存储器单元阵列之类的数据保持装置中扩展数据保留时间的系统和方法跟踪元件的电阻已达到或超过预定参考阈值电阻值。跟踪元件可以是阵列本身内的存储器单元，并且可以具有基本上高于阵列中的编程存储器单元的初始电阻值的初始电阻值，使得跟踪单元中的电阻增加将导致跟踪单元在核心存储器单元中发生数据损坏/丢失之前达到阈值并触发阵列刷新。

3. 发明授权

US07072781B1 Architecture for generating adaptive arbitrary waveforms 失效
标题翻译：用于生成自适应任意波形的体系结构
公开(公告)号：US07072781B1
公开(公告)日：2006-07-04
申请号：US10885284
申请日：2004-07-06
申请人： Eugen Gershon , David Gaun , Colin S. Bill , Tzu-Ning Fang
发明人： Eugen Gershon , David Gaun , Colin S. Bill , Tzu-Ning Fang
IPC分类号： G01R31/36
CPC分类号： G01R31/31924 , G01R31/3167 , G01R31/31908 , G11C29/56 , G11C29/56004
摘要： A test system having a feedback loop that facilitates adjusting an output test waveform to a DUT/CUT (Device Under Test/Circuit Under Test) on-the-fly according to changing DUT/CUT parameters. The system includes a tester having an arbitrary waveform generator (AWG) and a data acquisition system (DAS) that monitors the status of the DUT/CUT. The AWG and DAS connect to the DUT/CUT through a feedback loop where the AWG outputs the test waveform to the DUT/CUT, the DAS monitors the DUT/CUT parameters, and the DAS analyzes and communicates changes to the AWG to effect changes in the output waveform, when desired. The AWG builds the output waveform in small slices (or segments) that are assembled together through a process of selection and calibration. The feedback architecture facilitates a number of changes in the output waveform, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform.
摘要翻译：具有反馈回路的测试系统，其根据改变的DUT / CUT参数，有助于将DUT / CUT（被测设备/待测电路）的输出测试波形实时调整。该系统包括具有任意波形发生器（AWG）的测试器和监视DUT / CUT的状态的数据采集系统（DAS）。 AWG和DAS通过反馈回路连接到DUT / CUT，AWG将测试波形输出到DUT / CUT，DAS监视DUT / CUT参数，DAS分析并传送AWG的变化，以实现更改输出波形。 AWG通过选择和校准过程组装在一起的小片（或片段）中构建输出波形。反馈架构有助于输出波形的一些变化，包括预先组装的切片的原始顺序的改变以及输出波形的幅度/形状的变化。

4. 发明申请

US20120092924A1 METHOD OF PROVIDING AN ERASE ACTIVATION ENERGY OF A MEMORY DEVICE 审中-公开
标题翻译：提供存储器件的擦除活化能的方法
公开(公告)号：US20120092924A1
公开(公告)日：2012-04-19
申请号：US13324310
申请日：2011-12-13
申请人： Michael A. VanBuskirk , Colin S. Bill , Zhida Lan , Tzu-Ning Fang
发明人： Michael A. VanBuskirk , Colin S. Bill , Zhida Lan , Tzu-Ning Fang
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： G11C13/0014 , B82Y10/00
摘要： A write-once read-many times memory device is made up of first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second electrode. The memory device is programmed by providing a charged species from the passive layer into the active layer. The memory device may be programmed to have for the programmed memory device a first erase activation energy. The present method provides for the programmed memory device a second erase activation energy greater than the first erase activation energy.
摘要翻译：一次写入多次存储器件由第一和第二电极，第一和第二电极之间的无源层以及第一和第二电极之间的有源层组成。通过从被动层提供带电物质到活性层来对存储器件进行编程。存储器件可以被编程为使编程的存储器件具有第一擦除激活能量。本方法为编程的存储器件提供大于第一擦除激活能量的第二擦除激活能量。

5. 发明授权

US07443710B2 Control of memory devices possessing variable resistance characteristics 有权
标题翻译：具有可变电阻特性的存储器件的控制
公开(公告)号：US07443710B2
公开(公告)日：2008-10-28
申请号：US10983919
申请日：2004-11-08
申请人： Tzu-Ning Fang , Michael Allen Van Buskirk , Colin S. Bill
发明人： Tzu-Ning Fang , Michael Allen Van Buskirk , Colin S. Bill
IPC分类号： G11C11/00
CPC分类号： G11C11/5664 , B82Y10/00 , G11C13/0014 , G11C13/0069 , G11C13/0097 , G11C2013/0071 , G11C2013/0078 , G11C2213/15 , G11C2213/79
摘要： Systems and methods employing at least one constant current source to facilitate programming of an organic memory cell and/or employing at least one constant voltage source to facilitate erasing of a memory device. The present invention is utilized in single memory cell devices and memory cell arrays. Employing a constant current source prevents current spikes during programming and allows accurate control of a memory cell's state during write cycles, independent of the cell's resistance. Employing a constant voltage source provides a stable load for memory cells during erase cycles and allows for accurate voltage control across the memory cell despite large dynamic changes in cell resistance during the process.
摘要翻译：采用至少一个恒定电流源的系统和方法促进有机存储器单元的编程和/或采用至少一个恒定电压源以便于擦除存储器件。本发明用于单个存储器单元装置和存储单元阵列。使用恒流源防止编程期间的电流尖峰，并允许在写周期期间精确控制存储单元的状态，而与电池的电阻无关。使用恒定电压源在擦除周期期间为存储器单元提供稳定的负载，并且允许跨过存储器单元的精确的电压控制，尽管在该过程中电池电阻的大的动态变化。

6. 发明授权

US07379317B2 Method of programming, reading and erasing memory-diode in a memory-diode array 有权
标题翻译：在存储二极管阵列中编程，读取和擦除存储二极管的方法
公开(公告)号：US07379317B2
公开(公告)日：2008-05-27
申请号：US11021958
申请日：2004-12-23
申请人： Colin S. Bill , Swaroop Kaza , Tzu-Ning Fang , Stuart Spitzer
发明人： Colin S. Bill , Swaroop Kaza , Tzu-Ning Fang , Stuart Spitzer
IPC分类号： G11C5/06 , G11C17/06
CPC分类号： G11C11/36
摘要： A memory array includes first and second sets of conductors and a plurality of memory-diodes, each connecting in a forward direction a conductor of the first set with a conductor of the second set. An electrical potential is applied across a selected memory-diode, from higher to lower potential in the forward direction, intended to program the selected memory-diode. During this intended programming, each other memory-diode in the array has provided thereacross in the forward direction thereof an electrical potential lower than its threshold voltage. The threshold voltage of each memory-diode can be established by applying an electrical potential across that memory-diode from higher to lower potential in the reverse direction. By so establishing a sufficient threshold voltage, and by selecting appropriate electrical potentials applied to conductors of the array, problems related to current leakage and disturb are avoided.
摘要翻译：存储器阵列包括第一和第二组导体和多个存储器二极管，每个存储器二极管以正向方向连接第一组的导体与第二组的导体。在选定的存储器二极管上施加电位，从正向上的较高电位到较低的电位，用于对所选存储二极管进行编程。在该期望的编程期间，阵列中的每个其它存储器二极管在其正向方向上提供低于其阈值电压的电位。每个存储器二极管的阈值电压可以通过在该存储器二极管上从相反方向上从较高电位向较低电位施加电位来建立。通过这样建立足够的阈值电压，并且通过选择适用于阵列导体的适当电位，避免了与电流泄漏和干扰有关的问题。

7. 发明授权

US07286388B1 Resistive memory device with improved data retention 有权
标题翻译：具有改善数据保持性的电阻式存储器件
公开(公告)号：US07286388B1
公开(公告)日：2007-10-23
申请号：US11165005
申请日：2005-06-23
申请人： An Chen , Sameer Haddad , Tzu-Ning Fang , Yi-Ching Jean Wu , Colin S. Bill
发明人： An Chen , Sameer Haddad , Tzu-Ning Fang , Yi-Ching Jean Wu , Colin S. Bill
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/02 , G11C2013/009 , G11C2213/11 , G11C2213/56 , G11C2213/79
摘要： In the present method of programming a memory device from an erased state, the memory device includes first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second electrodes. In the programming method, (i) an electrical potential is applied across the first and second electrodes from higher to lower potential in one direction to reduce the resistance of the memory device, and (ii) an electrical potential is applied across the first and second electrodes from higher to lower potential in the other direction to further reduce the resistance of the memory device.
摘要翻译：在从擦除状态编程存储器件的本方法中，存储器件包括第一和第二电极，第一和第二电极之间的无源层以及第一和第二电极之间的有源层。在编程方法中，（i）在一个方向上跨越第一和第二电极施加电位从较高电位到较低的电位，以减小存储器件的电阻，并且（ii）电势跨越第一和第二电极在另一个方向从较高电位变为较低电位，以进一步降低存储器件的电阻。

8. 发明授权

US08098521B2 Method of providing an erase activation energy of a memory device 有权
标题翻译：提供存储器件的擦除激活能的方法
公开(公告)号：US08098521B2
公开(公告)日：2012-01-17
申请号：US11095849
申请日：2005-03-31
申请人： Michael A. VanBuskirk , Colin S. Bill , Zhida Lan , Tzu-Ning Fang
发明人： Michael A. VanBuskirk , Colin S. Bill , Zhida Lan , Tzu-Ning Fang
IPC分类号： G11C11/34
CPC分类号： G11C13/0014 , B82Y10/00
摘要： A write-once read-many times memory device is made up of first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second electrode. The memory device is programmed by providing a charged species from the passive layer into the active layer. The memory device may be programmed to have for the programmed memory device a first erase activation energy. The present method provides for the programmed memory device a second erase activation energy greater than the first erase activation energy.
摘要翻译：一次写入多次存储器件由第一和第二电极，第一和第二电极之间的无源层以及第一和第二电极之间的有源层组成。通过从被动层提供带电物质到活性层来对存储器件进行编程。存储器件可以被编程为使编程的存储器件具有第一擦除激活能量。本方法为编程的存储器件提供大于第一擦除激活能量的第二擦除激活能量。

9. 发明授权

US07035141B1 Diode array architecture for addressing nanoscale resistive memory arrays 有权
标题翻译：用于寻址纳米尺度电阻式存储器阵列的二极管阵列架构
公开(公告)号：US07035141B1
公开(公告)日：2006-04-25
申请号：US10990706
申请日：2004-11-17
申请人： Nicholas H. Tripsas , Colin S. Bill , Michael A. VanBuskirk , Matthew Buynoski , Tzu-Ning Fang , Wei Daisy Cai , Suzette Pangrle , Steven Avanzino
发明人： Nicholas H. Tripsas , Colin S. Bill , Michael A. VanBuskirk , Matthew Buynoski , Tzu-Ning Fang , Wei Daisy Cai , Suzette Pangrle , Steven Avanzino
IPC分类号： G11C11/36 , G11C27/00
CPC分类号： G11C13/003 , G11C13/0002 , G11C13/0007 , G11C2213/56 , G11C2213/72 , G11C2213/74 , G11C2213/76 , H01L27/101 , H01L27/1021
摘要： The present memory structure includes thereof a first conductor, a second conductor, a resistive memory cell connected to the second conductor, a first diode connected to the resistive memory cell and the first conductor, and oriented in the forward direction from the resistive memory cell to the first conductor, and a second diode connected to the resistive memory cell and the first conductor, in parallel with the first diode, and oriented in the reverse direction from the resistive memory cell to the first conductor. The first and second diodes have different threshold voltages.
摘要翻译：本存储器结构包括第一导体，第二导体，连接到第二导体的电阻性存储单元，连接到电阻存储单元和第一导体的第一二极管，并且从电阻存储单元向前取向所述第一导体和连接到所述电阻性存储器单元和所述第一导体的第二二极管与所述第一二极管并联，并且在从所述电阻存储器单元到所述第一导体的相反方向上定向。第一和第二二极管具有不同的阈值电压。

10. 发明授权

US07579631B2 Variable breakdown characteristic diode 有权
标题翻译：可变击穿特性二极管
公开(公告)号：US07579631B2
公开(公告)日：2009-08-25
申请号：US11087000
申请日：2005-03-22
申请人： David Gaun , Colin S. Bill , Swaroop Kaza
发明人： David Gaun , Colin S. Bill , Swaroop Kaza
IPC分类号： H01L29/00
CPC分类号： H01L51/0575 , B82Y10/00 , G11C11/5664 , G11C11/5692 , G11C13/0009 , G11C13/0014 , G11C13/0016 , G11C2213/11 , G11C2213/12 , G11C2213/15 , G11C2213/56 , G11C2213/71 , G11C2213/77 , H01L27/285
摘要： A memory cell made of at least two electrodes with a controllably conductive media between the at least two electrodes is disclosed. The controllably conductive media includes a passive layer made of super ionic material and an active layer. When an external stimuli, such as an applied electric field, is imposed upon the first and second electrode, ions move and dope and/or de-dope the polymer. The applied external stimuli used to dope the polymer is larger than an applied external stimuli to operate the memory cell. The polymer functions as a variable breakdown characteristic diode with electrical characteristics which are a consequence of the doping degree. The memory element may have a current limited read signal. Methods of making the memory devices/cells, methods of using the memory devices/cells, and devices such as computers, hand-held electronic devices and memory devices containing the memory cell(s) are also disclosed.
摘要翻译：公开了一种由在至少两个电极之间具有可控导电介质的至少两个电极制成的存储单元。可控导电介质包括由超离子材料和有源层制成的钝化层。当诸如施加的电场的外部刺激施加在第一和第二电极上时，离子移动并掺杂和/或去透明聚合物。用于掺杂聚合物的应用外部刺激物大于施加的外部刺激以操作记忆单元。该聚合物用作具有电特性的可变击穿特性二极管，这是掺杂度的结果。存储元件可以具有电流受限读取信号。还公开了制造存储器件/单元的方法，使用存储器件/单元的方法，以及诸如计算机，手持式电子设备和包含存储单元的存储器件的设备。

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