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1. 发明授权

US06496417B1 Method and integrated circuit for bit line soft programming (BLISP) 有权
标题翻译：位线软编程方法与集成电路（BLISP）
公开(公告)号：US06496417B1
公开(公告)日：2002-12-17
申请号：US09601089
申请日：2000-07-27
申请人： Tzeng-Huei Shiau , Ray-Lin Wan , Han Sung Chen , Yu-Shen Lin , Wen-Pin Lu , Tso-Ming Chang
发明人： Tzeng-Huei Shiau , Ray-Lin Wan , Han Sung Chen , Yu-Shen Lin , Wen-Pin Lu , Tso-Ming Chang
IPC分类号： G11C1604
CPC分类号： G11C16/107 , G11C16/3404 , G11C16/3409 , G11C16/3413 , G11C16/3445
摘要： A method and an integrated circuit for performing a soft program after erase provides efficient convergence of over-erased floating gate memory cells disposed in bit lines. The soft program is applied to successive subject bit lines. The BLISP method includes selection of a selected bit line and applying the soft program to a subject bit line corresponding to the selected bit line. For integrated circuits having no defective bit lines, the subject bit lines comprise the selected bit lines. The BLISP method is adapted for low current consumption compared to bulk soft programming methods. In some embodiments, the integrated circuit includes defective bit lines. For these integrated circuits, the selection of the selected bit line includes indicating a bit line type corresponding to the selected bit line. The defective bit lines are logically replaced by redundant bit lines so that the soft program is applied to conforming selected bit lines and redundant bit lines corresponding to defective bit lines. The defective bit lines in the first memory array can be disabled during the soft program and replaced by corresponding redundant bit lines disposed in the second memory array, so that the soft program is not applied to the defective bit lines. By preventing application of the soft program to the defective bit lines, the BLISP method avoids consumption of excessive current that would otherwise be consumed by very low threshold voltage memory cells disposed on the defective bit lines. The excessive current would render the soft program method much less efficient.
摘要翻译：用于在擦除之后执行软程序的方法和集成电路提供了布置在位线中的过擦除的浮动栅极存储单元的有效收敛。软程序应用于连续的主题位线。 BLISP方法包括选择所选位线并将软程序应用于对应于所选位线的对象位线。对于没有有缺陷的位线的集成电路，主题位线包括所选择的位线。与批量软编程方法相比，BLISP方法适用于低电流消耗。在一些实施例中，集成电路包括有缺陷的位线。对于这些集成电路，选择的位线的选择包括指示对应于所选位线的位线类型。有缺陷的位线在逻辑上被冗余位线替代，使得软程序被应用于对应于有缺陷位线的选定位线和冗余位线。可以在软程序期间禁用第一存储器阵列中的有缺陷的位线，并且由位于第二存储器阵列中的对应的冗余位线替换第一存储器阵列中的有缺陷的位线，使得软程序不被施加到有缺陷的位线。通过防止将软程序应用于有缺陷的位线，BLISP方法避免消耗过剩的电流，否则会由设置在有缺陷位线上的非常低的阈值电压存储单元消耗。过度的电流将使软程序方法效率低得多。

2. 发明授权

US06229732B1 Regulated voltage supply circuit for inducing tunneling current in floating gate memory devices 有权
标题翻译：用于在浮动栅极存储器件中感应隧道电流的稳压电源电路
公开(公告)号：US06229732B1
公开(公告)日：2001-05-08
申请号：US09380873
申请日：1999-09-09
申请人： Yu-Shen Lin , Tzeng-Huei Shiau , Ray-Lin Wan
发明人： Yu-Shen Lin , Tzeng-Huei Shiau , Ray-Lin Wan
IPC分类号： G11C1604
CPC分类号： G11C5/147 , G11C16/12 , G11C16/30
摘要： A circuit is provided for applying a negative voltage to the control gate of a floating gate memory cell and a positive voltage to the source drain or channel which comprises a positive voltage source to provide a positive voltage to the source of the cell, and a negative voltage source responsive to the supply voltage to provide a negative voltage to the control gate. A voltage regulator is included that is coupled to the negative voltage source and to the positive voltage source to maintain the negative voltage at a level responsive to the source voltage. The regulator maintains the negative voltage in response to the source voltage so that the electric field remains essentially constant over a range of values of source voltage.
摘要翻译：提供电路用于向浮动栅极存储单元的控制栅极施加负电压，并向源极漏极或沟道施加正电压，该正电压包括正电压源以向电池源提供正电压，负电压电压源响应于电源电压以向控制栅极提供负电压。包括耦合到负电压源和正电压源的电压调节器，以将负电压保持在响应于电源电压的电平。调节器响应于源极电压维持负电压，使得电源在源极电压值的范围内基本保持恒定。

3. 发明授权

US5966331A Block decoded wordline driver with positive and negative voltage modes using four terminal MOS transistors 失效
标题翻译：使用四端MOS晶体管对正负电压模式进行块解码字线驱动
公开(公告)号：US5966331A
公开(公告)日：1999-10-12
申请号：US122258
申请日：1998-07-24
申请人： Tzeng-Huei Shiau , Yu-Shen Lin , Ray-Lin Wan
发明人： Tzeng-Huei Shiau , Yu-Shen Lin , Ray-Lin Wan
IPC分类号： G11C16/16 , G11C16/04 , G11C16/06
CPC分类号： G11C16/16
摘要： The negative supply voltage and isolation well bias used by the drivers during sector or chip level erase operations are decoded separately from each other and from the decoding of the inputs of the individual wordline drivers in a compact wordline driver and decoder system. An integrated circuit memory comprising an array of memory cells arranged in a plurality of segments, a set of wordlines is coupled to the memory cells in the array, and wordline driver circuitry using shared isolation well MOS transistors coupled to the set of wordlines is provided. The wordline driver circuitry includes a first supply voltage source, a second supply voltage source, a third supply voltage source for the shared isolation well and a set of wordline drivers. The wordline drivers are coupled to the first, second and third supply voltage sources, and selectively drive wordlines in the set of wordlines with a wordline voltage from either the first supply voltage source or the second supply voltage source in response to address signals which identify the respective drivers. The second supply voltage source includes a set of supply voltage selectors. Each supply voltage selector in the set is coupled with a subset of the set of drivers. The subset of drivers is coupled with a respective segment in the array. The supply voltage selectors select a negative erase supply voltage or an erase inhibit supply voltage during an erase mode in response to address signals identifying the respective segments. The selected negative erase supply voltage or erase inhibit supply voltage is applied to the subsets of the set of drivers which are coupled to the respective segment on a segment by segment basis.
摘要翻译：在扇区或芯片级擦除操作期间由驱动器使用的负电源电压和隔离阱偏压彼此分开解码，并且在紧凑的字线驱动器和解码器系统中对各个字线驱动器的输入进行解码。一种集成电路存储器，包括布置在多个段中的存储单元的阵列，一组字线耦合到该阵列中的存储单元，并且提供了使用共享隔离阱MOS晶体管的字线驱动器电路，耦合到该组字线。字线驱动器电路包括第一电源电压源，第二电源电压源，用于共用隔离阱的第三电源电压源和一组字线驱动器。字线驱动器耦合到第一，第二和第三电源电压源，并且响应于识别第一，第二和第三电源电压源的地址信号，用来自第一电源电压源或第二电源电压源的字线电压选择性地驱动字线组中的字线各自的司机。第二电源电压源包括一组电源电压选择器。该组中的每个电源电压选择器与该组驱动器的子集耦合。驱动器的子集与阵列中的相应段耦合。电源电压选择器响应于识别相应段的地址信号，在擦除模式期间选择负擦除电源电压或擦除禁止电源电压。所选择的否定擦除电源电压或擦除禁止电源电压被施加到该组驱动器的子集，该组被分段地连接到相应的段。

4. 发明授权

US6021083A Block decoded wordline driver with positive and negative voltage modes 失效
标题翻译：使用正负电压模式的块解码字线驱动器
公开(公告)号：US6021083A
公开(公告)日：2000-02-01
申请号：US051005
申请日：1998-03-30
申请人： Tzeng-Huei Shiau , Yu-Shen Lin , Ray-Lin Wan
发明人： Tzeng-Huei Shiau , Yu-Shen Lin , Ray-Lin Wan
IPC分类号： G11C8/08 , G11C16/08 , G11C13/00
CPC分类号： G11C8/08 , G11C16/08
摘要： The negative supply voltage used by the drivers during sector or chip level erase operations is decoded separately from the decoding of the inputs of the individual wordline drivers in a compact wordline driver and decoder system. An integrated circuit memory comprising an array of memory cells arranged in a plurality of segments, a set of wordlines is coupled to the memory cells in the array, and wordline driver circuitry coupled to the set of wordlines is provided. The wordline driver circuitry includes a first supply voltage source, a second supply voltage source, and a set of wordline drivers. The wordline drivers are coupled to the first and second supply voltage sources, and selectively drive wordlines in the set of wordlines with a wordline voltage from either the first supply voltage source or the second supply voltage source in response to address signals which identify the respective drivers. The second supply voltage source includes a set of supply voltage selectors. Each supply voltage selector in the set is coupled with a subset of the set of drivers. The subset of drivers is coupled with a respective segment in the array. The supply voltage selectors select a negative erase supply voltage or an erase inhibit supply voltage during an erase mode in response to address signals identifying the respective segments. The selected negative erase supply voltage or erase inhibit supply voltage is applied to the subsets of the set of drivers which are coupled to the respective segment on a segment by segment basis.
摘要翻译： PCT No.PCT / US97 / 22102 Sec。 371日期1998年3月30日 102（e）1998年3月30日PCT 1997年12月5日PCT公布。出版物WO99 / 30326 日期1999年6月17日在扇区或芯片级擦除操作期间由驱动器使用的负电源电压与紧凑型字线驱动器和解码器系统中的单个字线驱动器的输入的解码分开解码。一种集成电路存储器，包括布置在多个段中的存储器单元的阵列，一组字线耦合到阵列中的存储器单元，并且提供耦合到该组字线的字线驱动器电路。字线驱动器电路包括第一电源电压源，第二电源电压源和一组字线驱动器。字线驱动器耦合到第一和第二电源电压源，并且响应于识别相应驱动器的地址信号，用来自第一电源电压源或第二电源电压源的字线电压选择性地驱动字线组中的字线。第二电源电压源包括一组电源电压选择器。该组中的每个电源电压选择器与该组驱动器的子集耦合。驱动器的子集与阵列中的相应段耦合。电源电压选择器响应于识别相应段的地址信号，在擦除模式期间选择负擦除电源电压或擦除禁止电源电压。所选择的否定擦除电源电压或擦除禁止电源电压被施加到该组驱动器的子集，该组被分段地连接到相应的段。

5. 发明授权

US05999455A Channel FN program/erase recovery scheme 有权
标题翻译：通道FN程序/擦除恢复方案
公开(公告)号：US05999455A
公开(公告)日：1999-12-07
申请号：US162108
申请日：1998-09-28
申请人： Yu-Shen Lin , Tzeng-Huei Shiau , Ray-Lin Wan
发明人： Yu-Shen Lin , Tzeng-Huei Shiau , Ray-Lin Wan
IPC分类号： G11C16/00 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/34
CPC分类号： G11C16/3413 , G11C16/3404 , G11C16/3409
摘要： A recovery circuit for recovering the control gate and the channel well of a floating gate memory cell to a first recovery potential and a second recovery potential respectively after a program or erase process has been performed on the cell is provided. The floating gate memory cell may include the control gate coupled to a first node at a first program/erase potential, a floating gate, the channel well coupled to a second node at a second program/erase potential having a first conductivity type, and drain and source regions within the channel well having a second conductivity type different from the first. The recovery circuit includes control circuitry that provides a recovery control signal indicating when the program or erase process has been completed, and a coupling circuit that connects the control gate to the channel well in response to the recovery control signal. The recovery circuit further includes first and second voltage detectors that generate first and second grounding signals when the control gate and channel well voltages reach a first and second switching voltage respectively. The first and second grounding signals are provided to first and second voltage grounding circuits that bias the control gate and the channel well to the first and second recovery potentials respectively in response to the grounding signals. In one embodiment the first and second recovery potentials are connected to a node at ground potential, and in another embodiment the first conductivity type is p-type. In a further embodiment the floating gate memory cell is a triple well transistor, the channel well of which is within an isolation well on the substrate of an integrated circuit.
摘要翻译：提供了一种恢复电路，用于在对单元进行编程或擦除处理之后，分别将浮动栅极存储单元的控制栅极和沟道阱恢复到第一恢复电位和第二恢复电位。浮动栅极存储单元可以包括以第一编程/擦除电位耦合到第一节点的控制栅极，浮置栅极，在具有第一导电类型的第二编程/擦除电位下良好地耦合到第二节点的沟道，以及漏极以及通道井内的源极区具有不同于第一导电类型的第二导电类型。恢复电路包括控制电路，其提供指示编程或擦除过程何时完成的恢复控制信号，以及响应于恢复控制信号将控制门连接到信道的耦合电路。恢复电路还包括当控制栅极和沟道阱电压分别达到第一和第二开关电压时产生第一和第二接地信号的第一和第二电压检测器。第一和第二接地信号被提供给分别响应于接地信号而将控制栅极和沟道良好地偏置到第一和第二恢复电位的第一和第二电压接地电路。在一个实施例中，第一和第二恢复电位连接到地电位的节点，在另一个实施例中，第一导电类型是p型。在另一个实施例中，浮动栅极存储单元是三阱阱晶体管，其沟道阱位于集成电路的衬底上的隔离阱内。

6. 发明授权

US5787039A Low current floating gate programming with bit-by-bit verification 失效
标题翻译：低电流浮栅编程与逐位验证
公开(公告)号：US5787039A
公开(公告)日：1998-07-28
申请号：US812615
申请日：1997-03-06
申请人： Han-Sung Chen , Tzeng-Huei Shiau , Yu-Shen Lin , Chung-Cheng Tsai , Jin-Lien Lin , Ray Lin Wan , Yuan-Chang Liu , Chun Hsiung Hung
发明人： Han-Sung Chen , Tzeng-Huei Shiau , Yu-Shen Lin , Chung-Cheng Tsai , Jin-Lien Lin , Ray Lin Wan , Yuan-Chang Liu , Chun Hsiung Hung
IPC分类号： G11C16/10 , G11C16/34 , G11C16/06
CPC分类号： G11C16/3486 , G11C16/10 , G11C16/3459 , G11C16/3468
摘要： A system for programming arrays of floating gate memory cells reduces programming current requirements, and reduces wordline and bitline stress during programming. A word-to-be-programmed into a floating gate memory array is divided into a plurality of smaller subwords. Only one subword is programmed at a time, thereby reducing programming current requirements. Additionally, subwords which are successfully programmed are not reprogrammed even if bits in other subwords do not program properly. This creates less wordline stress than previous systems which program an entire word at once, thereby requiring subwords which program successfully to be reprogrammed along with subwords which fail to program. Finally, within each subword only those bits which failed to program are reprogrammed, thereby reducing bitline stress during reprogramming for those bits which were successfully programmed.
摘要翻译：用于编程浮动栅极存储器单元阵列的系统减少了编程电流要求，并且减少了编程期间的字线和位线应力。要被编程到浮动存储器阵列中的字被分成多个较小的子字。一次只编写一个子字，从而减少编程电流的要求。此外，即使其他子词的位未正确编程，成功编程的子词也不会被重新编程。这与以前系统一样编制整个单词的系统产生较少的字面压力，从而要求程序成功地重新编程的子词以及不能编程的子词。最后，在每个子字中，只有那些无法编程的位被重新编程，从而在对已成功编程的那些位的重新编程期间减少位线应力。

7. 发明授权

US6119226A Memory supporting multiple address protocols 失效
标题翻译：内存支持多个地址协议
公开(公告)号：US6119226A
公开(公告)日：2000-09-12
申请号：US76693
申请日：1998-05-12
申请人： Tzeng-Huei Shiau , Han-Sung Chen , Tso-Ming Chang , Ray Lin Wan , Fuchia Shone
发明人： Tzeng-Huei Shiau , Han-Sung Chen , Tso-Ming Chang , Ray Lin Wan , Fuchia Shone
IPC分类号： G06F9/445 , G11C8/00 , G11C16/08 , G11C16/10
CPC分类号： G06F9/4403 , G11C16/08 , G11C16/10 , G11C8/00
摘要： The present invention provides a new memory device for storage of boot code for microprocessors which boot to either the top or bottom of a memory map on power-up. The device includes a memory array, a first block, and decoders. The first block is defined as rows of the memory array designated for storage of data. The decoders decode a memory access requested for the data. The memory access request may be in either one of a top-down or bottom-up address protocol. In another embodiment, an integrated circuit memory includes: a memory array, a decoder, a control, and a logic gate. The decoders decode a memory access request to select a row of memory array. The control has an output for outputting either a bottom-up or a top-down address protocol signal. The logic gate outputs a logical "Exclusive Or" of the control signal and a corresponding bit of the memory access request, whereby a memory request in a bottom-up address protocol is converted to a memory address in a top-down address protocol.
摘要翻译：本发明提供了一种用于存储用于微处理器的引导代码的新存储器装置，其在上电时被引导到存储器映射图的顶部或底部。该设备包括存储器阵列，第一块和解码器。第一个块被定义为指定用于存储数据的存储器阵列的行。解码器解码为数据请求的存储器访问。存储器访问请求可以是自顶向下或自下而上的地址协议中的任一个。在另一个实施例中，集成电路存储器包括：存储器阵列，解码器，控制和逻辑门。解码器解码存储器访问请求以选择一行存储器阵列。该控制具有用于输出自下而上或自上而下的地址协议信号的输出。逻辑门输出控制信号的逻辑“异或”和存储器访问请求的相应位，由此自下而上地址协议中的存储器请求被转换成自顶向下地址协议中的存储器地址。

8. 发明授权

US5818764A Block-level wordline enablement to reduce negative wordline stress 失效
标题翻译：块级字词启用以减少负面字线压力
公开(公告)号：US5818764A
公开(公告)日：1998-10-06
申请号：US796821
申请日：1997-02-06
申请人： Tom D. Yiu , I-Long Lee , Kuen-Long Chang , Han-Sung Chen , Tzeng-Huei Shiau , Chun-Hsiung Hung , Ray-Lin Wan
发明人： Tom D. Yiu , I-Long Lee , Kuen-Long Chang , Han-Sung Chen , Tzeng-Huei Shiau , Chun-Hsiung Hung , Ray-Lin Wan
IPC分类号： G11C8/08 , G11C16/08 , G11C16/16 , G11C16/00
CPC分类号： G11C8/08 , G11C16/08 , G11C16/16
摘要： A circuit is provided for supplying a negative erasing voltage onto the wordlines of selected blocks in an array of floating gate memory cells. The circuit includes a voltage circuit, which has a plurality of local outputs, each of which connects to wordlines of an associated block of floating gate memory cells. A block selector circuit is coupled to the local outputs of the voltage circuit and selectively switches each of the local outputs to apply either an erasing voltage or a non-erasing voltage onto the wordlines of the associated block of floating gate memory cells. Negative wordline stress is thus reduced for wordlines of unselected blocks which receive a less negative, non-erasing voltage during block erase operations.
摘要翻译：提供电路，用于向浮动栅极存储单元阵列中的选定块的字线提供负的擦除电压。该电路包括具有多个本地输出的电压电路，每个本地输出连接到浮动栅极存储器单元的相关块的字线。块选择器电路耦合到电压电路的本地输出，并且选择性地切换每个本地输出以将擦除电压或非擦除电压施加到浮动栅极存储器单元的相关联块的字线上。因此，对于在块擦除操作期间接收到较小负的非擦除电压的未选择块的字线，负字线应力减小。

9. 发明授权

US6084446A Power on reset circuit 失效
标题翻译：上电复位电路
公开(公告)号：US6084446A
公开(公告)日：2000-07-04
申请号：US101679
申请日：1998-06-12
申请人： Han-Sung Chen , Tzeng-Huei Shiau , Ray-Lin Wan
发明人： Han-Sung Chen , Tzeng-Huei Shiau , Ray-Lin Wan
IPC分类号： H03K3/356 , H03K17/22
CPC分类号： H03K17/223 , H03K3/356008
摘要： A circuit generates a power on reset signal in response to the changing of a supply potential across a supply node and a reference node from a power down level to a power on level. The circuit comprises a capacitor having a first terminal coupled to the supply node and a second terminal. An output driver, such as an inverter, is coupled between the supply node and the reference node. The output driver has an output coupled to the second terminal of the capacitor. An input driver comprises a circuit which drives the input of the output driver to a level which tracks changes in the supply potential. A clamp transistor, such as a n-channel MOS transistor having a lower threshold than normal transistors in the circuit, is coupled between the input of the output driver and the supply potential. The clamp transistor clamps the input of the output driver to a driver ready level which is below the trip point of the output driver when the supply potential is at a power down level. In addition, a feedback transistor is included, which has a gate coupled to the output of the output driver, a drain coupled to the input of the output driver, and a source coupled to the supply node. The feedback transistor pulls the input of the output driver to a driver off level above the trip point of the output driver.
摘要翻译： PCT No.PCT / US98 / 06255 Sec。 371日期：1998年6月12日 102（e）1998年6月12日PCT 1998年3月30日PCT PCT。公开号WO99 / 50962 日期1999年10月7日电路响应于供电节点和参考节点从断电电平变为上电电平的电源电位而产生上电复位信号。电路包括具有耦合到电源节点的第一端子和第二端子的电容器。诸如逆变器的输出驱动器耦合在供电节点和参考节点之间。输出驱动器具有耦合到电容器的第二端子的输出。输入驱动器包括将输出驱动器的输入驱动到跟踪电源电位变化的电平的电路。钳位晶体管，例如具有比电路中的正常晶体管低的阈值的n沟道MOS晶体管，耦合在输出驱动器的输入端和电源电位之间。当供电电位处于断电电平时，钳位晶体管将输出驱动器的输入钳位到驱动器就绪电平，该电平低于输出驱动器的跳变点。此外，包括反馈晶体管，其具有耦合到输出驱动器的输出的栅极，耦合到输出驱动器的输入的漏极和耦合到电源节点的源极。反馈晶体管将输出驱动器的输入端拉至高于输出驱动器跳变点的驱动器。

10. 发明授权

US5963476A Fowler-Nordheim (F-N) tunneling for pre-programming in a floating gate memory device 失效
标题翻译： Fowler-Nordheim（F-N）隧道，用于在浮动栅极存储器件中进行预编程
公开(公告)号：US5963476A
公开(公告)日：1999-10-05
申请号：US975516
申请日：1997-11-12
申请人： Chun Hsiung Hung , Tzeng-Huei Shiau , Yao-Wu Cheng , I-Long Lee , Fuchia Shone , Ray-Lin Wan
发明人： Chun Hsiung Hung , Tzeng-Huei Shiau , Yao-Wu Cheng , I-Long Lee , Fuchia Shone , Ray-Lin Wan
IPC分类号： G11C16/02 , G11C16/04 , G11C16/16 , G11C16/34 , H01L27/115 , G11C16/06
CPC分类号： G11C16/107 , G11C16/0416 , G11C16/16 , G11C16/3454 , G11C16/3459 , H01L27/115
摘要： A new flash memory cell structure and operational bias is based on the use of a triple well flash memory cell which allows pre-programming by Fowler Nordheim (F-N) tunneling over blocks of cells at a time. The floating gate memory cell is made in a semiconductor substrate having a first conductivity type, such as p-type. A first well within the substrate by having a second conductivity type different than the first conductivity type is included. A second well within the first well is also included having the first conductivity type. A drain and a source are formed in the second well having the second conductivity type, and spaced away from one another to define a channel area between the drain and the source. A floating gate and control gate structure is included over the channel area. The floating gate memory cell is coupled with circuits that induce F-N tunneling of electrons out of the floating gate into the channel area of the substrate for erasing by applying a positive voltage to the second well, such as a voltage higher than the supply voltage, applying a positive voltage to the first well, which is substantially equal to the positive voltage of the second well, applying a negative voltage to the control gate of the cell, while the substrate is grounded. A block wide pre-program operation involves F-N tunneling of electrons into the floating gate from the channel area, using a negative voltage in the second well.
摘要翻译：新的闪存单元结构和操作偏置是基于使用三阱闪存单元，其允许Fowler Nordheim（F-N）一次在单元格块上进行预编程。浮栅存储单元由具有第一导电类型的半导体衬底制成，例如p型。包括具有不同于第一导电类型的第二导电类型的衬底内的第一阱。还包括第一阱中的第二阱具有第一导电类型。在具有第二导电类型的第二阱中形成漏极和源极，并且彼此间隔开以限定漏极和源极之间的沟道区域。通道区域中包括浮动栅极和控制栅极结构。浮动栅极存储单元与电路耦合，该电路通过向第二阱施加正电压，例如高于电源电压的电压，施加电压，使电子从浮动栅极进入隧道区域进入衬底的通道区域以进行擦除与第一阱的正电压相比，其基本上等于第二阱的正电压，而在衬底接地时，向电池的控制栅极施加负电压。块宽的预编程操作涉及使用第二阱中的负电压将电子从沟道区域F-N隧穿到浮置栅极。

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