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1. 发明授权

US07101746B2 Method to lower work function of gate electrode through Ge implantation 有权
标题翻译：通过Ge注入来降低栅电极的功函数的方法
公开(公告)号：US07101746B2
公开(公告)日：2006-09-05
申请号：US10701963
申请日：2003-11-05
申请人： Tze Ho Simon Chan , Mousumi Bhat , Jeffrey Chee
发明人： Tze Ho Simon Chan , Mousumi Bhat , Jeffrey Chee
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823842 , H01L21/32155 , H01L21/82385
摘要： A method for forming selective P type and N type gates is described. A gate oxide layer is grown overlying a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. Germanium ions are implanted into a portion of the polysilicon layer not covered by a mask to form a polysilicon-germanium layer. The polysilicon layer and the polysilicon-germanium layer are patterned to form NMOS polysilicon gates and PMOS polysilicon-germanium gates. In an alternative, nitrogen ions are implanted into the polysilicon-germanium layer and the gates are annealed after patterning to redistribute the germanium ions throughout the polysilicon-germanium layer. In a second alternative, germanium ions are implanted into a first thin polysilicon layer, then a second polysilicon layer is deposited to achieve the total polysilicon layer thickness before patterning the gates.
摘要翻译：描述了形成选择性P型和N型栅极的方法。生长在半导体衬底上的栅氧化层。沉积在栅极氧化物层上的多晶硅层。将锗离子注入到未被掩模覆盖的多晶硅层的一部分中以形成多晶硅 - 锗层。图案化多晶硅层和多晶硅 - 锗层以形成NMOS多晶硅栅极和PMOS多晶硅 - 锗栅极。替代地，将氮离子注入到多晶硅 - 锗层中，并且在图案化之后对栅极进行退火以将锗离子重新分布在整个多晶硅 - 锗层中。在第二替代方案中，将锗离子注入到第一薄多晶硅层中，然后沉积第二多晶硅层以在栅极图案化之前实现总多晶硅层厚度。

2. 发明申请

US20060205138A1 Method to selectively form SiGe P type electrode and polysilicon N type electrode through planarization 审中-公开
标题翻译：通过平面化选择性地形成SiGe P型电极和多晶N型电极的方法
公开(公告)号：US20060205138A1
公开(公告)日：2006-09-14
申请号：US11079731
申请日：2005-03-14
申请人： Tze Chan , Mousumi Bhat , Jeffrey Chee
发明人： Tze Chan , Mousumi Bhat , Jeffrey Chee
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/823425
摘要： A method for forming selective P type and N type gates is described. A first gate oxide layer is grown overlying a semiconductor substrate. A polysilicon layer is deposited overlying the first gate oxide layer. The polysilicon layer is patterned to form first NMOS gates. A second gate oxide layer is grown overlying the substrate. A polysilicon-germanium layer is deposited overlying the second gate oxide layer and the first gates. The polysilicon-germanium layer and first gates are planarized to a uniform thickness. The polysilicon first gates and the polysilicon-germanium layer are patterned to form second NMOS polysilicon gates and PMOS polysilicon-germanium gates.
摘要翻译：描述了形成选择性P型和N型栅极的方法。生长在半导体衬底上的第一栅极氧化物层。堆叠覆盖第一栅极氧化物层的多晶硅层。图案化多晶硅层以形成第一NMOS栅极。在衬底上生长第二栅极氧化物层。沉积覆盖第二栅极氧化物层和第一栅极的多晶硅 - 锗层。将多晶硅锗层和第一栅极平坦化成均匀的厚度。图案化多晶硅第一栅极和多晶硅 - 锗层以形成第二NMOS多晶硅栅极和PMOS多晶硅 - 锗栅极。

3. 发明申请

US20050095773A1 Method to lower work function of gate electrode through Ge implantation 有权
标题翻译：通过Ge注入来降低栅电极的功函数的方法
公开(公告)号：US20050095773A1
公开(公告)日：2005-05-05
申请号：US10701963
申请日：2003-11-05
申请人： Tze Ho Chan , Mousumi Bhat , Jeffrey Chee
发明人： Tze Ho Chan , Mousumi Bhat , Jeffrey Chee
IPC分类号： H01L21/3215 , H01L21/8238 , H01R4/64 , H01L21/302 , H01L21/461 , H01R4/60
CPC分类号： H01L21/823842 , H01L21/32155 , H01L21/82385
摘要： A method for forming selective P type and N type gates is described. A gate oxide layer is grown overlying a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. Germanium ions are implanted into a portion of the polysilicon layer not covered by a mask to form a polysilicon-germanium layer. The polysilicon layer and the polysilicon-germanium layer are patterned to form NMOS polysilicon gates and PMOS polysilicon-germanium gates. In an alternative, nitrogen ions are implanted into the polysilicon-germanium layer and the gates are annealed after patterning to redistribute the germanium ions throughout the polysilicon-germanium layer. In a second alternative, germanium ions are implanted into a first thin polysilicon layer, then a second polysilicon layer is deposited to achieve the total polysilicon layer thickness before patterning the gates.
摘要翻译：描述了形成选择性P型和N型栅极的方法。生长在半导体衬底上的栅氧化层。沉积在栅极氧化物层上的多晶硅层。将锗离子注入到未被掩模覆盖的多晶硅层的一部分中以形成多晶硅 - 锗层。图案化多晶硅层和多晶硅 - 锗层以形成NMOS多晶硅栅极和PMOS多晶硅 - 锗栅极。替代地，将氮离子注入到多晶硅 - 锗层中，并且在图案化之后对栅极进行退火以将锗离子重新分布在整个多晶硅 - 锗层中。在第二替代方案中，将锗离子注入到第一薄多晶硅层中，然后沉积第二多晶硅层以在栅极图案化之前实现总多晶硅层厚度。

4. 发明授权

US06872608B1 Method to selectively form poly SiGe P type electrode and polysilicon N type electrode through planarization 失效
标题翻译：通过平面化选择性地形成多晶SiGe P型电极和多晶N型电极的方法
公开(公告)号：US06872608B1
公开(公告)日：2005-03-29
申请号：US10697746
申请日：2003-10-30
申请人： Tze Ho Chan , Mousumi Bhat , Jeffrey Chee
发明人： Tze Ho Chan , Mousumi Bhat , Jeffrey Chee
IPC分类号： H01L21/28 , H01L21/8238 , H01L21/338 , H01L21/00 , H01L21/84
CPC分类号： H01L21/823842 , H01L21/2807
摘要： A method for forming selective P type and N type gates is described. A first gate oxide layer is grown overlying a semiconductor substrate. A polysilicon layer is deposited overlying the first gate oxide layer. The polysilicon layer is patterned to form first NMOS gates. A second gate oxide layer is grown overlying the substrate. A polysilicon-germanium layer is deposited overlying the second gate oxide layer and the first gates. The polysilicon-germanium layer and first gates are planarized to a uniform thickness. The polysilicon first gates and the polysilicon-germanium layer are patterned to form second NMOS polysilicon gates and PMOS polysilicon-germanium gates.
摘要翻译：描述了形成选择性P型和N型栅极的方法。生长在半导体衬底上的第一栅极氧化物层。堆叠覆盖第一栅极氧化物层的多晶硅层。图案化多晶硅层以形成第一NMOS栅极。在衬底上生长第二栅极氧化物层。沉积覆盖第二栅极氧化物层和第一栅极的多晶硅 - 锗层。将多晶硅锗层和第一栅极平坦化成均匀的厚度。图案化多晶硅第一栅极和多晶硅 - 锗层以形成第二NMOS多晶硅栅极和PMOS多晶硅 - 锗栅极。

5. 发明申请

US20080157223A1 INTEGRATED CIRCUIT HAVING A PLURALITY OF MOSFET DEVICES 有权
标题翻译：具有多个MOSFET器件的集成电路
公开(公告)号：US20080157223A1
公开(公告)日：2008-07-03
申请号：US11617552
申请日：2006-12-28
申请人： Lee Wee Teo , Yong Meng Lee , Jeffrey Chee , Shyue Seng Tan , Chung Woh Lai , Johnny Widodo , Zhao Lun , Shailendra Mishra
发明人： Lee Wee Teo , Yong Meng Lee , Jeffrey Chee , Shyue Seng Tan , Chung Woh Lai , Johnny Widodo , Zhao Lun , Shailendra Mishra
IPC分类号： H01L27/088 , H01L21/77 , G06F17/50
CPC分类号： H01L21/823807 , G06F17/5063 , H01L21/823412 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/7843
摘要： A method is provided for manufacturing an integrated circuit having a plurality of MOSFET devices, comprising the steps of: providing a plurality of MOSFET devices each having a first and a second structural parameter associated therewith, wherein a value of one of the first and a second structural parameter of each device is selected to provide a value of a performance parameter of the device substantially equal to a predetermined reference value, the predetermined reference value being the same for each device.
摘要翻译：提供了一种用于制造具有多个MOSFET器件的集成电路的方法，包括以下步骤：提供多个MOSFET器件，每个MOSFET器件具有与其相关联的第一和第二结构参数，其中第一和第二选择每个设备的结构参数以提供设备的性能参数的值基本上等于预定参考值，所述预定参考值对于每个设备是相同的。

6. 发明申请

US20080150074A1 INTEGRATED CIRCUIT SYSTEM WITH ISOLATION 有权
标题翻译：集成电路系统与隔离
公开(公告)号：US20080150074A1
公开(公告)日：2008-06-26
申请号：US11614961
申请日：2006-12-21
申请人： Shailendra Mishra , Lee Wee Teo , Yong Meng Lee , Zhao Lun , Chung Woh Lai , Shyue Seng Tan , Jeffrey Chee , Johnny Widodo
发明人： Shailendra Mishra , Lee Wee Teo , Yong Meng Lee , Zhao Lun , Chung Woh Lai , Shyue Seng Tan , Jeffrey Chee , Johnny Widodo
IPC分类号： H01L21/762 , H01L29/06
CPC分类号： H01L21/76232 , H01L21/76283 , H01L21/823481
摘要： An integrated circuit system is provided including providing a substrate, forming an isolation structure base in the substrate without removal of the substrate, and forming a first transistor in the substrate next to the isolation structure base.
摘要翻译：提供一种集成电路系统，包括提供衬底，在衬底中形成隔离结构基底而不去除衬底，以及在隔离结构基底旁边的衬底中形成第一晶体管。

7. 发明授权

US08716081B2 Capacitor top plate over source/drain to form a 1T memory device 有权
标题翻译：源极/漏极上的电容器顶板形成1T存储器件
公开(公告)号：US08716081B2
公开(公告)日：2014-05-06
申请号：US11686475
申请日：2007-03-15
申请人： Lee Wee Teo , Yong Meng Lee , Zhao Lun , Chung Woh Lai , Shyue Seng Tan , Jeffrey Chee , Shailendra Mishra , Johnny Widodo
发明人： Lee Wee Teo , Yong Meng Lee , Zhao Lun , Chung Woh Lai , Shyue Seng Tan , Jeffrey Chee , Shailendra Mishra , Johnny Widodo
IPC分类号： H01L29/76
CPC分类号： H01L29/94 , H01L27/10805 , H01L27/1085 , H01L27/11
摘要： A method and structure for a memory device, such as a 1T-SRAM, having a capacitor top plate directly over a doped bottom plate region. An example device comprises the following. An isolation film formed as to surround an active area on a substrate. A gate dielectric and gate electrode formed over a portion of the active area. A source element and a drain element in the substrate adjacent to the gate electrode. The drain element is comprised of a drain region and a bottom plate region. The drain region is between the bottom plate region and the gate structure. A capacitor dielectric and a capacitor top plate are over at least portions of the bottom plate region.
摘要翻译：用于诸如1T-SRAM的存储器件的方法和结构，其具有直接在掺杂底板区域上方的电容器顶板。示例设备包括以下。形成为围绕衬底上的有源区域的隔离膜。形成在有源区域的一部分上的栅极电介质和栅电极。与栅电极相邻的衬底中的源极元件和漏极元件。漏极元件由漏区和底板区组成。漏极区域位于底板区域和栅极结构之间。电容器电介质和电容器顶板在底板区域的至少部分上方。

8. 发明授权

US08274115B2 Hybrid orientation substrate with stress layer 失效
标题翻译：混合取向基材与应力层
公开(公告)号：US08274115B2
公开(公告)日：2012-09-25
申请号：US12050956
申请日：2008-03-19
申请人： Lee Wee Teo , Chung Woh Lai , Johnny Widodo , Shyue Seng Tan , Shailendra Mishra , Zhao Lun , Yong Meng Lee , Jeffrey Chee
发明人： Lee Wee Teo , Chung Woh Lai , Johnny Widodo , Shyue Seng Tan , Shailendra Mishra , Zhao Lun , Yong Meng Lee , Jeffrey Chee
IPC分类号： H01L27/12
CPC分类号： H01L21/823807 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/1054 , H01L29/7849
摘要： A hybrid orientation substrate includes a base substrate having a first orientation, a first surface layer having a first orientation disposed on the base substrate in a first region, and a second surface layer disposed on the base substrate in a second region. The second surface layer has an upper sub-layer having a second orientation, and a lower sub-layer between the base substrate and the upper sub-layer. The lower sub-layer having a first stress induces a second stress on the upper sub-layer.
摘要翻译：混合取向基板包括具有第一取向的基底基板，在第一区域中具有设置在基底基板上的第一取向的第一表面层和在第二区域中设置在基底基板上的第二表面层。第二表层具有具有第二取向的上子层和在基底基板和上子层之间的下子层。具有第一应力的下部子层在上部子层上引起第二应力。

9. 发明授权

US07932178B2 Integrated circuit having a plurality of MOSFET devices 有权
标题翻译：具有多个MOSFET器件的集成电路
公开(公告)号：US07932178B2
公开(公告)日：2011-04-26
申请号：US11617552
申请日：2006-12-28
申请人： Lee Wee Teo , Yong Meng Lee , Jeffrey Chee , Shyue Seng Tan , Chung Woh Lai , Johnny Widodo , Zhao Lun , Shailendra Mishra
发明人： Lee Wee Teo , Yong Meng Lee , Jeffrey Chee , Shyue Seng Tan , Chung Woh Lai , Johnny Widodo , Zhao Lun , Shailendra Mishra
IPC分类号： H01L21/44
CPC分类号： H01L21/823807 , G06F17/5063 , H01L21/823412 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/7843
摘要： A method is provided for manufacturing an integrated circuit having a plurality of MOSFET devices, comprising the steps of: providing a plurality of MOSFET devices each having a first and a second structural parameter associated therewith, wherein a value of one of the first and a second structural parameter of each device is selected to provide a value of a performance parameter of the device substantially equal to a predetermined reference value, the predetermined reference value being the same for each device.
摘要翻译：提供了一种用于制造具有多个MOSFET器件的集成电路的方法，包括以下步骤：提供多个MOSFET器件，每个MOSFET器件具有与其相关联的第一和第二结构参数，其中第一和第二选择每个设备的结构参数以提供设备的性能参数的值基本上等于预定参考值，所述预定参考值对于每个设备是相同的。

10. 发明申请

US20090236663A1 HYBRID ORIENTATION SUBSTRATE WITH STRESS LAYER 失效
标题翻译：具有应力层的混合方向衬底
公开(公告)号：US20090236663A1
公开(公告)日：2009-09-24
申请号：US12050956
申请日：2008-03-19
申请人： Lee Wee Teo , Chung Woh Lai , Johnny Widodo , Shyue Seng Tan , Shailendra Mishra , Zhao Lun , Yong Meng Lee , Jeffrey Chee
发明人： Lee Wee Teo , Chung Woh Lai , Johnny Widodo , Shyue Seng Tan , Shailendra Mishra , Zhao Lun , Yong Meng Lee , Jeffrey Chee
IPC分类号： H01L29/786 , H01L21/76 , H01L23/58
CPC分类号： H01L21/823807 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/1054 , H01L29/7849
摘要： A hybrid orientation substrate includes a base substrate having a first orientation, a first surface layer having a first orientation disposed on the base substrate in a first region, and a second surface layer disposed on the base substrate in a second region. The second surface layer has an upper sub-layer having a second orientation, and a lower sub-layer between the base substrate and the upper sub-layer. The lower sub-layer having a first stress induces a second stress on the upper sub-layer.
摘要翻译：混合取向基板包括具有第一取向的基底基板，在第一区域中具有设置在基底基板上的第一取向的第一表面层和在第二区域中设置在基底基板上的第二表面层。第二表层具有具有第二取向的上子层和在基底基板和上子层之间的下子层。具有第一应力的下部子层在上部子层上引起第二应力。

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