专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06872608B1 Method to selectively form poly SiGe P type electrode and polysilicon N type electrode through planarization 失效
标题翻译：通过平面化选择性地形成多晶SiGe P型电极和多晶N型电极的方法
公开(公告)号：US06872608B1
公开(公告)日：2005-03-29
申请号：US10697746
申请日：2003-10-30
申请人： Tze Ho Chan , Mousumi Bhat , Jeffrey Chee
发明人： Tze Ho Chan , Mousumi Bhat , Jeffrey Chee
IPC分类号： H01L21/28 , H01L21/8238 , H01L21/338 , H01L21/00 , H01L21/84
CPC分类号： H01L21/823842 , H01L21/2807
摘要： A method for forming selective P type and N type gates is described. A first gate oxide layer is grown overlying a semiconductor substrate. A polysilicon layer is deposited overlying the first gate oxide layer. The polysilicon layer is patterned to form first NMOS gates. A second gate oxide layer is grown overlying the substrate. A polysilicon-germanium layer is deposited overlying the second gate oxide layer and the first gates. The polysilicon-germanium layer and first gates are planarized to a uniform thickness. The polysilicon first gates and the polysilicon-germanium layer are patterned to form second NMOS polysilicon gates and PMOS polysilicon-germanium gates.
摘要翻译：描述了形成选择性P型和N型栅极的方法。生长在半导体衬底上的第一栅极氧化物层。堆叠覆盖第一栅极氧化物层的多晶硅层。图案化多晶硅层以形成第一NMOS栅极。在衬底上生长第二栅极氧化物层。沉积覆盖第二栅极氧化物层和第一栅极的多晶硅 - 锗层。将多晶硅锗层和第一栅极平坦化成均匀的厚度。图案化多晶硅第一栅极和多晶硅 - 锗层以形成第二NMOS多晶硅栅极和PMOS多晶硅 - 锗栅极。

2. 发明申请

US20050098780A1 Planar voltage contrast test structure and method 有权
标题翻译：平面电压对比测试结构及方法
公开(公告)号：US20050098780A1
公开(公告)日：2005-05-12
申请号：US10703285
申请日：2003-11-06
申请人： Seng-Keong Lim , Dennis Tan , Tze Ho Chan
发明人： Seng-Keong Lim , Dennis Tan , Tze Ho Chan
IPC分类号： G01R31/28 , G01R31/307 , H01L21/66 , G01R31/26 , H01L23/58 , H01L29/10
CPC分类号： G01R31/307 , G01R31/2853 , G01R31/2884
摘要： An integrated circuit and e-beam testing method are disclosed. The integrated circuit includes a test structure with a ground grid, a metal pad having a space therein and positioned within the ground grid, and a metal line connected to the ground grid and positioned in the space. Structures for detecting open circuits and short circuits are described.
摘要翻译：公开了集成电路和电子束测试方法。集成电路包括具有接地栅格的测试结构，金属垫在其内具有空间并位于接地格栅内，金属线连接到接地格并定位在该空间中。描述了用于检测开路和短路的结构。

3. 发明申请

US20050095773A1 Method to lower work function of gate electrode through Ge implantation 有权
标题翻译：通过Ge注入来降低栅电极的功函数的方法
公开(公告)号：US20050095773A1
公开(公告)日：2005-05-05
申请号：US10701963
申请日：2003-11-05
申请人： Tze Ho Chan , Mousumi Bhat , Jeffrey Chee
发明人： Tze Ho Chan , Mousumi Bhat , Jeffrey Chee
IPC分类号： H01L21/3215 , H01L21/8238 , H01R4/64 , H01L21/302 , H01L21/461 , H01R4/60
CPC分类号： H01L21/823842 , H01L21/32155 , H01L21/82385
摘要： A method for forming selective P type and N type gates is described. A gate oxide layer is grown overlying a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. Germanium ions are implanted into a portion of the polysilicon layer not covered by a mask to form a polysilicon-germanium layer. The polysilicon layer and the polysilicon-germanium layer are patterned to form NMOS polysilicon gates and PMOS polysilicon-germanium gates. In an alternative, nitrogen ions are implanted into the polysilicon-germanium layer and the gates are annealed after patterning to redistribute the germanium ions throughout the polysilicon-germanium layer. In a second alternative, germanium ions are implanted into a first thin polysilicon layer, then a second polysilicon layer is deposited to achieve the total polysilicon layer thickness before patterning the gates.
摘要翻译：描述了形成选择性P型和N型栅极的方法。生长在半导体衬底上的栅氧化层。沉积在栅极氧化物层上的多晶硅层。将锗离子注入到未被掩模覆盖的多晶硅层的一部分中以形成多晶硅 - 锗层。图案化多晶硅层和多晶硅 - 锗层以形成NMOS多晶硅栅极和PMOS多晶硅 - 锗栅极。替代地，将氮离子注入到多晶硅 - 锗层中，并且在图案化之后对栅极进行退火以将锗离子重新分布在整个多晶硅 - 锗层中。在第二替代方案中，将锗离子注入到第一薄多晶硅层中，然后沉积第二多晶硅层以在栅极图案化之前实现总多晶硅层厚度。

4. 发明申请

US20050101102A1 Non-volatile memory and manufacturing method using STI trench implantation 有权
标题翻译：使用STI沟槽植入的非易失性存储器和制造方法
公开(公告)号：US20050101102A1
公开(公告)日：2005-05-12
申请号：US10703289
申请日：2003-11-06
申请人： Tze Ho Chan , Weining Li , Elgin Quek , Jia Zheng , Pradeep Ramachandramurthy Yelehanka , Tommy Lai
发明人： Tze Ho Chan , Weining Li , Elgin Quek , Jia Zheng , Pradeep Ramachandramurthy Yelehanka , Tommy Lai
IPC分类号： H01L21/336 , H01L21/762 , H01L21/8247 , H01L27/115 , H01L21/76
CPC分类号： H01L27/11521 , H01L21/76237 , H01L27/115 , H01L29/66825
摘要： A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming two trenches in the semiconductor substrate to define an active region therebetween. An implanted source region is formed in one of the trenches on one side of the active region. An implanted drain region is formed in the other trench on the other side of the active region. Shallow trench isolations are then formed in the trenches. One or more gates are formed over the active region, and contacts to the implanted source region and the implanted drain region are formed.
摘要翻译：一种用于制造集成电路结构的方法包括提供半导体衬底并在半导体衬底中形成两个沟槽以在其间限定有源区。植入的源极区域形成在有源区域的一侧的沟槽中的一个中。在有源区的另一侧的另一个沟槽中形成注入的漏极区。然后在沟槽中形成浅沟槽隔离。在有源区域上形成一个或多个栅极，并且形成与注入源极区域和注入的漏极区域的接触。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式