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1. 发明申请

US20100318707A1 EXTERNAL DEVICE ACCESS APPARATUS, CONTROL METHOD THEREOF, AND SYSTEM LSI 审中-公开
标题翻译：外部设备访问装置，其控制方法和系统LSI
公开(公告)号：US20100318707A1
公开(公告)日：2010-12-16
申请号：US12866061
申请日：2008-08-13
申请人： Tsuyoshi Tanaka , Nobuo Higaki , Takasi Inoue , Yosuke Kudo , Kazushi Kurata
发明人： Tsuyoshi Tanaka , Nobuo Higaki , Takasi Inoue , Yosuke Kudo , Kazushi Kurata
IPC分类号： G06F13/24 , G06F9/30
CPC分类号： G06F13/385 , G06F3/0611 , G06F3/0656 , G06F3/0659 , G06F3/0683
摘要： An external device access apparatus according to the present invention includes: an address control unit that accepts a prefetch request and a prefetch data readout request from a master and performs a prefetch operation and a prefetch data readout operation; a readout data storage unit that stores data read out through the prefetch operation; a storage operation status holding unit that holds a prefetch operation status indicating whether or not the prefetch operation has been completed; and an acceptance signal generation unit that outputs, to the master, an acceptance signal indicating that the prefetch data readout request has been accepted from the master. First information indicating a status of the prefetch operation is outputted to the master based on the prefetch operation status.
摘要翻译：根据本发明的外部设备接入装置包括：地址控制单元，其从主机接收预取请求和预取数据读出请求，并执行预取操作和预取数据读出操作; 读出数据存储单元，存储通过预取操作读出的数据; 存储操作状态保持单元，其保存指示预取操作是否已经完成的预取操作状态; 以及接收信号生成单元，其向主设备输出表示预取数据读出请求已经从主机接受的接收信号。基于预取操作状态，将指示预取操作的状态的第一信息输出到主机。

2. 发明授权

US08719827B2 Processor and program execution method capable of efficient program execution 有权
标题翻译：处理器和程序执行方法能够高效地执行程序
公开(公告)号：US08719827B2
公开(公告)日：2014-05-06
申请号：US13179614
申请日：2011-07-11
申请人： Kazushi Kurata , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazuya Furukawa , Shigeki Fujii , Toshio Sugimura
发明人： Kazushi Kurata , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazuya Furukawa , Shigeki Fujii , Toshio Sugimura
IPC分类号： G06F9/46 , G06F9/00 , G06F1/00
CPC分类号： G06F9/4881 , G06F9/3851 , G06F9/3867 , G06F9/462
摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.
摘要翻译：一种处理器，用于使用存储在与所述程序一对一的存储器中的多个寄存器值组来顺序地执行多个程序。处理器包括多个寄存器组; 选择/切换单元，其可操作以选择所述多个寄存器组中的一个作为程序执行所基于的执行目标寄存器组，并且每当经过第一预定时间时切换所述选择目标; 恢复单元，其可操作以在每次执行切换时将所述寄存器值组中的一个恢复为未被选择为所述执行目标寄存器组的寄存器组之一; 保存单元，其可操作以通过重写与寄存器值相对应的存储器中的寄存器值组来在恢复之前保存用于恢复的寄存器组中的值; 以及程序执行单元，其可操作以在每次执行切换时执行与执行目标寄存器组中的寄存器值组相对应的程序。

3. 发明授权

US07386707B2 Processor and program execution method capable of efficient program execution 有权
标题翻译：处理器和程序执行方法能够高效地执行程序
公开(公告)号：US07386707B2
公开(公告)日：2008-06-10
申请号：US10338408
申请日：2003-01-08
申请人： Kazushi Kurata , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazuya Furukawa , Shigeki Fujii , Toshio Sugimura
发明人： Kazushi Kurata , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazuya Furukawa , Shigeki Fujii , Toshio Sugimura
IPC分类号： G06F9/30 , G06F9/40
CPC分类号： G06F9/4881 , G06F9/3851 , G06F9/3867 , G06F9/462
摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.
摘要翻译：一种处理器，用于使用存储在与所述程序一对一的存储器中的多个寄存器值组来顺序地执行多个程序。处理器包括多个寄存器组; 选择/切换单元，其可操作以选择所述多个寄存器组中的一个作为程序执行所基于的执行目标寄存器组，并且每当经过第一预定时间时切换所述选择目标; 恢复单元，其可操作以在每次执行切换时将所述寄存器值组中的一个恢复为未被选择为所述执行目标寄存器组的寄存器组之一; 保存单元，其可操作以通过重写与寄存器值相对应的存储器中的寄存器值组来在恢复之前保存用于恢复的寄存器组中的值; 以及程序执行单元，其可操作以在每次执行切换时执行与执行目标寄存器组中的寄存器值组相对应的程序。

4. 发明授权

US07930520B2 Processor and program execution method capable of efficient program execution 有权
公开(公告)号：US07930520B2
公开(公告)日：2011-04-19
申请号：US12110539
申请日：2008-04-28
申请人： Kazushi Kurata , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazuya Furukawa , Shigeki Fujii , Toshio Sugimura
发明人： Kazushi Kurata , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazuya Furukawa , Shigeki Fujii , Toshio Sugimura
IPC分类号： G06F9/30 , G06F9/44 , G06F1/32
CPC分类号： G06F9/4881 , G06F9/3851 , G06F9/3867 , G06F9/462
摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

5. 发明申请

US20100180095A1 BUFFER CONTROL DEVICE AND BUFFER MEMORY DEVICE 审中-公开
标题翻译：缓冲器控制器件和缓冲器存储器件
公开(公告)号：US20100180095A1
公开(公告)日：2010-07-15
申请号：US12095610
申请日：2006-11-28
申请人： Masanori Fujibayashi , Nobuo Higaki , Kazushi Kurata , Tomoko Matsui
发明人： Masanori Fujibayashi , Nobuo Higaki , Kazushi Kurata , Tomoko Matsui
IPC分类号： G06F12/14
CPC分类号： G06F5/14 , G06F2205/062
摘要： The buffer control device of this invention includes: a pointer holding unit which holds a virtual pointer different from a read pointer and a write pointer; an access control unit that controls an access to a ring buffer; a judging unit that judges whether or not one of the read pointer and the write pointer has reached an address substantially identical to an address indicated by the virtual pointer; and disabling unit that disables a normal access using the one of the read pointer and the write pointer, when the judging unit judges that the one of the read pointer and the write pointer has reached the address substantially identical to the address indicated by the virtual pointer, the normal access being controlled by the access control unit, wherein the access control unit further controls a reaccess to the ring buffer.
摘要翻译：本发明的缓冲器控制装置包括：保持与读指针不同的虚拟指针和写指针的指针保持单元; 访问控制单元，其控制对环形缓冲器的访问; 判断单元，判断读指针和写指针之一是否达到与虚拟指针所指示的地址基本相同的地址; 以及禁止单元，其在所述读取指针和所述写入指针之一达到与所述虚拟指针所指示的地址基本相同的地址的情况下，使用所述读取指针和所述写入指针中的一者禁止正常访问正常访问由访问控制单元控制，其中访问控制单元进一步控制对环形缓冲器的重新访问。

6. 发明申请

US20090063734A1 BUS CONTROLLER 审中-公开
标题翻译：总线控制器
公开(公告)号：US20090063734A1
公开(公告)日：2009-03-05
申请号：US11817094
申请日：2006-02-27
申请人： Kazushi Kurata , Nobuo Higaki
发明人： Kazushi Kurata , Nobuo Higaki
IPC分类号： G06F3/00
CPC分类号： G06F13/28 , G06F13/4059
摘要： A bus controller capable of shortening the time required before a flush is completed so as not to degrade the performance of a processor. A bus controller includes: a FIFO for temporarily holding, on a first-in first-out basis, data to be stored from a processor into a memory; a flush pointer for holding a pointer which indicates end data held by the FIFO at a time when a trigger signal is received; a memory control unit for writing a portion of the data held by the FIFO into the memory according to the trigger signal so as to partially flush the FIFO, the portion ranging from start data through end data indicated by the flush pointer; and a wait circuit for generating a wait signal for a specific access instruction, which is executed by the processor, until the memory control unit completes the partial flush.
摘要翻译：一种总线控制器，能够在完成冲洗之前缩短所需的时间，从而不降低处理器的性能。总线控制器包括：FIFO，用于将先前从处理器存储的数据暂时保存在存储器中; 用于保持指示器的刷新指针，其指示在接收到触发信号时由FIFO保持的结束数据; 存储器控制单元，用于根据触发信号将由FIFO保存的数据的一部分写入存储器，以部分地刷新FIFO，该部分从开始数据到由刷新指针指示的结束数据; 以及等待电路，用于产生由处理器执行的特定访问指令的等待信号，直到存储器控制单元完成部分刷新。

7. 发明申请

US20080209192A1 PROCESSOR AND PROGRAM EXECUTION METHOD CAPABLE OF EFFICIENT PROGRAM EXECUTION 有权
公开(公告)号：US20080209192A1
公开(公告)日：2008-08-28
申请号：US12110513
申请日：2008-04-28
申请人： Kazuya Furukawa , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazushi Kurata , Shigeki Fujii , Toshio Sugimura
发明人： Kazuya Furukawa , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazushi Kurata , Shigeki Fujii , Toshio Sugimura
IPC分类号： G06F9/22
CPC分类号： G06F9/4881 , G06F9/3851 , G06F9/3867 , G06F9/462
摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

8. 发明授权

US08006076B2 Processor and program execution method capable of efficient program execution 有权
公开(公告)号：US08006076B2
公开(公告)日：2011-08-23
申请号：US12110491
申请日：2008-04-28
申请人： Kazushi Kurata , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazuya Furukawa , Shigeki Fujii , Toshio Sugimura
发明人： Kazushi Kurata , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazuya Furukawa , Shigeki Fujii , Toshio Sugimura
IPC分类号： G06F9/48 , G06F9/52
CPC分类号： G06F9/4881 , G06F9/3851 , G06F9/3867 , G06F9/462
摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

9. 发明申请

US20060259662A1 DATA TRNASFER APPARATUS, DATA TRANSFER METHOD, AND PROGRAM 有权
标题翻译：数据传输设备，数据传输方法和程序
公开(公告)号：US20060259662A1
公开(公告)日：2006-11-16
申请号：US11382379
申请日：2006-05-09
申请人： Kazuya Furukawa , Nobuo Higaki , Hideyo Tsuruta , Kazushi Kurata , Shigeki Fujii , Kousuke Yoshioka , Hiroyuki Morishita
发明人： Kazuya Furukawa , Nobuo Higaki , Hideyo Tsuruta , Kazushi Kurata , Shigeki Fujii , Kousuke Yoshioka , Hiroyuki Morishita
IPC分类号： G06F3/00
CPC分类号： G06F3/0221 , G06F13/28 , Y02D10/14
摘要： A data transfer apparatus according to the present invention has; a DMAC and another DMAC which transfer data by direct memory access among a plurality of buses; a command queue which holds, as a queue, commands for instructing the data transfer; a bus information obtainment unit which obtains the commands from the command queue; a grouping unit which groups the held commands, based on a source and a destination designated in each of the obtained commands; a schedule unit which decides an order of issuing the commands sequentially from a group having more command, as a priority; and a selector which selects a command to be issued according to the decided order.
摘要翻译：根据本发明的数据传送装置具有： DMAC和另一个DMAC，其通过多个总线之间的直接存储器访问来传送数据; 作为队列保存用于指示数据传送的命令的命令队列; 总线信息获取单元，其从命令队列获取命令; 分组单元，其基于在每个所获得的命令中指定的源和目的地对保持的命令进行分组; 作为优先级，从具有更多命令的组中顺序地确定发出命令的顺序的调度单元; 以及选择器，其根据所决定的顺序选择要发出的命令。

10. 发明授权

US07716391B2 Data transfer apparatus, data transfer method, and program 有权
标题翻译：数据传输装置，数据传输方法和程序
公开(公告)号：US07716391B2
公开(公告)日：2010-05-11
申请号：US11382379
申请日：2006-05-09
申请人： Kazuya Furukawa , Nobuo Higaki , Hideyo Tsuruta , Kazushi Kurata , Shigeki Fujii , Kousuke Yoshioka , Hiroyuki Morishita
发明人： Kazuya Furukawa , Nobuo Higaki , Hideyo Tsuruta , Kazushi Kurata , Shigeki Fujii , Kousuke Yoshioka , Hiroyuki Morishita
IPC分类号： G06F3/00
CPC分类号： G06F3/0221 , G06F13/28 , Y02D10/14
摘要： A data transfer apparatus according to the present invention has; a DMAC and another DMAC which transfer data by direct memory access among a plurality of buses; a command queue which holds, as a queue, commands for instructing the data transfer; a bus information obtainment unit which obtains the commands from the command queue; a grouping unit which groups the held commands, based on a source and a destination designated in each of the obtained commands; a schedule unit which decides an order of issuing the commands sequentially from a group having more command, as a priority; and a selector which selects a command to be issued according to the decided order.
摘要翻译：根据本发明的数据传送装置具有： DMAC和另一个DMAC，其通过多个总线之间的直接存储器访问来传送数据; 作为队列保存用于指示数据传送的命令的命令队列; 总线信息获取单元，其从命令队列获取命令; 分组单元，其基于在每个所获得的命令中指定的源和目的地对保持的命令进行分组; 作为优先级，从具有更多命令的组中顺序地确定发出命令的顺序的调度单元; 以及选择器，其根据所决定的顺序选择要发出的命令。

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