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1. 发明申请

US20080012078A1 SEMICONDUCTOR DEVICE FORMED IN SEMICONDUCTOR LAYER ARRANGED ON SUBSTRATE WITH ONE OF INSULATING FILM AND CAVITY INTERPOSED BETWEEN THE SUBSTRATE AND THE SEMICONDUCTOR LAYER 失效
标题翻译：在半导体层中形成的半导体器件在衬底上安装有绝缘膜和衬底与半导体层之间的绝缘膜之间的孔
公开(公告)号：US20080012078A1
公开(公告)日：2008-01-17
申请号：US11849682
申请日：2007-09-04
申请人： Tsutomu Sato , Hajime Nagano , Ichiro Mizushima , Takashi Yamada , Yuso Udo , Shinichi Nitta
发明人： Tsutomu Sato , Hajime Nagano , Ichiro Mizushima , Takashi Yamada , Yuso Udo , Shinichi Nitta
IPC分类号： H01L27/01
CPC分类号： H01L21/764 , H01L21/76264 , H01L21/76283 , H01L21/76289 , H01L21/823412 , H01L21/823481 , H01L21/84 , H01L27/10897 , H01L27/1203 , H01L27/1207
摘要： A semiconductor device including a first semiconductor layer formed on a semiconductor substrate, a second semiconductor layer surrounding the first semiconductor layer, the second semiconductor layer being formed on the semiconductor substrate with one of an insulating film and a cavity, and a third semiconductor layer surrounding the second semiconductor layer, the third semiconductor layer being formed on the semiconductor substrate.
摘要翻译：一种半导体器件，包括形成在半导体衬底上的第一半导体层，围绕第一半导体层的第二半导体层，在半导体衬底上形成有绝缘膜和空腔中的一个的第二半导体层和围绕所述第二半导体层，所述第三半导体层形成在所述半导体衬底上。

2. 发明申请

US20050156245A1 Semiconductor device formed in semiconductor layer arranged on substrate with one of insulating film and cavity interposed between the substrate and the semiconductor layer 审中-公开
标题翻译：在半导体层中形成的半导体器件，其布置在基板上，绝缘膜和空腔中的一个介于基板和半导体层之间
公开(公告)号：US20050156245A1
公开(公告)日：2005-07-21
申请号：US11073617
申请日：2005-03-08
申请人： Tsutomu Sato , Hajime Nagano , Ichiro Mizushima , Takashi Yamada , Yuso Udo , Shinichi Nitta
发明人： Tsutomu Sato , Hajime Nagano , Ichiro Mizushima , Takashi Yamada , Yuso Udo , Shinichi Nitta
IPC分类号： H01L21/762 , H01L27/12 , H01L27/10
CPC分类号： H01L21/764 , H01L21/76264 , H01L21/76283 , H01L21/76289 , H01L21/823412 , H01L21/823481 , H01L21/84 , H01L27/10897 , H01L27/1203 , H01L27/1207
摘要： A semiconductor device according to an aspect of the present invention comprises a first semiconductor layer and a plurality of second semiconductor layers. The first semiconductor layer is formed in a first region of a semiconductor substrate with one of an insulating film and a cavity interposed between the semiconductor substrate and the first semiconductor layer. The plurality of second semiconductor layers is formed in second regions of the semiconductor substrate.
摘要翻译：根据本发明的一个方面的半导体器件包括第一半导体层和多个第二半导体层。第一半导体层形成在半导体衬底的第一区域中，绝缘膜和介于半导体衬底和第一半导体层之间的腔中的一个。多个第二半导体层形成在半导体衬底的第二区域中。

3. 发明授权

US07420249B2 Semiconductor device formed in semiconductor layer arranged on substrate with one of insulating film and cavity interposed between the substrate and the semiconductor layer 失效
标题翻译：在半导体层中形成的半导体器件，其布置在基板上，绝缘膜和空腔中的一个介于基板和半导体层之间
公开(公告)号：US07420249B2
公开(公告)日：2008-09-02
申请号：US11849682
申请日：2007-09-04
申请人： Tsutomu Sato , Hajime Nagano , Ichiro Mizushima , Takashi Yamada , Yuso Udo , Shinichi Nitta
发明人： Tsutomu Sato , Hajime Nagano , Ichiro Mizushima , Takashi Yamada , Yuso Udo , Shinichi Nitta
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L21/764 , H01L21/76264 , H01L21/76283 , H01L21/76289 , H01L21/823412 , H01L21/823481 , H01L21/84 , H01L27/10897 , H01L27/1203 , H01L27/1207
摘要： A semiconductor device including a first semiconductor layer formed on a semiconductor substrate, a second semiconductor layer surrounding the first semiconductor layer, the second semiconductor layer being formed on the semiconductor substrate with one of an insulating film and a cavity, and a third semiconductor layer surrounding the second semiconductor layer, the third semiconductor layer being formed on the semiconductor substrate.
摘要翻译：一种半导体器件，包括形成在半导体衬底上的第一半导体层，围绕第一半导体层的第二半导体层，在半导体衬底上形成有绝缘膜和空腔中的一个的第二半导体层和围绕所述第二半导体层，所述第三半导体层形成在所述半导体衬底上。

4. 发明授权

US07019365B2 Semiconductor device formed in semiconductor layer arranged on substrate with one of insulating film and cavity interposed between the substrate and the semiconductor layer 失效
公开(公告)号：US07019365B2
公开(公告)日：2006-03-28
申请号：US10637665
申请日：2003-08-11
申请人： Tsutomu Sato , Hajime Nagano , Ichiro Mizushima , Takashi Yamada , Yuso Udo , Shinichi Nitta
发明人： Tsutomu Sato , Hajime Nagano , Ichiro Mizushima , Takashi Yamada , Yuso Udo , Shinichi Nitta
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L21/764 , H01L21/76264 , H01L21/76283 , H01L21/76289 , H01L21/823412 , H01L21/823481 , H01L21/84 , H01L27/10897 , H01L27/1203 , H01L27/1207
摘要： A semiconductor device according to an aspect of the present invention comprises a first semiconductor layer and a plurality of second semiconductor layers. The first semiconductor layer is formed in a first region of a semiconductor substrate with one of an insulating film and a cavity interposed between the semiconductor substrate and the first semiconductor layer. The plurality of second semiconductor layers is formed in second regions of the semiconductor substrate.

5. 发明授权

US06630714B2 Semiconductor device formed in semiconductor layer arranged on substrate with one of insulating film and cavity interposed between the substrate and the semiconductor layer 有权
标题翻译：在半导体层中形成的半导体器件，其布置在基板上，绝缘膜和空腔中的一个介于基板和半导体层之间
公开(公告)号：US06630714B2
公开(公告)日：2003-10-07
申请号：US10091448
申请日：2002-03-07
申请人： Tsutomu Sato , Hajime Nagano , Ichiro Mizushima , Takashi Yamada , Yuso Udo , Shinichi Nitta
发明人： Tsutomu Sato , Hajime Nagano , Ichiro Mizushima , Takashi Yamada , Yuso Udo , Shinichi Nitta
IPC分类号： H01L2701
CPC分类号： H01L21/764 , H01L21/76264 , H01L21/76283 , H01L21/76289 , H01L21/823412 , H01L21/823481 , H01L21/84 , H01L27/10897 , H01L27/1203 , H01L27/1207
摘要： A semiconductor device according to an aspect of the present invention comprises a first semiconductor layer and a plurality of second semiconductor layers. The first semiconductor layer is formed in a first region of a semiconductor substrate with one of an insulating film and a cavity interposed between the semiconductor substrate and the first semiconductor layer. The plurality of second semiconductor layers is formed in second regions of the semiconductor substrate.
摘要翻译：根据本发明的一个方面的半导体器件包括第一半导体层和多个第二半导体层。第一半导体层形成在半导体衬底的第一区域中，绝缘膜和介于半导体衬底和第一半导体层之间的腔中的一个。多个第二半导体层形成在半导体衬底的第二区域中。

6. 发明申请

US20060131696A1 Semiconductor wafer with ID mark, equipment for and method of manufacturing semiconductor device from them 失效
公开(公告)号：US20060131696A1
公开(公告)日：2006-06-22
申请号：US11350027
申请日：2006-02-09
申请人： Tsunetoshi Arikado , Masao Iwase , Soichi Nadahara , Yuso Udo , Yukihiro Ushiku , Shinichi Nitta , Moriya Miyashita , Junji Sugamoto , Hiroaki Yamada , Hajime Nagano , Katsujiro Tanzawa , Hiroshi Matsushita , Norihiko Tsuchiya , Katsuya Okumura
发明人： Tsunetoshi Arikado , Masao Iwase , Soichi Nadahara , Yuso Udo , Yukihiro Ushiku , Shinichi Nitta , Moriya Miyashita , Junji Sugamoto , Hiroaki Yamada , Hajime Nagano , Katsujiro Tanzawa , Hiroshi Matsushita , Norihiko Tsuchiya , Katsuya Okumura
IPC分类号： H01L29/06 , H01L23/02
CPC分类号： H01L23/544 , H01L2223/54406 , H01L2223/54413 , H01L2223/54433 , H01L2223/54493 , H01L2924/0002 , Y10S438/974 , H01L2924/00
摘要： A semiconductor wafer has a bevel contour formed along the periphery thereof, products formed on the wafer, and an ID mark formed on the bevel contour. The ID mark shows at least the properties, manufacturing conditions, and test results of the products.

7. 发明授权

US07057259B2 Semiconductor wafer with ID mark, equipment for and method of manufacturing semiconductor device from them 失效
公开(公告)号：US07057259B2
公开(公告)日：2006-06-06
申请号：US10101337
申请日：2002-03-20
申请人： Tsunetoshi Arikado , Masao Iwase , Soichi Nadahara , Yuso Udo , Yukihiro Ushiku , Shinichi Nitta , Moriya Miyashita , Junji Sugamoto , Hiroaki Yamada , Hajime Nagano , Katsujiro Tanzawa , Hiroshi Matsushita , Norihiko Tsuchiya , Katsuya Okumura
发明人： Tsunetoshi Arikado , Masao Iwase , Soichi Nadahara , Yuso Udo , Yukihiro Ushiku , Shinichi Nitta , Moriya Miyashita , Junji Sugamoto , Hiroaki Yamada , Hajime Nagano , Katsujiro Tanzawa , Hiroshi Matsushita , Norihiko Tsuchiya , Katsuya Okumura
IPC分类号： H01L29/06
CPC分类号： H01L23/544 , H01L2223/54406 , H01L2223/54413 , H01L2223/54433 , H01L2223/54493 , H01L2924/0002 , Y10S438/974 , H01L2924/00
摘要： A semiconductor wafer has a bevel contour formed along the periphery thereof, products formed on the wafer, and an ID mark formed on the bevel contour. The ID mark shows at least the properties, manufacturing conditions, and test results of the products.

8. 发明授权

US07700381B2 Semiconductor wafer with ID mark, equipment for and method of manufacturing semiconductor device from them 失效
标题翻译：具有ID标记的半导体晶圆，其半导体器件的制造方法和制造方法
公开(公告)号：US07700381B2
公开(公告)日：2010-04-20
申请号：US11350027
申请日：2006-02-09
申请人： Tsunetoshi Arikado , Masao Iwase , Soichi Nadahara , Yuso Udo , Yukihiro Ushiku , Shinichi Nitta , Moriya Miyashita , Junji Sugamoto , Hiroaki Yamada , Hajime Nagano , Katsujiro Tanzawa , Hiroshi Matsushita , Norihiko Tsuchiya , Katsuya Okumura
发明人： Tsunetoshi Arikado , Masao Iwase , Soichi Nadahara , Yuso Udo , Yukihiro Ushiku , Shinichi Nitta , Moriya Miyashita , Junji Sugamoto , Hiroaki Yamada , Hajime Nagano , Katsujiro Tanzawa , Hiroshi Matsushita , Norihiko Tsuchiya , Katsuya Okumura
IPC分类号： G01R31/26 , H01L21/66
CPC分类号： H01L23/544 , H01L2223/54406 , H01L2223/54413 , H01L2223/54433 , H01L2223/54493 , H01L2924/0002 , Y10S438/974 , H01L2924/00
摘要： A semiconductor wafer has a bevel contour formed along the periphery thereof, products formed on the wafer, and an ID mark formed on the bevel contour. The ID mark shows at least the properties, manufacturing conditions, and test results of the products.
摘要翻译：半导体晶片具有沿其周边形成的斜面轮廓，形成在晶片上的产品和形成在斜面轮廓上的ID标记。 ID标记至少显示产品的性能，制造条件和测试结果。

9. 发明授权

US06515733B1 Pattern exposure apparatus for transferring circuit pattern on semiconductor wafer and pattern exposure method 失效
标题翻译：用于在半导体晶片上传送电路图案的图案曝光装置和图案曝光方法
公开(公告)号：US06515733B1
公开(公告)日：2003-02-04
申请号：US09605897
申请日：2000-06-29
申请人： Yuso Udo
发明人： Yuso Udo
IPC分类号： G03B2742
CPC分类号： G03F9/7034 , G03F9/7046
摘要： A semiconductor wafer having an effective chip region set within an effective element region in which an element is formed and required for forming a single chip and an ineffective chip region which includes an ineffective element region in which no element is formed and required for forming a single chip. A degree of unevenness of a surface of the semiconductor wafer is measured at a plurality of sites within a predetermined region by an unevenness measuring section by applying light thereof, so that unevenness data are output. The predetermined region includes either or a part of both of the effective chip region and the ineffective chip region. A reference plane to which light is applied is determined by using only unevenness data of the effective chip region after unevenness data of the ineffective chip region are eliminated from the unevenness data. Inclination of the semiconductor wafer is controlled in accordance with the reference plane obtained through the calculation performed by the calculating section.
摘要翻译：将有效芯片区域设置在有效元件区域内的半导体晶片，其中形成元件并形成单个芯片所需的有效芯片区域和无效的芯片区域，其包括无效元件区域，其中没有元件形成并且需要用于形成单个芯片芯片。半导体晶片的表面的不均匀度通过不平坦度测量部分在预定区域内的多个位置处被测量，从而输出不均匀性数据。预定区域包括有效芯片区域和无效芯片区域中的任一个或一部分。通过在不均匀性数据中消除无效芯片区域的不均匀性数据之后，仅使用有效芯片区域的不均匀性数据来确定施加光的参考平面。根据通过计算部执行的计算而获得的参考平面来控制半导体晶片的倾斜。

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