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1. 发明授权

US07188049B2 System and method for controlling manufacturing processes, and method for manufacturing a semiconductor device 失效
标题翻译：用于控制制造工艺的系统和方法，以及制造半导体器件的方法
公开(公告)号：US07188049B2
公开(公告)日：2007-03-06
申请号：US11086220
申请日：2005-03-23
申请人： Norihiko Tsuchiya , Yukihiro Ushiku
发明人： Norihiko Tsuchiya , Yukihiro Ushiku
IPC分类号： G06F15/00
CPC分类号： H01L21/67253 , H01L22/20 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A control system for a manufacturing process includes an inspection tool inspecting a dislocation image in semiconductor substrate processed by manufacturing processes; an inspection information input module configured to acquire the inspected dislocation image; a process condition input module acquiring process conditions of the manufacturing processes; a structure information input module acquiring structure of the semiconductor substrate processed by target manufacturing process; a stress analysis module calculating stresses at nodes provided in the structure, based on target process condition and the structure; an origin setting module providing origins at positions where stress concentration having stress value not less than reference value is predicted; a dislocation dynamics analysis module calculating dislocation pattern in stress field for each position of the origins; and a dislocation pattern comparison module comparing the dislocation pattern with the inspected dislocation image so as to determine whether the target manufacturing process is critical manufacturing process.
摘要翻译：用于制造工艺的控制系统包括检查通过制造工艺处理的半导体衬底中的位错图像的检查工具; 检查信息输入模块，被配置为获取所检查的位错图像; 过程条件输入模块获取制造过程的处理条件; 通过目标制造工艺处理的半导体衬底的结构信息输入模块获取结构; 应力分析模块，根据目标过程条件和结构计算结构中提供的节点处的应力; 原点设定模块，其在具有应力值不小于参考值的应力集中的位置处提供起点; 位错动力学分析模块计算各个位置的应力场位错模式; 以及位错图案比较模块，将位错图案与被检查的位错图像进行比较，以确定目标制造过程是否是关键的制造过程。

2. 发明授权

US06320655B1 Defect-position identifying method for semiconductor substrate 失效
标题翻译：半导体衬底的缺陷位置识别方法
公开(公告)号：US06320655B1
公开(公告)日：2001-11-20
申请号：US09525943
申请日：2000-03-15
申请人： Hiroshi Matsushita , Norihiko Tsuchiya , Youko Toyomaru
发明人： Hiroshi Matsushita , Norihiko Tsuchiya , Youko Toyomaru
IPC分类号： G01N2100
CPC分类号： G01N21/9501
摘要： A defect-position identifying method for a semiconductor substrate comprises the steps of: forming at least three reference points on a semiconductor substrate; detecting the reference points and a defect on the semiconductor substrate by means of a first evaluating system, which is provided for evaluating the defect on the semiconductor substrate, to measure coordinate values of the reference points and the defect in a system of coordinates of the first evaluating system; detecting the reference points on the semiconductor substrate by means of a second evaluating system, which is provided for evaluating the defect on the semiconductor substrate, to measure coordinate values of the reference points in a system of coordinates of the second evaluating system; determining an affine transformation for transforming the system of coordinates of the first evaluating system to the system of coordinates of the second evaluating system on the basis of the coordinate values of each of the reference points in the first and second evaluating systems; and identifying the position of the defect in the system of coordinates of the second evaluating system on the basis of the determined affine transformation and the coordinate values of the defect in the system of coordinates of the first evaluating system. Thus, it is possible to precisely identify the position of the defect.
摘要翻译：半导体衬底的缺陷位置识别方法包括以下步骤：在半导体衬底上形成至少三个参考点; 通过用于评估半导体衬底上的缺陷的第一评估系统来检测参考点和半导体衬底上的缺陷，以测量第一个坐标系的参考点和缺陷的坐标值评价体系; 通过用于评估半导体衬底上的缺陷的第二评估系统来检测半导体衬底上的参考点，以测量第二评估系统的坐标系中的参考点的坐标值; 基于第一和第二评估系统中的每个参考点的坐标值，确定用于将第一评估系统的坐标系变换为第二评估系统的坐标系的仿射变换; 并且基于所确定的仿射变换和第一评估系统的坐标系中的缺陷的坐标值，识别第二评估系统的坐标系中的缺陷的位置。因此，可以精确地识别缺陷的位置。

3. 发明授权

US5675176A Semiconductor device and a method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5675176A
公开(公告)日：1997-10-07
申请号：US530721
申请日：1995-09-15
申请人： Yukihiro Ushiku , Atsushi Yagishita , Satoshi Inaba , Minoru Takahashi , Masanori Numano , Yoshiki Hayashi , Yoshiaki Matsushita , Yasunori Okayama , Hiroyasu Kubota , Norihiko Tsuchiya
发明人： Yukihiro Ushiku , Atsushi Yagishita , Satoshi Inaba , Minoru Takahashi , Masanori Numano , Yoshiki Hayashi , Yoshiaki Matsushita , Yasunori Okayama , Hiroyasu Kubota , Norihiko Tsuchiya
IPC分类号： H01L27/092 , H01L27/108 , H01L29/10 , H01L29/30
CPC分类号： H01L27/0921 , H01L27/10808 , H01L29/1079
摘要： A semiconductor device has a semiconductor substrate having a groove, and a semiconductor element formed in a surface region of the semiconductor substrate. A substance having a thermal expansion coefficient different from the semiconductor substrate is embedded in at least a portion of the groove, a crystal defect is generated from the region near the bottom of the groove in the semiconductor substrate, thereby alleviating stress and strain in other regions of the semiconductor substrate, such that such regions cannot generate crystal defects in a region necessary for a circuit operation of the semiconductor element of the surface region.
摘要翻译：半导体器件具有具有凹槽的半导体衬底和形成在半导体衬底的表面区域中的半导体元件。具有与半导体基板不同的热膨胀系数的物质嵌入到槽的至少一部分中，从半导体衬底中的槽的底部附近的区域产生晶体缺陷，从而减轻其他区域中的应力和应变使得这些区域不会在表面区域的半导体元件的电路操作所需的区域中产生晶体缺陷。

4. 发明授权

US07531462B2 Method of inspecting semiconductor wafer 失效
标题翻译：检查半导体晶圆的方法
公开(公告)号：US07531462B2
公开(公告)日：2009-05-12
申请号：US11444301
申请日：2006-06-01
申请人： Katsujiro Tanzawa , Norihiko Tsuchiya , Junji Sugamoto , Yukihiro Ushiku
发明人： Katsujiro Tanzawa , Norihiko Tsuchiya , Junji Sugamoto , Yukihiro Ushiku
IPC分类号： H01L21/302
CPC分类号： H01L22/12 , G01N21/9501
摘要： A method of inspecting a semiconductor wafer, comprises removing a device structure film on the semiconductor wafer with a chemical solution to expose a crystal surface of the semiconductor wafer; coating a protected area, which is a part of the crystal surface of the semiconductor wafer, with a mask material for protecting the crystal surface of the semiconductor wafer; etching the semiconductor wafer selectively, thereby making a crystal defect in a non-protected area, which is a part of the crystal surface of the semiconductor wafer that is not coated with the mask material, appear after the crystal surface is coated with the mask material; removing the mask material after the selective etching; carrying out quantitative measurement of the protected area and the non-protected area using an optical defect inspection apparatus or a beam-type defect inspection apparatus; and calculating the number of crystal defects of the semiconductor wafer base on the result of the measurement.
摘要翻译：一种检查半导体晶片的方法，包括用化学溶液去除半导体晶片上的器件结构膜以暴露半导体晶片的晶体表面; 用保护半导体晶片的晶体表面的掩模材料涂覆作为半导体晶片的晶体表面的一部分的保护区域; 选择性地蚀刻半导体晶片，从而在未涂覆有掩模材料的半导体晶片的晶体表面的一部分的非保护区域中出现晶体缺陷，在晶体表面涂覆有掩模材料之后 ; 在选择性蚀刻之后去除掩模材料; 使用光学缺陷检查装置或光束型缺陷检查装置进行保护区域和非保护区域的定量测量; 并根据测量结果计算半导体晶片基底的晶体缺陷数。

5. 发明授权

US6146911A Semiconductor wafer and method of manufacturing the same 有权
标题翻译：半导体晶片及其制造方法
公开(公告)号：US6146911A
公开(公告)日：2000-11-14
申请号：US263216
申请日：1999-03-05
申请人： Norihiko Tsuchiya , Hiroshi Matsushita
发明人： Norihiko Tsuchiya , Hiroshi Matsushita
IPC分类号： H01L21/324 , H01L21/02 , H01L21/66
CPC分类号： H01L22/12
摘要： The average density and scattered light intensity or the average density and average size of void defects contained in a surface region in a predetermined depth of a semiconductor wafer sample are measured. An ingot whose a semiconductor wafer sample satisfies D.times.Is.ltoreq.a predetermined value between the measured average density D and scattered light intensity Is or satisfies D.times.L.sup.3 .ltoreq.fixed value between the measured average density D and average size L is extracted and wafers cut from the ingot are annealed. The semiconductor wafers having few residual defects in a surface region wherein devices are to be formed can be obtained.
摘要翻译：测量包含在半导体晶片样品的预定深度的表面区域中的空隙的平均密度和散射光强度或平均密度和平均尺寸。将半导体晶片样品满足DxIs之间的测量平均密度D和散射光强度Is之间的预定值或满足DxL3 <测量平均密度D和平均尺寸L之间的固定值的晶锭，并从锭退火。可以获得在要形成器件的表面区域中具有很少残留缺陷的半导体晶片。

6. 发明授权

US5738942A Semiconductor silicon wafer and process for producing it 失效
标题翻译：半导体硅晶片及其生产工艺
公开(公告)号：US5738942A
公开(公告)日：1998-04-14
申请号：US580926
申请日：1995-12-29
申请人： Atsuko Kubota , Masakatu Kojima , Norihiko Tsuchiya , Shuichi Samata , Masanori Numano , Yoshihiro Ueno
发明人： Atsuko Kubota , Masakatu Kojima , Norihiko Tsuchiya , Shuichi Samata , Masanori Numano , Yoshihiro Ueno
IPC分类号： H01L21/304 , C30B15/00 , C30B33/00 , H01L21/322 , H01L21/332 , B32B9/00 , H01L21/306 , H01L23/58 , H01L29/04
CPC分类号： C30B29/06 , C30B15/00 , C30B33/00 , H01L21/3221 , H01L21/3225 , H01L29/66393 , Y10S148/06 , Y10S148/061
摘要： Provided is a process for producing a semiconductor silicon wafer by which an intrinsic gettering effect can be improved and at the same time the top side can be made free from faults. A silicon ingot is produced and sliced to obtain silicon wafers. Then, a polycrystal silicon depositing film is formed on one side of a silicon wafer, which is subjected to a heat treatment in an inert gas, a reducing gas or a mixture thereof to discharge oxygen from the vicinity of the other side. Alternatively, after discharging oxygen from the silicon wafer by a heat treatment, a polycrystal silicon depositing film may be formed on one side of the silicon wafer.
摘要翻译：本发明提供一种半导体硅晶片的制造方法，其特征在于能够提高固有的吸杂效果，同时能够使上侧无缺陷。生产硅锭并切片以获得硅晶片。然后，在硅晶片的一侧上形成多晶硅沉积膜，该硅晶片在惰性气体，还原气体或其混合物中进行热处理，以从另一侧附近排出氧气。或者，在通过热处理从硅晶片中排出氧之后，可以在硅晶片的一侧上形成多晶硅沉积膜。

7. 发明申请

US20060281281A1 Method of inspecting semiconductor wafer 失效
公开(公告)号：US20060281281A1
公开(公告)日：2006-12-14
申请号：US11444301
申请日：2006-06-01
申请人： Katsujiro Tanzawa , Norihiko Tsuchiya , Junji Sugamoto , Yukihiro Ushiku
发明人： Katsujiro Tanzawa , Norihiko Tsuchiya , Junji Sugamoto , Yukihiro Ushiku
IPC分类号： H01L21/66 , H01L21/30
CPC分类号： H01L22/12 , G01N21/9501
摘要： A method of inspecting a semiconductor wafer, comprises removing a device structure film on the semiconductor wafer with a chemical solution to expose a crystal surface of the semiconductor wafer; coating a protected area, which is a part of the crystal surface of the semiconductor wafer, with a mask material for protecting the crystal surface of the semiconductor wafer; etching the semiconductor wafer selectively, thereby making a crystal defect in a non-protected area, which is a part of the crystal surface of the semiconductor wafer that is not coated with the mask material, appear after the crystal surface is coated with the mask material; removing the mask material after the selective etching; carrying out quantitative measurement of the protected area and the non-protected area using an optical defect inspection apparatus or a beam-type defect inspection apparatus; and calculating the number of crystal defects of the semiconductor wafer base on the result of the measurement.

8. 发明授权

US06963630B2 Method for evaluating an SOI substrate, evaluation processor, and method for manufacturing a semiconductor device 失效
标题翻译：用于评估SOI衬底的方法，评估处理器以及用于制造半导体器件的方法
公开(公告)号：US06963630B2
公开(公告)日：2005-11-08
申请号：US10336685
申请日：2003-01-06
申请人： Kaori Umezawa , Norihiko Tsuchiya
发明人： Kaori Umezawa , Norihiko Tsuchiya
IPC分类号： G01N23/207 , G01N23/20 , H01L21/66 , H01L27/12
CPC分类号： H01L22/12 , G01N23/20
摘要： A method for evaluating an SOI layer on an insulating film disposed on a base substrate so as to construct an SOI substrate, includes: measuring a first diffraction intensity distribution of an X-ray beam corresponding to an incident angle formed with the X-ray beam and a front surface of the SOI substrate by irradiating the X-ray beam onto the base substrate; measuring a second diffraction intensity distribution of the X-ray beam for the incident angle formed with the X-ray beam and the front surface of the SOI substrate by irradiating the X-ray beam onto the SOI layer; determining an evaluation diffraction peak corresponding to the SOI layer from the first and the second diffraction intensity distribution; and observing an X-ray topograph by irradiating the X-ray beam on the SOI layer with a second incident beam angle of the evaluation diffraction peak.
摘要翻译：一种用于评估设置在基底基板上以构成SOI衬底的绝缘膜上的SOI层的方法，包括：测量与由X射线束形成的入射角相对应的X射线束的第一衍射强度分布以及通过将X射线束照射到基底基板上的SOI衬底的前表面; 通过将X射线束照射到SOI层上，测量与X射线束和SOI衬底的前表面形成的入射角的X射线束的第二衍射强度分布; 从所述第一和第二衍射强度分布确定对应于所述SOI层的评估衍射峰; 并且通过以评估衍射峰的第二入射光束角对SOI层照射X射线束来观察X射线显微镜。

9. 发明授权

US5994756A Substrate having shallow trench isolation 失效
标题翻译：衬底具有浅沟槽隔离
公开(公告)号：US5994756A
公开(公告)日：1999-11-30
申请号：US751438
申请日：1996-11-20
申请人： Kaori Umezawa , Norihiko Tsuchiya , Yoshiaki Matsushita , Hiroyuki Kamijou , Atsushi Yagishita , Tsunehiro Kita
发明人： Kaori Umezawa , Norihiko Tsuchiya , Yoshiaki Matsushita , Hiroyuki Kamijou , Atsushi Yagishita , Tsunehiro Kita
IPC分类号： H01L21/762 , H01L27/04 , H01L23/58
CPC分类号： H01L21/76232 , H01L21/76264 , H01L21/76275 , H01L21/76283
摘要： A semiconductor substrate having a shallow trench isolation (STI) structure and a method of manufacturing the same are provided, i.e., an isolation substrate in which grooves are selectively formed at predetermined locations of the semiconductor substrate and oxide films using organic silicon source as material are buried in the grooves as buried oxide films. The present invention is characterized in that the buried oxide films are annealed at a predetermined temperature within the range of 1100 to 1350.degree. C. before or after planarization of the semiconductor substrate such that ring structures of more than 5-fold ring and ring structures of less than 4-fold ring are formed at predetermined rates in the buried oxide films. The above annealing allows stress of the oxide film buried in the grooves to be relaxed. Hence, the generation of dislocation is suppressed.
摘要翻译：提供具有浅沟槽隔离（STI）结构的半导体衬底及其制造方法，即，在半导体衬底的预定位置选择性地形成沟槽并且使用有机硅源作为材料的氧化物膜的隔离衬底埋在凹槽中作为掩埋氧化膜。本发明的特征在于，在半导体衬底的平坦化之前或之后，在1100〜1350℃的范围内的预定温度下对所述埋入氧化物膜进行退火，使得所述半导体衬底的环结构超过5倍，在掩埋氧化膜中以预定的速率形成小于4倍的环。通过上述退火，能够缓和埋入槽内的氧化膜的应力。因此，错位的产生被抑制。

10. 发明授权

US5148457A System for analyzing metal impurity on the surface of a single crystal semiconductor by using total reflection of X-rays fluorescence 失效
标题翻译：利用X射线荧光全面反射分析单晶半导体表面金属杂质的系统
公开(公告)号：US5148457A
公开(公告)日：1992-09-15
申请号：US719706
申请日：1991-06-27
申请人： Atsuko Kubota , Norihiko Tsuchiya , Shuichi Samata , Yoshiaki Matsushita , Mokuji Kageyama
发明人： Atsuko Kubota , Norihiko Tsuchiya , Shuichi Samata , Yoshiaki Matsushita , Mokuji Kageyama
IPC分类号： G01N23/223
CPC分类号： G01N23/223 , G01N2223/076
摘要： A system for analyzing a metal impurity at the surface of a single crystal semiconductor comprising: an incident device for allowing X-ray to be incident, at an incident angle less than a total reflection angle, onto the surface of a wafer in the form of a thin plate comprised of a single crystal semiconductor (e.g., silicon); a wafer fixing/positioning stage wherein when it is assumed that the wafer surface is partitioned by a lattice having an interval d, and that the wavelength of the X-ray from the incident device is .lambda., an angle that the X-ray and the wafer surface form is .theta., and an arbitrary integer is n, the stage is adapted to fix the crystal orientation of the wafer so as to satisfy the condition of "2d sin .theta..noteq.n.lambda.", and to allow sample points to which X-ray is incident to be subjected to positioning by a horizontal movement; and analyzing device for measuring a light quantity of a fluorescent X-ray generated as the result of the fact that the incident X-ray excites atoms at the wafer surface to analyze a quantity of the metal impurity attached on the wafer surface under the condition that the Bragg reflection causing measurement noises does not take place.

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